LXR qemu/hw/char/bcm2835

   1/*
   2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
   3 * Copyright (c) 2015, Microsoft
   4 * Written by Andrew Baumann
   5 * Based on pl011.c, copyright terms below:
   6 *
   7 * Arm PrimeCell PL011 UART
   8 *
   9 * Copyright (c) 2006 CodeSourcery.
  10 * Written by Paul Brook
  11 *
  12 * This code is licensed under the GPL.
  13 *
  14 * At present only the core UART functions (data path for tx/rx) are
  15 * implemented. The following features/registers are unimplemented:
  16 *  - Line/modem control
  17 *  - Scratch register
  18 *  - Extra control
  19 *  - Baudrate
  20 *  - SPI interfaces
  21 */
  22
  23#include "qemu/osdep.h"
  24#include "hw/char/bcm2835_aux.h"
  25#include "qemu/log.h"
  26
  27#define AUX_IRQ         0x0
  28#define AUX_ENABLES     0x4
  29#define AUX_MU_IO_REG   0x40
  30#define AUX_MU_IER_REG  0x44
  31#define AUX_MU_IIR_REG  0x48
  32#define AUX_MU_LCR_REG  0x4c
  33#define AUX_MU_MCR_REG  0x50
  34#define AUX_MU_LSR_REG  0x54
  35#define AUX_MU_MSR_REG  0x58
  36#define AUX_MU_SCRATCH  0x5c
  37#define AUX_MU_CNTL_REG 0x60
  38#define AUX_MU_STAT_REG 0x64
  39#define AUX_MU_BAUD_REG 0x68
  40
  41/* bits in IER/IIR registers */
  42#define RX_INT  0x1
  43#define TX_INT  0x2
  44
  45static void bcm2835_aux_update(BCM2835AuxState *s)
  46{
  47    /* signal an interrupt if either:
  48     * 1. rx interrupt is enabled and we have a non-empty rx fifo, or
  49     * 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
  50     */
  51    s->iir = 0;
  52    if ((s->ier & RX_INT) && s->read_count != 0) {
  53        s->iir |= RX_INT;
  54    }
  55    if (s->ier & TX_INT) {
  56        s->iir |= TX_INT;
  57    }
  58    qemu_set_irq(s->irq, s->iir != 0);
  59}
  60
  61static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
  62{
  63    BCM2835AuxState *s = opaque;
  64    uint32_t c, res;
  65
  66    switch (offset) {
  67    case AUX_IRQ:
  68        return s->iir != 0;
  69
  70    case AUX_ENABLES:
  71        return 1; /* mini UART permanently enabled */
  72
  73    case AUX_MU_IO_REG:
  74        /* "DLAB bit set means access baudrate register" is NYI */
  75        c = s->read_fifo[s->read_pos];
  76        if (s->read_count > 0) {
  77            s->read_count--;
  78            if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
  79                s->read_pos = 0;
  80            }
  81        }
  82        qemu_chr_fe_accept_input(&s->chr);
  83        bcm2835_aux_update(s);
  84        return c;
  85
  86    case AUX_MU_IER_REG:
  87        /* "DLAB bit set means access baudrate register" is NYI */
  88        return 0xc0 | s->ier; /* FIFO enables always read 1 */
  89
  90    case AUX_MU_IIR_REG:
  91        res = 0xc0; /* FIFO enables */
  92        /* The spec is unclear on what happens when both tx and rx
  93         * interrupts are active, besides that this cannot occur. At
  94         * present, we choose to prioritise the rx interrupt, since
  95         * the tx fifo is always empty. */
  96        if (s->read_count != 0) {
  97            res |= 0x4;
  98        } else {
  99            res |= 0x2;
 100        }
 101        if (s->iir == 0) {
 102            res |= 0x1;
 103        }
 104        return res;
 105
 106    case AUX_MU_LCR_REG:
 107        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
 108        return 0;
 109
 110    case AUX_MU_MCR_REG:
 111        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
 112        return 0;
 113
 114    case AUX_MU_LSR_REG:
 115        res = 0x60; /* tx idle, empty */
 116        if (s->read_count != 0) {
 117            res |= 0x1;
 118        }
 119        return res;
 120
 121    case AUX_MU_MSR_REG:
 122        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
 123        return 0;
 124
 125    case AUX_MU_SCRATCH:
 126        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
 127        return 0;
 128
 129    case AUX_MU_CNTL_REG:
 130        return 0x3; /* tx, rx enabled */
 131
 132    case AUX_MU_STAT_REG:
 133        res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
 134        if (s->read_count > 0) {
 135            res |= 0x1; /* data in input buffer */
 136            assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
 137            res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
 138        }
 139        return res;
 140
 141    case AUX_MU_BAUD_REG:
 142        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
 143        return 0;
 144
 145    default:
 146        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 147                      __func__, offset);
 148        return 0;
 149    }
 150}
 151
 152static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
 153                              unsigned size)
 154{
 155    BCM2835AuxState *s = opaque;
 156    unsigned char ch;
 157
 158    switch (offset) {
 159    case AUX_ENABLES:
 160        if (value != 1) {
 161            qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
 162                          "or disable UART\n", __func__);
 163        }
 164        break;
 165
 166    case AUX_MU_IO_REG:
 167        /* "DLAB bit set means access baudrate register" is NYI */
 168        ch = value;
 169        /* XXX this blocks entire thread. Rewrite to use
 170         * qemu_chr_fe_write and background I/O callbacks */
 171        qemu_chr_fe_write_all(&s->chr, &ch, 1);
 172        break;
 173
 174    case AUX_MU_IER_REG:
 175        /* "DLAB bit set means access baudrate register" is NYI */
 176        s->ier = value & (TX_INT | RX_INT);
 177        bcm2835_aux_update(s);
 178        break;
 179
 180    case AUX_MU_IIR_REG:
 181        if (value & 0x2) {
 182            s->read_count = 0;
 183        }
 184        break;
 185
 186    case AUX_MU_LCR_REG:
 187        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
 188        break;
 189
 190    case AUX_MU_MCR_REG:
 191        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
 192        break;
 193
 194    case AUX_MU_SCRATCH:
 195        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
 196        break;
 197
 198    case AUX_MU_CNTL_REG:
 199        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
 200        break;
 201
 202    case AUX_MU_BAUD_REG:
 203        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
 204        break;
 205
 206    default:
 207        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 208                      __func__, offset);
 209    }
 210
 211    bcm2835_aux_update(s);
 212}
 213
 214static int bcm2835_aux_can_receive(void *opaque)
 215{
 216    BCM2835AuxState *s = opaque;
 217
 218    return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
 219}
 220
 221static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
 222{
 223    BCM2835AuxState *s = opaque;
 224    int slot;
 225
 226    slot = s->read_pos + s->read_count;
 227    if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
 228        slot -= BCM2835_AUX_RX_FIFO_LEN;
 229    }
 230    s->read_fifo[slot] = value;
 231    s->read_count++;
 232    if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
 233        /* buffer full */
 234    }
 235    bcm2835_aux_update(s);
 236}
 237
 238static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
 239{
 240    bcm2835_aux_put_fifo(opaque, *buf);
 241}
 242
 243static const MemoryRegionOps bcm2835_aux_ops = {
 244    .read = bcm2835_aux_read,
 245    .write = bcm2835_aux_write,
 246    .endianness = DEVICE_NATIVE_ENDIAN,
 247    .valid.min_access_size = 4,
 248    .valid.max_access_size = 4,
 249};
 250
 251static const VMStateDescription vmstate_bcm2835_aux = {
 252    .name = TYPE_BCM2835_AUX,
 253    .version_id = 1,
 254    .minimum_version_id = 1,
 255    .fields = (VMStateField[]) {
 256        VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
 257                            BCM2835_AUX_RX_FIFO_LEN),
 258        VMSTATE_UINT8(read_pos, BCM2835AuxState),
 259        VMSTATE_UINT8(read_count, BCM2835AuxState),
 260        VMSTATE_UINT8(ier, BCM2835AuxState),
 261        VMSTATE_UINT8(iir, BCM2835AuxState),
 262        VMSTATE_END_OF_LIST()
 263    }
 264};
 265
 266static void bcm2835_aux_init(Object *obj)
 267{
 268    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 269    BCM2835AuxState *s = BCM2835_AUX(obj);
 270
 271    memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
 272                          TYPE_BCM2835_AUX, 0x100);
 273    sysbus_init_mmio(sbd, &s->iomem);
 274    sysbus_init_irq(sbd, &s->irq);
 275}
 276
 277static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
 278{
 279    BCM2835AuxState *s = BCM2835_AUX(dev);
 280
 281    qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
 282                             bcm2835_aux_receive, NULL, NULL, s, NULL, true);
 283}
 284
 285static Property bcm2835_aux_props[] = {
 286    DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
 287    DEFINE_PROP_END_OF_LIST(),
 288};
 289
 290static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
 291{
 292    DeviceClass *dc = DEVICE_CLASS(oc);
 293
 294    dc->realize = bcm2835_aux_realize;
 295    dc->vmsd = &vmstate_bcm2835_aux;
 296    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 297    dc->props = bcm2835_aux_props;
 298}
 299
 300static const TypeInfo bcm2835_aux_info = {
 301    .name          = TYPE_BCM2835_AUX,
 302    .parent        = TYPE_SYS_BUS_DEVICE,
 303    .instance_size = sizeof(BCM2835AuxState),
 304    .instance_init = bcm2835_aux_init,
 305    .class_init    = bcm2835_aux_class_init,
 306};
 307
 308static void bcm2835_aux_register_types(void)
 309{
 310    type_register_static(&bcm2835_aux_info);
 311}
 312
 313type_init(bcm2835_aux_register_types)
 314