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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/mips/mips.h"
28#include "hw/mips/cpudevs.h"
29#include "hw/i386/pc.h"
30#include "hw/dma/i8257.h"
31#include "hw/char/serial.h"
32#include "hw/char/parallel.h"
33#include "hw/isa/isa.h"
34#include "hw/block/fdc.h"
35#include "sysemu/sysemu.h"
36#include "sysemu/arch_init.h"
37#include "hw/boards.h"
38#include "net/net.h"
39#include "hw/scsi/esp.h"
40#include "hw/mips/bios.h"
41#include "hw/loader.h"
42#include "hw/timer/mc146818rtc.h"
43#include "hw/timer/i8254.h"
44#include "hw/display/vga.h"
45#include "hw/audio/pcspk.h"
46#include "hw/input/i8042.h"
47#include "hw/sysbus.h"
48#include "exec/address-spaces.h"
49#include "sysemu/qtest.h"
50#include "qapi/error.h"
51#include "qemu/error-report.h"
52#include "qemu/help_option.h"
53
54enum jazz_model_e
55{
56 JAZZ_MAGNUM,
57 JAZZ_PICA61,
58};
59
60static void main_cpu_reset(void *opaque)
61{
62 MIPSCPU *cpu = opaque;
63
64 cpu_reset(CPU(cpu));
65}
66
67static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
68{
69 uint8_t val;
70 address_space_read(&address_space_memory, 0x90000071,
71 MEMTXATTRS_UNSPECIFIED, &val, 1);
72 return val;
73}
74
75static void rtc_write(void *opaque, hwaddr addr,
76 uint64_t val, unsigned size)
77{
78 uint8_t buf = val & 0xff;
79 address_space_write(&address_space_memory, 0x90000071,
80 MEMTXATTRS_UNSPECIFIED, &buf, 1);
81}
82
83static const MemoryRegionOps rtc_ops = {
84 .read = rtc_read,
85 .write = rtc_write,
86 .endianness = DEVICE_NATIVE_ENDIAN,
87};
88
89static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
90 unsigned size)
91{
92
93
94 return 0xff;
95}
96
97static void dma_dummy_write(void *opaque, hwaddr addr,
98 uint64_t val, unsigned size)
99{
100
101
102}
103
104static const MemoryRegionOps dma_dummy_ops = {
105 .read = dma_dummy_read,
106 .write = dma_dummy_write,
107 .endianness = DEVICE_NATIVE_ENDIAN,
108};
109
110#define MAGNUM_BIOS_SIZE_MAX 0x7e000
111#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
112
113static CPUUnassignedAccess real_do_unassigned_access;
114static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
115 bool is_write, bool is_exec,
116 int opaque, unsigned size)
117{
118 if (!is_exec) {
119
120 return;
121 }
122 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
123}
124
125static void mips_jazz_init(MachineState *machine,
126 enum jazz_model_e jazz_model)
127{
128 MemoryRegion *address_space = get_system_memory();
129 char *filename;
130 int bios_size, n;
131 MIPSCPU *cpu;
132 CPUClass *cc;
133 CPUMIPSState *env;
134 qemu_irq *i8259;
135 rc4030_dma *dmas;
136 IOMMUMemoryRegion *rc4030_dma_mr;
137 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
138 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
139 MemoryRegion *rtc = g_new(MemoryRegion, 1);
140 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
141 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
142 NICInfo *nd;
143 DeviceState *dev, *rc4030;
144 SysBusDevice *sysbus;
145 ISABus *isa_bus;
146 ISADevice *pit;
147 DriveInfo *fds[MAX_FD];
148 MemoryRegion *ram = g_new(MemoryRegion, 1);
149 MemoryRegion *bios = g_new(MemoryRegion, 1);
150 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
151 SysBusESPState *sysbus_esp;
152 ESPState *esp;
153
154
155 cpu = MIPS_CPU(cpu_create(machine->cpu_type));
156 env = &cpu->env;
157 qemu_register_reset(main_cpu_reset, cpu);
158
159
160
161
162
163
164
165
166 cc = CPU_GET_CLASS(cpu);
167 real_do_unassigned_access = cc->do_unassigned_access;
168 cc->do_unassigned_access = mips_jazz_do_unassigned_access;
169
170
171 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
172 machine->ram_size);
173 memory_region_add_subregion(address_space, 0, ram);
174
175 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
176 &error_fatal);
177 memory_region_set_readonly(bios, true);
178 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
179 0, MAGNUM_BIOS_SIZE);
180 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
181 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
182
183
184 if (bios_name == NULL)
185 bios_name = BIOS_FILENAME;
186 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
187 if (filename) {
188 bios_size = load_image_targphys(filename, 0xfff00000LL,
189 MAGNUM_BIOS_SIZE);
190 g_free(filename);
191 } else {
192 bios_size = -1;
193 }
194 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
195 error_report("Could not load MIPS bios '%s'", bios_name);
196 exit(1);
197 }
198
199
200 cpu_mips_irq_init_cpu(cpu);
201 cpu_mips_clock_init(cpu);
202
203
204 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
205 sysbus = SYS_BUS_DEVICE(rc4030);
206 sysbus_connect_irq(sysbus, 0, env->irq[6]);
207 sysbus_connect_irq(sysbus, 1, env->irq[3]);
208 memory_region_add_subregion(address_space, 0x80000000,
209 sysbus_mmio_get_region(sysbus, 0));
210 memory_region_add_subregion(address_space, 0xf0000000,
211 sysbus_mmio_get_region(sysbus, 1));
212 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
213 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
214
215
216 memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
217 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
218 memory_region_add_subregion(address_space, 0x90000000, isa_io);
219 memory_region_add_subregion(address_space, 0x91000000, isa_mem);
220 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
221
222
223 i8259 = i8259_init(isa_bus, env->irq[4]);
224 isa_bus_irqs(isa_bus, i8259);
225 i8257_dma_init(isa_bus, 0);
226 pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
227 pcspk_init(isa_bus, pit);
228
229
230 switch (jazz_model) {
231 case JAZZ_MAGNUM:
232 dev = qdev_create(NULL, "sysbus-g364");
233 qdev_init_nofail(dev);
234 sysbus = SYS_BUS_DEVICE(dev);
235 sysbus_mmio_map(sysbus, 0, 0x60080000);
236 sysbus_mmio_map(sysbus, 1, 0x40000000);
237 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
238 {
239
240 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
241 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
242 &error_fatal);
243 memory_region_set_readonly(rom_mr, true);
244 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
245 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
246 rom[0] = 0x10;
247 }
248 break;
249 case JAZZ_PICA61:
250 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
251 break;
252 default:
253 break;
254 }
255
256
257 for (n = 0; n < nb_nics; n++) {
258 nd = &nd_table[n];
259 if (!nd->model)
260 nd->model = g_strdup("dp83932");
261 if (strcmp(nd->model, "dp83932") == 0) {
262 qemu_check_nic_model(nd, "dp83932");
263
264 dev = qdev_create(NULL, "dp8393x");
265 qdev_set_nic_properties(dev, nd);
266 qdev_prop_set_uint8(dev, "it_shift", 2);
267 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
268 qdev_init_nofail(dev);
269 sysbus = SYS_BUS_DEVICE(dev);
270 sysbus_mmio_map(sysbus, 0, 0x80001000);
271 sysbus_mmio_map(sysbus, 1, 0x8000b000);
272 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
273 break;
274 } else if (is_help_option(nd->model)) {
275 error_report("Supported NICs: dp83932");
276 exit(1);
277 } else {
278 error_report("Unsupported NIC: %s", nd->model);
279 exit(1);
280 }
281 }
282
283
284 dev = qdev_create(NULL, TYPE_ESP);
285 sysbus_esp = ESP_STATE(dev);
286 esp = &sysbus_esp->esp;
287 esp->dma_memory_read = rc4030_dma_read;
288 esp->dma_memory_write = rc4030_dma_write;
289 esp->dma_opaque = dmas[0];
290 sysbus_esp->it_shift = 0;
291
292 esp->dma_enabled = 1;
293 qdev_init_nofail(dev);
294
295 sysbus = SYS_BUS_DEVICE(dev);
296 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
297 sysbus_mmio_map(sysbus, 0, 0x80002000);
298
299 scsi_bus_legacy_handle_cmdline(&esp->bus);
300
301
302 for (n = 0; n < MAX_FD; n++) {
303 fds[n] = drive_get(IF_FLOPPY, 0, n);
304 }
305
306 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
307
308
309 mc146818_rtc_init(isa_bus, 1980, NULL);
310 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
311 memory_region_add_subregion(address_space, 0x80004000, rtc);
312
313
314 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
315 i8042, 0x1000, 0x1);
316 memory_region_add_subregion(address_space, 0x80005000, i8042);
317
318
319 if (serial_hd(0)) {
320 serial_mm_init(address_space, 0x80006000, 0,
321 qdev_get_gpio_in(rc4030, 8), 8000000/16,
322 serial_hd(0), DEVICE_NATIVE_ENDIAN);
323 }
324 if (serial_hd(1)) {
325 serial_mm_init(address_space, 0x80007000, 0,
326 qdev_get_gpio_in(rc4030, 9), 8000000/16,
327 serial_hd(1), DEVICE_NATIVE_ENDIAN);
328 }
329
330
331 if (parallel_hds[0])
332 parallel_mm_init(address_space, 0x80008000, 0,
333 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
334
335
336
337
338 dev = qdev_create(NULL, "ds1225y");
339 qdev_init_nofail(dev);
340 sysbus = SYS_BUS_DEVICE(dev);
341 sysbus_mmio_map(sysbus, 0, 0x80009000);
342
343
344 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
345}
346
347static
348void mips_magnum_init(MachineState *machine)
349{
350 mips_jazz_init(machine, JAZZ_MAGNUM);
351}
352
353static
354void mips_pica61_init(MachineState *machine)
355{
356 mips_jazz_init(machine, JAZZ_PICA61);
357}
358
359static void mips_magnum_class_init(ObjectClass *oc, void *data)
360{
361 MachineClass *mc = MACHINE_CLASS(oc);
362
363 mc->desc = "MIPS Magnum";
364 mc->init = mips_magnum_init;
365 mc->block_default_type = IF_SCSI;
366 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
367}
368
369static const TypeInfo mips_magnum_type = {
370 .name = MACHINE_TYPE_NAME("magnum"),
371 .parent = TYPE_MACHINE,
372 .class_init = mips_magnum_class_init,
373};
374
375static void mips_pica61_class_init(ObjectClass *oc, void *data)
376{
377 MachineClass *mc = MACHINE_CLASS(oc);
378
379 mc->desc = "Acer Pica 61";
380 mc->init = mips_pica61_init;
381 mc->block_default_type = IF_SCSI;
382 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
383}
384
385static const TypeInfo mips_pica61_type = {
386 .name = MACHINE_TYPE_NAME("pica61"),
387 .parent = TYPE_MACHINE,
388 .class_init = mips_pica61_class_init,
389};
390
391static void mips_jazz_machine_init(void)
392{
393 type_register_static(&mips_magnum_type);
394 type_register_static(&mips_pica61_type);
395}
396
397type_init(mips_jazz_machine_init)
398
