1
2
3
4
5
6
7
8
9
10
11
12#include "qemu/osdep.h"
13#include "qemu/bitops.h"
14#include "sysemu/watchdog.h"
15
16#include "hw/misc/imx2_wdt.h"
17
18#define IMX2_WDT_WCR_WDA BIT(5)
19#define IMX2_WDT_WCR_SRS BIT(4)
20
21static uint64_t imx2_wdt_read(void *opaque, hwaddr addr,
22 unsigned int size)
23{
24 return 0;
25}
26
27static void imx2_wdt_write(void *opaque, hwaddr addr,
28 uint64_t value, unsigned int size)
29{
30 if (addr == IMX2_WDT_WCR &&
31 (value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
32 watchdog_perform_action();
33 }
34}
35
36static const MemoryRegionOps imx2_wdt_ops = {
37 .read = imx2_wdt_read,
38 .write = imx2_wdt_write,
39 .endianness = DEVICE_NATIVE_ENDIAN,
40 .impl = {
41
42
43
44
45
46
47 .min_access_size = 4,
48 .max_access_size = 4,
49 .unaligned = false,
50 },
51};
52
53static void imx2_wdt_realize(DeviceState *dev, Error **errp)
54{
55 IMX2WdtState *s = IMX2_WDT(dev);
56
57 memory_region_init_io(&s->mmio, OBJECT(dev),
58 &imx2_wdt_ops, s,
59 TYPE_IMX2_WDT".mmio",
60 IMX2_WDT_REG_NUM * sizeof(uint16_t));
61 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
62}
63
64static void imx2_wdt_class_init(ObjectClass *klass, void *data)
65{
66 DeviceClass *dc = DEVICE_CLASS(klass);
67
68 dc->realize = imx2_wdt_realize;
69 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
70}
71
72static const TypeInfo imx2_wdt_info = {
73 .name = TYPE_IMX2_WDT,
74 .parent = TYPE_SYS_BUS_DEVICE,
75 .instance_size = sizeof(IMX2WdtState),
76 .class_init = imx2_wdt_class_init,
77};
78
79static WatchdogTimerModel model = {
80 .wdt_name = "imx2-watchdog",
81 .wdt_description = "i.MX2 Watchdog",
82};
83
84static void imx2_wdt_register_type(void)
85{
86 watchdog_add_model(&model);
87 type_register_static(&imx2_wdt_info);
88}
89type_init(imx2_wdt_register_type)
90