LXR qemu/hw/misc/stm32f2xx

   1/*
   2 * STM32F2XX SYSCFG
   3 *
   4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/misc/stm32f2xx_syscfg.h"
  27#include "qemu/log.h"
  28
  29#ifndef STM_SYSCFG_ERR_DEBUG
  30#define STM_SYSCFG_ERR_DEBUG 0
  31#endif
  32
  33#define DB_PRINT_L(lvl, fmt, args...) do { \
  34    if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
  35        qemu_log("%s: " fmt, __func__, ## args); \
  36    } \
  37} while (0)
  38
  39#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  40
  41static void stm32f2xx_syscfg_reset(DeviceState *dev)
  42{
  43    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
  44
  45    s->syscfg_memrmp = 0x00000000;
  46    s->syscfg_pmc = 0x00000000;
  47    s->syscfg_exticr1 = 0x00000000;
  48    s->syscfg_exticr2 = 0x00000000;
  49    s->syscfg_exticr3 = 0x00000000;
  50    s->syscfg_exticr4 = 0x00000000;
  51    s->syscfg_cmpcr = 0x00000000;
  52}
  53
  54static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
  55                                     unsigned int size)
  56{
  57    STM32F2XXSyscfgState *s = opaque;
  58
  59    DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
  60
  61    switch (addr) {
  62    case SYSCFG_MEMRMP:
  63        return s->syscfg_memrmp;
  64    case SYSCFG_PMC:
  65        return s->syscfg_pmc;
  66    case SYSCFG_EXTICR1:
  67        return s->syscfg_exticr1;
  68    case SYSCFG_EXTICR2:
  69        return s->syscfg_exticr2;
  70    case SYSCFG_EXTICR3:
  71        return s->syscfg_exticr3;
  72    case SYSCFG_EXTICR4:
  73        return s->syscfg_exticr4;
  74    case SYSCFG_CMPCR:
  75        return s->syscfg_cmpcr;
  76    default:
  77        qemu_log_mask(LOG_GUEST_ERROR,
  78                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
  79        return 0;
  80    }
  81
  82    return 0;
  83}
  84
  85static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
  86                       uint64_t val64, unsigned int size)
  87{
  88    STM32F2XXSyscfgState *s = opaque;
  89    uint32_t value = val64;
  90
  91    DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
  92
  93    switch (addr) {
  94    case SYSCFG_MEMRMP:
  95        qemu_log_mask(LOG_UNIMP,
  96                      "%s: Changeing the memory mapping isn't supported " \
  97                      "in QEMU\n", __func__);
  98        return;
  99    case SYSCFG_PMC:
 100        qemu_log_mask(LOG_UNIMP,
 101                      "%s: Changeing the memory mapping isn't supported " \
 102                      "in QEMU\n", __func__);
 103        return;
 104    case SYSCFG_EXTICR1:
 105        s->syscfg_exticr1 = (value & 0xFFFF);
 106        return;
 107    case SYSCFG_EXTICR2:
 108        s->syscfg_exticr2 = (value & 0xFFFF);
 109        return;
 110    case SYSCFG_EXTICR3:
 111        s->syscfg_exticr3 = (value & 0xFFFF);
 112        return;
 113    case SYSCFG_EXTICR4:
 114        s->syscfg_exticr4 = (value & 0xFFFF);
 115        return;
 116    case SYSCFG_CMPCR:
 117        s->syscfg_cmpcr = value;
 118        return;
 119    default:
 120        qemu_log_mask(LOG_GUEST_ERROR,
 121                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 122    }
 123}
 124
 125static const MemoryRegionOps stm32f2xx_syscfg_ops = {
 126    .read = stm32f2xx_syscfg_read,
 127    .write = stm32f2xx_syscfg_write,
 128    .endianness = DEVICE_NATIVE_ENDIAN,
 129};
 130
 131static void stm32f2xx_syscfg_init(Object *obj)
 132{
 133    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
 134
 135    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 136
 137    memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
 138                          TYPE_STM32F2XX_SYSCFG, 0x400);
 139    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 140}
 141
 142static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
 143{
 144    DeviceClass *dc = DEVICE_CLASS(klass);
 145
 146    dc->reset = stm32f2xx_syscfg_reset;
 147}
 148
 149static const TypeInfo stm32f2xx_syscfg_info = {
 150    .name          = TYPE_STM32F2XX_SYSCFG,
 151    .parent        = TYPE_SYS_BUS_DEVICE,
 152    .instance_size = sizeof(STM32F2XXSyscfgState),
 153    .instance_init = stm32f2xx_syscfg_init,
 154    .class_init    = stm32f2xx_syscfg_class_init,
 155};
 156
 157static void stm32f2xx_syscfg_register_types(void)
 158{
 159    type_register_static(&stm32f2xx_syscfg_info);
 160}
 161
 162type_init(stm32f2xx_syscfg_register_types)
 163