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32#include "qemu/osdep.h"
33#include "qemu/event_notifier.h"
34#include "qemu/thread.h"
35#include "qemu/sockets.h"
36#include "qapi/error.h"
37#include "chardev/char.h"
38#include "hw/hw.h"
39#include "hw/pci/pci.h"
40#include "net/can_emu.h"
41
42#include "can_sja1000.h"
43
44#define TYPE_CAN_PCI_DEV "kvaser_pci"
45
46#define KVASER_PCI_DEV(obj) \
47 OBJECT_CHECK(KvaserPCIState, (obj), TYPE_CAN_PCI_DEV)
48
49#ifndef KVASER_PCI_VENDOR_ID1
50#define KVASER_PCI_VENDOR_ID1 0x10e8
51#endif
52
53#ifndef KVASER_PCI_DEVICE_ID1
54#define KVASER_PCI_DEVICE_ID1 0x8406
55#endif
56
57#define KVASER_PCI_S5920_RANGE 0x80
58#define KVASER_PCI_SJA_RANGE 0x80
59#define KVASER_PCI_XILINX_RANGE 0x8
60
61#define KVASER_PCI_BYTES_PER_SJA 0x20
62
63#define S5920_OMB 0x0C
64#define S5920_IMB 0x1C
65#define S5920_MBEF 0x34
66#define S5920_INTCSR 0x38
67#define S5920_RCR 0x3C
68#define S5920_PTCR 0x60
69
70#define S5920_INTCSR_ADDON_INTENABLE_M 0x2000
71#define S5920_INTCSR_INTERRUPT_ASSERTED_M 0x800000
72
73#define KVASER_PCI_XILINX_VERINT 7
74
75
76#define KVASER_PCI_XILINX_VERSION_NUMBER 13
77
78typedef struct KvaserPCIState {
79
80 PCIDevice dev;
81
82 MemoryRegion s5920_io;
83 MemoryRegion sja_io;
84 MemoryRegion xilinx_io;
85
86 CanSJA1000State sja_state;
87 qemu_irq irq;
88
89 uint32_t s5920_intcsr;
90 uint32_t s5920_irqstate;
91
92 CanBusState *canbus;
93} KvaserPCIState;
94
95static void kvaser_pci_irq_handler(void *opaque, int irq_num, int level)
96{
97 KvaserPCIState *d = (KvaserPCIState *)opaque;
98
99 d->s5920_irqstate = level;
100 if (d->s5920_intcsr & S5920_INTCSR_ADDON_INTENABLE_M) {
101 pci_set_irq(&d->dev, level);
102 }
103}
104
105static void kvaser_pci_reset(DeviceState *dev)
106{
107 KvaserPCIState *d = KVASER_PCI_DEV(dev);
108 CanSJA1000State *s = &d->sja_state;
109
110 can_sja_hardware_reset(s);
111}
112
113static uint64_t kvaser_pci_s5920_io_read(void *opaque, hwaddr addr,
114 unsigned size)
115{
116 KvaserPCIState *d = opaque;
117 uint64_t val;
118
119 switch (addr) {
120 case S5920_INTCSR:
121 val = d->s5920_intcsr;
122 val &= ~S5920_INTCSR_INTERRUPT_ASSERTED_M;
123 if (d->s5920_irqstate) {
124 val |= S5920_INTCSR_INTERRUPT_ASSERTED_M;
125 }
126 return val;
127 }
128 return 0;
129}
130
131static void kvaser_pci_s5920_io_write(void *opaque, hwaddr addr, uint64_t data,
132 unsigned size)
133{
134 KvaserPCIState *d = opaque;
135
136 switch (addr) {
137 case S5920_INTCSR:
138 if (d->s5920_irqstate &&
139 ((d->s5920_intcsr ^ data) & S5920_INTCSR_ADDON_INTENABLE_M)) {
140 pci_set_irq(&d->dev, !!(data & S5920_INTCSR_ADDON_INTENABLE_M));
141 }
142 d->s5920_intcsr = data;
143 break;
144 }
145}
146
147static uint64_t kvaser_pci_sja_io_read(void *opaque, hwaddr addr, unsigned size)
148{
149 KvaserPCIState *d = opaque;
150 CanSJA1000State *s = &d->sja_state;
151
152 if (addr >= KVASER_PCI_BYTES_PER_SJA) {
153 return 0;
154 }
155
156 return can_sja_mem_read(s, addr, size);
157}
158
159static void kvaser_pci_sja_io_write(void *opaque, hwaddr addr, uint64_t data,
160 unsigned size)
161{
162 KvaserPCIState *d = opaque;
163 CanSJA1000State *s = &d->sja_state;
164
165 if (addr >= KVASER_PCI_BYTES_PER_SJA) {
166 return;
167 }
168
169 can_sja_mem_write(s, addr, data, size);
170}
171
172static uint64_t kvaser_pci_xilinx_io_read(void *opaque, hwaddr addr,
173 unsigned size)
174{
175 switch (addr) {
176 case KVASER_PCI_XILINX_VERINT:
177 return (KVASER_PCI_XILINX_VERSION_NUMBER << 4) | 0;
178 }
179
180 return 0;
181}
182
183static void kvaser_pci_xilinx_io_write(void *opaque, hwaddr addr, uint64_t data,
184 unsigned size)
185{
186
187}
188
189static const MemoryRegionOps kvaser_pci_s5920_io_ops = {
190 .read = kvaser_pci_s5920_io_read,
191 .write = kvaser_pci_s5920_io_write,
192 .endianness = DEVICE_LITTLE_ENDIAN,
193 .impl = {
194 .min_access_size = 4,
195 .max_access_size = 4,
196 },
197};
198
199static const MemoryRegionOps kvaser_pci_sja_io_ops = {
200 .read = kvaser_pci_sja_io_read,
201 .write = kvaser_pci_sja_io_write,
202 .endianness = DEVICE_LITTLE_ENDIAN,
203 .impl = {
204 .max_access_size = 1,
205 },
206};
207
208static const MemoryRegionOps kvaser_pci_xilinx_io_ops = {
209 .read = kvaser_pci_xilinx_io_read,
210 .write = kvaser_pci_xilinx_io_write,
211 .endianness = DEVICE_LITTLE_ENDIAN,
212 .impl = {
213 .max_access_size = 1,
214 },
215};
216
217static void kvaser_pci_realize(PCIDevice *pci_dev, Error **errp)
218{
219 KvaserPCIState *d = KVASER_PCI_DEV(pci_dev);
220 CanSJA1000State *s = &d->sja_state;
221 uint8_t *pci_conf;
222
223 pci_conf = pci_dev->config;
224 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
225
226 d->irq = qemu_allocate_irq(kvaser_pci_irq_handler, d, 0);
227
228 can_sja_init(s, d->irq);
229
230 if (can_sja_connect_to_bus(s, d->canbus) < 0) {
231 error_setg(errp, "can_sja_connect_to_bus failed");
232 return;
233 }
234
235 memory_region_init_io(&d->s5920_io, OBJECT(d), &kvaser_pci_s5920_io_ops,
236 d, "kvaser_pci-s5920", KVASER_PCI_S5920_RANGE);
237 memory_region_init_io(&d->sja_io, OBJECT(d), &kvaser_pci_sja_io_ops,
238 d, "kvaser_pci-sja", KVASER_PCI_SJA_RANGE);
239 memory_region_init_io(&d->xilinx_io, OBJECT(d), &kvaser_pci_xilinx_io_ops,
240 d, "kvaser_pci-xilinx", KVASER_PCI_XILINX_RANGE);
241
242 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO,
243 &d->s5920_io);
244 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
245 &d->sja_io);
246 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_IO,
247 &d->xilinx_io);
248}
249
250static void kvaser_pci_exit(PCIDevice *pci_dev)
251{
252 KvaserPCIState *d = KVASER_PCI_DEV(pci_dev);
253 CanSJA1000State *s = &d->sja_state;
254
255 can_sja_disconnect(s);
256
257 qemu_free_irq(d->irq);
258}
259
260static const VMStateDescription vmstate_kvaser_pci = {
261 .name = "kvaser_pci",
262 .version_id = 1,
263 .minimum_version_id = 1,
264 .minimum_version_id_old = 1,
265 .fields = (VMStateField[]) {
266 VMSTATE_PCI_DEVICE(dev, KvaserPCIState),
267
268 VMSTATE_UINT32(s5920_intcsr, KvaserPCIState),
269 VMSTATE_STRUCT(sja_state, KvaserPCIState, 0, vmstate_can_sja,
270 CanSJA1000State),
271 VMSTATE_END_OF_LIST()
272 }
273};
274
275static void kvaser_pci_instance_init(Object *obj)
276{
277 KvaserPCIState *d = KVASER_PCI_DEV(obj);
278
279 object_property_add_link(obj, "canbus", TYPE_CAN_BUS,
280 (Object **)&d->canbus,
281 qdev_prop_allow_set_link_before_realize,
282 0, &error_abort);
283}
284
285static void kvaser_pci_class_init(ObjectClass *klass, void *data)
286{
287 DeviceClass *dc = DEVICE_CLASS(klass);
288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
289
290 k->realize = kvaser_pci_realize;
291 k->exit = kvaser_pci_exit;
292 k->vendor_id = KVASER_PCI_VENDOR_ID1;
293 k->device_id = KVASER_PCI_DEVICE_ID1;
294 k->revision = 0x00;
295 k->class_id = 0x00ff00;
296 dc->desc = "Kvaser PCICANx";
297 dc->vmsd = &vmstate_kvaser_pci;
298 dc->reset = kvaser_pci_reset;
299 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
300}
301
302static const TypeInfo kvaser_pci_info = {
303 .name = TYPE_CAN_PCI_DEV,
304 .parent = TYPE_PCI_DEVICE,
305 .instance_size = sizeof(KvaserPCIState),
306 .class_init = kvaser_pci_class_init,
307 .instance_init = kvaser_pci_instance_init,
308 .interfaces = (InterfaceInfo[]) {
309 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
310 { },
311 },
312};
313
314static void kvaser_pci_register_types(void)
315{
316 type_register_static(&kvaser_pci_info);
317}
318
319type_init(kvaser_pci_register_types)
320
