1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_bridge.h"
29#include "hw/pci/pci_bus.h"
30#include "hw/pci/pci_host.h"
31#include "monitor/monitor.h"
32#include "net/net.h"
33#include "sysemu/sysemu.h"
34#include "hw/loader.h"
35#include "qemu/error-report.h"
36#include "qemu/range.h"
37#include "trace.h"
38#include "hw/pci/msi.h"
39#include "hw/pci/msix.h"
40#include "exec/address-spaces.h"
41#include "hw/hotplug.h"
42#include "hw/boards.h"
43#include "qapi/error.h"
44#include "qapi/qapi-commands-misc.h"
45#include "qemu/cutils.h"
46
47
48#ifdef DEBUG_PCI
49# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
50#else
51# define PCI_DPRINTF(format, ...) do { } while (0)
52#endif
53
54bool pci_available = true;
55
56static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
57static char *pcibus_get_dev_path(DeviceState *dev);
58static char *pcibus_get_fw_dev_path(DeviceState *dev);
59static void pcibus_reset(BusState *qbus);
60
61static Property pci_props[] = {
62 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
63 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
64 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
65 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
66 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
67 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
68 QEMU_PCI_CAP_SERR_BITNR, true),
69 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
70 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
71 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
72 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
73 DEFINE_PROP_END_OF_LIST()
74};
75
76static const VMStateDescription vmstate_pcibus = {
77 .name = "PCIBUS",
78 .version_id = 1,
79 .minimum_version_id = 1,
80 .fields = (VMStateField[]) {
81 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
82 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
83 nirq, 0, vmstate_info_int32,
84 int32_t),
85 VMSTATE_END_OF_LIST()
86 }
87};
88
89static void pci_init_bus_master(PCIDevice *pci_dev)
90{
91 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
92
93 memory_region_init_alias(&pci_dev->bus_master_enable_region,
94 OBJECT(pci_dev), "bus master",
95 dma_as->root, 0, memory_region_size(dma_as->root));
96 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
97 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
98 &pci_dev->bus_master_enable_region);
99}
100
101static void pcibus_machine_done(Notifier *notifier, void *data)
102{
103 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
104 int i;
105
106 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
107 if (bus->devices[i]) {
108 pci_init_bus_master(bus->devices[i]);
109 }
110 }
111}
112
113static void pci_bus_realize(BusState *qbus, Error **errp)
114{
115 PCIBus *bus = PCI_BUS(qbus);
116
117 bus->machine_done.notify = pcibus_machine_done;
118 qemu_add_machine_init_done_notifier(&bus->machine_done);
119
120 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
121}
122
123static void pci_bus_unrealize(BusState *qbus, Error **errp)
124{
125 PCIBus *bus = PCI_BUS(qbus);
126
127 qemu_remove_machine_init_done_notifier(&bus->machine_done);
128
129 vmstate_unregister(NULL, &vmstate_pcibus, bus);
130}
131
132static bool pcibus_is_root(PCIBus *bus)
133{
134 return !bus->parent_dev;
135}
136
137static int pcibus_num(PCIBus *bus)
138{
139 if (pcibus_is_root(bus)) {
140 return 0;
141 }
142 return bus->parent_dev->config[PCI_SECONDARY_BUS];
143}
144
145static uint16_t pcibus_numa_node(PCIBus *bus)
146{
147 return NUMA_NODE_UNASSIGNED;
148}
149
150static void pci_bus_class_init(ObjectClass *klass, void *data)
151{
152 BusClass *k = BUS_CLASS(klass);
153 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
154
155 k->print_dev = pcibus_dev_print;
156 k->get_dev_path = pcibus_get_dev_path;
157 k->get_fw_dev_path = pcibus_get_fw_dev_path;
158 k->realize = pci_bus_realize;
159 k->unrealize = pci_bus_unrealize;
160 k->reset = pcibus_reset;
161
162 pbc->is_root = pcibus_is_root;
163 pbc->bus_num = pcibus_num;
164 pbc->numa_node = pcibus_numa_node;
165}
166
167static const TypeInfo pci_bus_info = {
168 .name = TYPE_PCI_BUS,
169 .parent = TYPE_BUS,
170 .instance_size = sizeof(PCIBus),
171 .class_size = sizeof(PCIBusClass),
172 .class_init = pci_bus_class_init,
173};
174
175static const TypeInfo pcie_interface_info = {
176 .name = INTERFACE_PCIE_DEVICE,
177 .parent = TYPE_INTERFACE,
178};
179
180static const TypeInfo conventional_pci_interface_info = {
181 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
182 .parent = TYPE_INTERFACE,
183};
184
185static const TypeInfo pcie_bus_info = {
186 .name = TYPE_PCIE_BUS,
187 .parent = TYPE_PCI_BUS,
188};
189
190static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
191static void pci_update_mappings(PCIDevice *d);
192static void pci_irq_handler(void *opaque, int irq_num, int level);
193static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
194static void pci_del_option_rom(PCIDevice *pdev);
195
196static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
197static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
198
199static QLIST_HEAD(, PCIHostState) pci_host_bridges;
200
201int pci_bar(PCIDevice *d, int reg)
202{
203 uint8_t type;
204
205 if (reg != PCI_ROM_SLOT)
206 return PCI_BASE_ADDRESS_0 + reg * 4;
207
208 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
209 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
210}
211
212static inline int pci_irq_state(PCIDevice *d, int irq_num)
213{
214 return (d->irq_state >> irq_num) & 0x1;
215}
216
217static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
218{
219 d->irq_state &= ~(0x1 << irq_num);
220 d->irq_state |= level << irq_num;
221}
222
223static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
224{
225 PCIBus *bus;
226 for (;;) {
227 bus = pci_get_bus(pci_dev);
228 irq_num = bus->map_irq(pci_dev, irq_num);
229 if (bus->set_irq)
230 break;
231 pci_dev = bus->parent_dev;
232 }
233 bus->irq_count[irq_num] += change;
234 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
235}
236
237int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
238{
239 assert(irq_num >= 0);
240 assert(irq_num < bus->nirq);
241 return !!bus->irq_count[irq_num];
242}
243
244
245
246static void pci_update_irq_status(PCIDevice *dev)
247{
248 if (dev->irq_state) {
249 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
250 } else {
251 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
252 }
253}
254
255void pci_device_deassert_intx(PCIDevice *dev)
256{
257 int i;
258 for (i = 0; i < PCI_NUM_PINS; ++i) {
259 pci_irq_handler(dev, i, 0);
260 }
261}
262
263static void pci_do_device_reset(PCIDevice *dev)
264{
265 int r;
266
267 pci_device_deassert_intx(dev);
268 assert(dev->irq_state == 0);
269
270
271 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
272 pci_get_word(dev->wmask + PCI_COMMAND) |
273 pci_get_word(dev->w1cmask + PCI_COMMAND));
274 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
275 pci_get_word(dev->wmask + PCI_STATUS) |
276 pci_get_word(dev->w1cmask + PCI_STATUS));
277 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
278 dev->config[PCI_INTERRUPT_LINE] = 0x0;
279 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
280 PCIIORegion *region = &dev->io_regions[r];
281 if (!region->size) {
282 continue;
283 }
284
285 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
286 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
287 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
288 } else {
289 pci_set_long(dev->config + pci_bar(dev, r), region->type);
290 }
291 }
292 pci_update_mappings(dev);
293
294 msi_reset(dev);
295 msix_reset(dev);
296}
297
298
299
300
301
302void pci_device_reset(PCIDevice *dev)
303{
304 qdev_reset_all(&dev->qdev);
305 pci_do_device_reset(dev);
306}
307
308
309
310
311
312
313static void pcibus_reset(BusState *qbus)
314{
315 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
316 int i;
317
318 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
319 if (bus->devices[i]) {
320 pci_do_device_reset(bus->devices[i]);
321 }
322 }
323
324 for (i = 0; i < bus->nirq; i++) {
325 assert(bus->irq_count[i] == 0);
326 }
327}
328
329static void pci_host_bus_register(DeviceState *host)
330{
331 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
332
333 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
334}
335
336PCIBus *pci_device_root_bus(const PCIDevice *d)
337{
338 PCIBus *bus = pci_get_bus(d);
339
340 while (!pci_bus_is_root(bus)) {
341 d = bus->parent_dev;
342 assert(d != NULL);
343
344 bus = pci_get_bus(d);
345 }
346
347 return bus;
348}
349
350const char *pci_root_bus_path(PCIDevice *dev)
351{
352 PCIBus *rootbus = pci_device_root_bus(dev);
353 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
354 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
355
356 assert(host_bridge->bus == rootbus);
357
358 if (hc->root_bus_path) {
359 return (*hc->root_bus_path)(host_bridge, rootbus);
360 }
361
362 return rootbus->qbus.name;
363}
364
365static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
366 MemoryRegion *address_space_mem,
367 MemoryRegion *address_space_io,
368 uint8_t devfn_min)
369{
370 assert(PCI_FUNC(devfn_min) == 0);
371 bus->devfn_min = devfn_min;
372 bus->slot_reserved_mask = 0x0;
373 bus->address_space_mem = address_space_mem;
374 bus->address_space_io = address_space_io;
375
376
377 QLIST_INIT(&bus->child);
378
379 pci_host_bus_register(parent);
380}
381
382bool pci_bus_is_express(PCIBus *bus)
383{
384 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
385}
386
387bool pci_bus_is_root(PCIBus *bus)
388{
389 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
390}
391
392void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
393 const char *name,
394 MemoryRegion *address_space_mem,
395 MemoryRegion *address_space_io,
396 uint8_t devfn_min, const char *typename)
397{
398 qbus_create_inplace(bus, bus_size, typename, parent, name);
399 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
400 devfn_min);
401}
402
403PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename)
407{
408 PCIBus *bus;
409
410 bus = PCI_BUS(qbus_create(typename, parent, name));
411 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
412 devfn_min);
413 return bus;
414}
415
416void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
417 void *irq_opaque, int nirq)
418{
419 bus->set_irq = set_irq;
420 bus->map_irq = map_irq;
421 bus->irq_opaque = irq_opaque;
422 bus->nirq = nirq;
423 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
424}
425
426PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
427 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
428 void *irq_opaque,
429 MemoryRegion *address_space_mem,
430 MemoryRegion *address_space_io,
431 uint8_t devfn_min, int nirq,
432 const char *typename)
433{
434 PCIBus *bus;
435
436 bus = pci_root_bus_new(parent, name, address_space_mem,
437 address_space_io, devfn_min, typename);
438 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
439 return bus;
440}
441
442int pci_bus_num(PCIBus *s)
443{
444 return PCI_BUS_GET_CLASS(s)->bus_num(s);
445}
446
447int pci_bus_numa_node(PCIBus *bus)
448{
449 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
450}
451
452static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
453 VMStateField *field)
454{
455 PCIDevice *s = container_of(pv, PCIDevice, config);
456 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
457 uint8_t *config;
458 int i;
459
460 assert(size == pci_config_size(s));
461 config = g_malloc(size);
462
463 qemu_get_buffer(f, config, size);
464 for (i = 0; i < size; ++i) {
465 if ((config[i] ^ s->config[i]) &
466 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
467 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
468 "cmask: %x wmask: %x w1cmask:%x", __func__,
469 i, config[i], s->config[i],
470 s->cmask[i], s->wmask[i], s->w1cmask[i]);
471 g_free(config);
472 return -EINVAL;
473 }
474 }
475 memcpy(s->config, config, size);
476
477 pci_update_mappings(s);
478 if (pc->is_bridge) {
479 PCIBridge *b = PCI_BRIDGE(s);
480 pci_bridge_update_mappings(b);
481 }
482
483 memory_region_set_enabled(&s->bus_master_enable_region,
484 pci_get_word(s->config + PCI_COMMAND)
485 & PCI_COMMAND_MASTER);
486
487 g_free(config);
488 return 0;
489}
490
491
492static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
493 VMStateField *field, QJSON *vmdesc)
494{
495 const uint8_t **v = pv;
496 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
497 qemu_put_buffer(f, *v, size);
498
499 return 0;
500}
501
502static VMStateInfo vmstate_info_pci_config = {
503 .name = "pci config",
504 .get = get_pci_config_device,
505 .put = put_pci_config_device,
506};
507
508static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
509 VMStateField *field)
510{
511 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
512 uint32_t irq_state[PCI_NUM_PINS];
513 int i;
514 for (i = 0; i < PCI_NUM_PINS; ++i) {
515 irq_state[i] = qemu_get_be32(f);
516 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
517 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
518 irq_state[i]);
519 return -EINVAL;
520 }
521 }
522
523 for (i = 0; i < PCI_NUM_PINS; ++i) {
524 pci_set_irq_state(s, i, irq_state[i]);
525 }
526
527 return 0;
528}
529
530static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
531 VMStateField *field, QJSON *vmdesc)
532{
533 int i;
534 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
535
536 for (i = 0; i < PCI_NUM_PINS; ++i) {
537 qemu_put_be32(f, pci_irq_state(s, i));
538 }
539
540 return 0;
541}
542
543static VMStateInfo vmstate_info_pci_irq_state = {
544 .name = "pci irq state",
545 .get = get_pci_irq_state,
546 .put = put_pci_irq_state,
547};
548
549static bool migrate_is_pcie(void *opaque, int version_id)
550{
551 return pci_is_express((PCIDevice *)opaque);
552}
553
554static bool migrate_is_not_pcie(void *opaque, int version_id)
555{
556 return !pci_is_express((PCIDevice *)opaque);
557}
558
559const VMStateDescription vmstate_pci_device = {
560 .name = "PCIDevice",
561 .version_id = 2,
562 .minimum_version_id = 1,
563 .fields = (VMStateField[]) {
564 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
565 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
566 migrate_is_not_pcie,
567 0, vmstate_info_pci_config,
568 PCI_CONFIG_SPACE_SIZE),
569 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
570 migrate_is_pcie,
571 0, vmstate_info_pci_config,
572 PCIE_CONFIG_SPACE_SIZE),
573 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
574 vmstate_info_pci_irq_state,
575 PCI_NUM_PINS * sizeof(int32_t)),
576 VMSTATE_END_OF_LIST()
577 }
578};
579
580
581void pci_device_save(PCIDevice *s, QEMUFile *f)
582{
583
584
585
586
587 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
588 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
589
590 pci_update_irq_status(s);
591}
592
593int pci_device_load(PCIDevice *s, QEMUFile *f)
594{
595 int ret;
596 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
597
598 pci_update_irq_status(s);
599 return ret;
600}
601
602static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
603{
604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
605 pci_default_sub_vendor_id);
606 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
607 pci_default_sub_device_id);
608}
609
610
611
612
613
614static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
615 unsigned int *slotp, unsigned int *funcp)
616{
617 const char *p;
618 char *e;
619 unsigned long val;
620 unsigned long dom = 0, bus = 0;
621 unsigned int slot = 0;
622 unsigned int func = 0;
623
624 p = addr;
625 val = strtoul(p, &e, 16);
626 if (e == p)
627 return -1;
628 if (*e == ':') {
629 bus = val;
630 p = e + 1;
631 val = strtoul(p, &e, 16);
632 if (e == p)
633 return -1;
634 if (*e == ':') {
635 dom = bus;
636 bus = val;
637 p = e + 1;
638 val = strtoul(p, &e, 16);
639 if (e == p)
640 return -1;
641 }
642 }
643
644 slot = val;
645
646 if (funcp != NULL) {
647 if (*e != '.')
648 return -1;
649
650 p = e + 1;
651 val = strtoul(p, &e, 16);
652 if (e == p)
653 return -1;
654
655 func = val;
656 }
657
658
659 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
660 return -1;
661
662 if (*e)
663 return -1;
664
665 *domp = dom;
666 *busp = bus;
667 *slotp = slot;
668 if (funcp != NULL)
669 *funcp = func;
670 return 0;
671}
672
673static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
674 const char *devaddr)
675{
676 int dom, bus;
677 unsigned slot;
678
679 if (!root) {
680 fprintf(stderr, "No primary PCI bus\n");
681 return NULL;
682 }
683
684 assert(!root->parent_dev);
685
686 if (!devaddr) {
687 *devfnp = -1;
688 return pci_find_bus_nr(root, 0);
689 }
690
691 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
692 return NULL;
693 }
694
695 if (dom != 0) {
696 fprintf(stderr, "No support for non-zero PCI domains\n");
697 return NULL;
698 }
699
700 *devfnp = PCI_DEVFN(slot, 0);
701 return pci_find_bus_nr(root, bus);
702}
703
704static void pci_init_cmask(PCIDevice *dev)
705{
706 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
707 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
708 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
709 dev->cmask[PCI_REVISION_ID] = 0xff;
710 dev->cmask[PCI_CLASS_PROG] = 0xff;
711 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
712 dev->cmask[PCI_HEADER_TYPE] = 0xff;
713 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
714}
715
716static void pci_init_wmask(PCIDevice *dev)
717{
718 int config_size = pci_config_size(dev);
719
720 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
721 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
722 pci_set_word(dev->wmask + PCI_COMMAND,
723 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
724 PCI_COMMAND_INTX_DISABLE);
725 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
726 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
727 }
728
729 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
730 config_size - PCI_CONFIG_HEADER_SIZE);
731}
732
733static void pci_init_w1cmask(PCIDevice *dev)
734{
735
736
737
738
739 pci_set_word(dev->w1cmask + PCI_STATUS,
740 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
741 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
742 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
743}
744
745static void pci_init_mask_bridge(PCIDevice *d)
746{
747
748
749 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
750
751
752 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
753 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
754 pci_set_word(d->wmask + PCI_MEMORY_BASE,
755 PCI_MEMORY_RANGE_MASK & 0xffff);
756 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
757 PCI_MEMORY_RANGE_MASK & 0xffff);
758 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
759 PCI_PREF_RANGE_MASK & 0xffff);
760 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
761 PCI_PREF_RANGE_MASK & 0xffff);
762
763
764 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
765
766
767 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
768 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
770 PCI_PREF_RANGE_TYPE_64);
771 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
772 PCI_PREF_RANGE_TYPE_64);
773
774
775
776
777
778 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
779 PCI_BRIDGE_CTL_PARITY |
780 PCI_BRIDGE_CTL_SERR |
781 PCI_BRIDGE_CTL_ISA |
782 PCI_BRIDGE_CTL_VGA |
783 PCI_BRIDGE_CTL_VGA_16BIT |
784 PCI_BRIDGE_CTL_MASTER_ABORT |
785 PCI_BRIDGE_CTL_BUS_RESET |
786 PCI_BRIDGE_CTL_FAST_BACK |
787 PCI_BRIDGE_CTL_DISCARD |
788 PCI_BRIDGE_CTL_SEC_DISCARD |
789 PCI_BRIDGE_CTL_DISCARD_SERR);
790
791
792 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
793 PCI_BRIDGE_CTL_DISCARD_STATUS);
794 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
795 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
797 PCI_PREF_RANGE_TYPE_MASK);
798 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
799 PCI_PREF_RANGE_TYPE_MASK);
800}
801
802static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
803{
804 uint8_t slot = PCI_SLOT(dev->devfn);
805 uint8_t func;
806
807 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
808 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
809 }
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824 if (PCI_FUNC(dev->devfn)) {
825 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
826 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
827
828 error_setg(errp, "PCI: single function device can't be populated "
829 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
830 return;
831 }
832 return;
833 }
834
835 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
836 return;
837 }
838
839 for (func = 1; func < PCI_FUNC_MAX; ++func) {
840 if (bus->devices[PCI_DEVFN(slot, func)]) {
841 error_setg(errp, "PCI: %x.0 indicates single function, "
842 "but %x.%x is already populated.",
843 slot, slot, func);
844 return;
845 }
846 }
847}
848
849static void pci_config_alloc(PCIDevice *pci_dev)
850{
851 int config_size = pci_config_size(pci_dev);
852
853 pci_dev->config = g_malloc0(config_size);
854 pci_dev->cmask = g_malloc0(config_size);
855 pci_dev->wmask = g_malloc0(config_size);
856 pci_dev->w1cmask = g_malloc0(config_size);
857 pci_dev->used = g_malloc0(config_size);
858}
859
860static void pci_config_free(PCIDevice *pci_dev)
861{
862 g_free(pci_dev->config);
863 g_free(pci_dev->cmask);
864 g_free(pci_dev->wmask);
865 g_free(pci_dev->w1cmask);
866 g_free(pci_dev->used);
867}
868
869static void do_pci_unregister_device(PCIDevice *pci_dev)
870{
871 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
872 pci_config_free(pci_dev);
873
874 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
875 memory_region_del_subregion(&pci_dev->bus_master_container_region,
876 &pci_dev->bus_master_enable_region);
877 }
878 address_space_destroy(&pci_dev->bus_master_as);
879}
880
881
882static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
883{
884 uint8_t bus_n;
885 uint16_t result;
886
887 switch (cache->type) {
888 case PCI_REQ_ID_BDF:
889 result = pci_get_bdf(cache->dev);
890 break;
891 case PCI_REQ_ID_SECONDARY_BUS:
892 bus_n = pci_dev_bus_num(cache->dev);
893 result = PCI_BUILD_BDF(bus_n, 0);
894 break;
895 default:
896 error_printf("Invalid PCI requester ID cache type: %d\n",
897 cache->type);
898 exit(1);
899 break;
900 }
901
902 return result;
903}
904
905
906
907
908
909
910
911
912
913
914static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
915{
916 PCIDevice *parent;
917 PCIReqIDCache cache = {
918 .dev = dev,
919 .type = PCI_REQ_ID_BDF,
920 };
921
922 while (!pci_bus_is_root(pci_get_bus(dev))) {
923
924 parent = pci_get_bus(dev)->parent_dev;
925 if (pci_is_express(parent)) {
926 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
927
928
929
930
931 cache.type = PCI_REQ_ID_SECONDARY_BUS;
932 cache.dev = dev;
933 }
934 } else {
935
936
937
938
939
940
941
942 cache.type = PCI_REQ_ID_BDF;
943 cache.dev = parent;
944 }
945 dev = parent;
946 }
947
948 return cache;
949}
950
951uint16_t pci_requester_id(PCIDevice *dev)
952{
953 return pci_req_id_cache_extract(&dev->requester_id_cache);
954}
955
956static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
957{
958 return !(bus->devices[devfn]);
959}
960
961static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
962{
963 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
964}
965
966
967static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
968 const char *name, int devfn,
969 Error **errp)
970{
971 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
972 PCIConfigReadFunc *config_read = pc->config_read;
973 PCIConfigWriteFunc *config_write = pc->config_write;
974 Error *local_err = NULL;
975 DeviceState *dev = DEVICE(pci_dev);
976 PCIBus *bus = pci_get_bus(pci_dev);
977
978
979 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
980 error_setg(errp,
981 "PCI: Only PCI/PCIe bridges can be plugged into %s",
982 bus->parent_dev->name);
983 return NULL;
984 }
985
986 if (devfn < 0) {
987 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
988 devfn += PCI_FUNC_MAX) {
989 if (pci_bus_devfn_available(bus, devfn) &&
990 !pci_bus_devfn_reserved(bus, devfn)) {
991 goto found;
992 }
993 }
994 error_setg(errp, "PCI: no slot/function available for %s, all in use "
995 "or reserved", name);
996 return NULL;
997 found: ;
998 } else if (pci_bus_devfn_reserved(bus, devfn)) {
999 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1000 " reserved",
1001 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1002 return NULL;
1003 } else if (!pci_bus_devfn_available(bus, devfn)) {
1004 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1005 " in use by %s",
1006 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1007 bus->devices[devfn]->name);
1008 return NULL;
1009 } else if (dev->hotplugged &&
1010 pci_get_function_0(pci_dev)) {
1011 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1012 " new func %s cannot be exposed to guest.",
1013 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1014 pci_get_function_0(pci_dev)->name,
1015 name);
1016
1017 return NULL;
1018 }
1019
1020 pci_dev->devfn = devfn;
1021 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1022 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1023
1024 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1025 "bus master container", UINT64_MAX);
1026 address_space_init(&pci_dev->bus_master_as,
1027 &pci_dev->bus_master_container_region, pci_dev->name);
1028
1029 if (qdev_hotplug) {
1030 pci_init_bus_master(pci_dev);
1031 }
1032 pci_dev->irq_state = 0;
1033 pci_config_alloc(pci_dev);
1034
1035 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1036 pci_config_set_device_id(pci_dev->config, pc->device_id);
1037 pci_config_set_revision(pci_dev->config, pc->revision);
1038 pci_config_set_class(pci_dev->config, pc->class_id);
1039
1040 if (!pc->is_bridge) {
1041 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1042 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1043 pc->subsystem_vendor_id);
1044 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1045 pc->subsystem_id);
1046 } else {
1047 pci_set_default_subsystem_id(pci_dev);
1048 }
1049 } else {
1050
1051 assert(!pc->subsystem_vendor_id);
1052 assert(!pc->subsystem_id);
1053 }
1054 pci_init_cmask(pci_dev);
1055 pci_init_wmask(pci_dev);
1056 pci_init_w1cmask(pci_dev);
1057 if (pc->is_bridge) {
1058 pci_init_mask_bridge(pci_dev);
1059 }
1060 pci_init_multifunction(bus, pci_dev, &local_err);
1061 if (local_err) {
1062 error_propagate(errp, local_err);
1063 do_pci_unregister_device(pci_dev);
1064 return NULL;
1065 }
1066
1067 if (!config_read)
1068 config_read = pci_default_read_config;
1069 if (!config_write)
1070 config_write = pci_default_write_config;
1071 pci_dev->config_read = config_read;
1072 pci_dev->config_write = config_write;
1073 bus->devices[devfn] = pci_dev;
1074 pci_dev->version_id = 2;
1075 return pci_dev;
1076}
1077
1078static void pci_unregister_io_regions(PCIDevice *pci_dev)
1079{
1080 PCIIORegion *r;
1081 int i;
1082
1083 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1084 r = &pci_dev->io_regions[i];
1085 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1086 continue;
1087 memory_region_del_subregion(r->address_space, r->memory);
1088 }
1089
1090 pci_unregister_vga(pci_dev);
1091}
1092
1093static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1094{
1095 PCIDevice *pci_dev = PCI_DEVICE(dev);
1096 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1097
1098 pci_unregister_io_regions(pci_dev);
1099 pci_del_option_rom(pci_dev);
1100
1101 if (pc->exit) {
1102 pc->exit(pci_dev);
1103 }
1104
1105 pci_device_deassert_intx(pci_dev);
1106 do_pci_unregister_device(pci_dev);
1107}
1108
1109void pci_register_bar(PCIDevice *pci_dev, int region_num,
1110 uint8_t type, MemoryRegion *memory)
1111{
1112 PCIIORegion *r;
1113 uint32_t addr;
1114 uint64_t wmask;
1115 pcibus_t size = memory_region_size(memory);
1116
1117 assert(region_num >= 0);
1118 assert(region_num < PCI_NUM_REGIONS);
1119 if (size & (size-1)) {
1120 error_report("ERROR: PCI region size must be pow2 "
1121 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
1122 exit(1);
1123 }
1124
1125 r = &pci_dev->io_regions[region_num];
1126 r->addr = PCI_BAR_UNMAPPED;
1127 r->size = size;
1128 r->type = type;
1129 r->memory = memory;
1130 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1131 ? pci_get_bus(pci_dev)->address_space_io
1132 : pci_get_bus(pci_dev)->address_space_mem;
1133
1134 wmask = ~(size - 1);
1135 if (region_num == PCI_ROM_SLOT) {
1136
1137 wmask |= PCI_ROM_ADDRESS_ENABLE;
1138 }
1139
1140 addr = pci_bar(pci_dev, region_num);
1141 pci_set_long(pci_dev->config + addr, type);
1142
1143 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1144 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1145 pci_set_quad(pci_dev->wmask + addr, wmask);
1146 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1147 } else {
1148 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1149 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1150 }
1151}
1152
1153static void pci_update_vga(PCIDevice *pci_dev)
1154{
1155 uint16_t cmd;
1156
1157 if (!pci_dev->has_vga) {
1158 return;
1159 }
1160
1161 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1162
1163 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1164 cmd & PCI_COMMAND_MEMORY);
1165 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1166 cmd & PCI_COMMAND_IO);
1167 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1168 cmd & PCI_COMMAND_IO);
1169}
1170
1171void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1172 MemoryRegion *io_lo, MemoryRegion *io_hi)
1173{
1174 PCIBus *bus = pci_get_bus(pci_dev);
1175
1176 assert(!pci_dev->has_vga);
1177
1178 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1179 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1180 memory_region_add_subregion_overlap(bus->address_space_mem,
1181 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1182
1183 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1184 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1185 memory_region_add_subregion_overlap(bus->address_space_io,
1186 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1187
1188 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1189 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1190 memory_region_add_subregion_overlap(bus->address_space_io,
1191 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1192 pci_dev->has_vga = true;
1193
1194 pci_update_vga(pci_dev);
1195}
1196
1197void pci_unregister_vga(PCIDevice *pci_dev)
1198{
1199 PCIBus *bus = pci_get_bus(pci_dev);
1200
1201 if (!pci_dev->has_vga) {
1202 return;
1203 }
1204
1205 memory_region_del_subregion(bus->address_space_mem,
1206 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1207 memory_region_del_subregion(bus->address_space_io,
1208 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1209 memory_region_del_subregion(bus->address_space_io,
1210 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1211 pci_dev->has_vga = false;
1212}
1213
1214pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1215{
1216 return pci_dev->io_regions[region_num].addr;
1217}
1218
1219static pcibus_t pci_bar_address(PCIDevice *d,
1220 int reg, uint8_t type, pcibus_t size)
1221{
1222 pcibus_t new_addr, last_addr;
1223 int bar = pci_bar(d, reg);
1224 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1225 Object *machine = qdev_get_machine();
1226 ObjectClass *oc = object_get_class(machine);
1227 MachineClass *mc = MACHINE_CLASS(oc);
1228 bool allow_0_address = mc->pci_allow_0_address;
1229
1230 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1231 if (!(cmd & PCI_COMMAND_IO)) {
1232 return PCI_BAR_UNMAPPED;
1233 }
1234 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1235 last_addr = new_addr + size - 1;
1236
1237
1238
1239 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1240 (!allow_0_address && new_addr == 0)) {
1241 return PCI_BAR_UNMAPPED;
1242 }
1243 return new_addr;
1244 }
1245
1246 if (!(cmd & PCI_COMMAND_MEMORY)) {
1247 return PCI_BAR_UNMAPPED;
1248 }
1249 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1250 new_addr = pci_get_quad(d->config + bar);
1251 } else {
1252 new_addr = pci_get_long(d->config + bar);
1253 }
1254
1255 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1256 return PCI_BAR_UNMAPPED;
1257 }
1258 new_addr &= ~(size - 1);
1259 last_addr = new_addr + size - 1;
1260
1261
1262
1263
1264 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1265 (!allow_0_address && new_addr == 0)) {
1266 return PCI_BAR_UNMAPPED;
1267 }
1268
1269
1270
1271
1272
1273
1274 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1275 return PCI_BAR_UNMAPPED;
1276 }
1277
1278
1279
1280
1281
1282
1283
1284 if (last_addr >= HWADDR_MAX) {
1285 return PCI_BAR_UNMAPPED;
1286 }
1287
1288 return new_addr;
1289}
1290
1291static void pci_update_mappings(PCIDevice *d)
1292{
1293 PCIIORegion *r;
1294 int i;
1295 pcibus_t new_addr;
1296
1297 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1298 r = &d->io_regions[i];
1299
1300
1301 if (!r->size)
1302 continue;
1303
1304 new_addr = pci_bar_address(d, i, r->type, r->size);
1305
1306
1307 if (new_addr == r->addr)
1308 continue;
1309
1310
1311 if (r->addr != PCI_BAR_UNMAPPED) {
1312 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
1313 PCI_SLOT(d->devfn),
1314 PCI_FUNC(d->devfn),
1315 i, r->addr, r->size);
1316 memory_region_del_subregion(r->address_space, r->memory);
1317 }
1318 r->addr = new_addr;
1319 if (r->addr != PCI_BAR_UNMAPPED) {
1320 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
1321 PCI_SLOT(d->devfn),
1322 PCI_FUNC(d->devfn),
1323 i, r->addr, r->size);
1324 memory_region_add_subregion_overlap(r->address_space,
1325 r->addr, r->memory, 1);
1326 }
1327 }
1328
1329 pci_update_vga(d);
1330}
1331
1332static inline int pci_irq_disabled(PCIDevice *d)
1333{
1334 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1335}
1336
1337
1338
1339
1340static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1341{
1342 int i, disabled = pci_irq_disabled(d);
1343 if (disabled == was_irq_disabled)
1344 return;
1345 for (i = 0; i < PCI_NUM_PINS; ++i) {
1346 int state = pci_irq_state(d, i);
1347 pci_change_irq_level(d, i, disabled ? -state : state);
1348 }
1349}
1350
1351uint32_t pci_default_read_config(PCIDevice *d,
1352 uint32_t address, int len)
1353{
1354 uint32_t val = 0;
1355
1356 memcpy(&val, d->config + address, len);
1357 return le32_to_cpu(val);
1358}
1359
1360void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1361{
1362 int i, was_irq_disabled = pci_irq_disabled(d);
1363 uint32_t val = val_in;
1364
1365 for (i = 0; i < l; val >>= 8, ++i) {
1366 uint8_t wmask = d->wmask[addr + i];
1367 uint8_t w1cmask = d->w1cmask[addr + i];
1368 assert(!(wmask & w1cmask));
1369 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1370 d->config[addr + i] &= ~(val & w1cmask);
1371 }
1372 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1373 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1374 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1375 range_covers_byte(addr, l, PCI_COMMAND))
1376 pci_update_mappings(d);
1377
1378 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1379 pci_update_irq_disabled(d, was_irq_disabled);
1380 memory_region_set_enabled(&d->bus_master_enable_region,
1381 pci_get_word(d->config + PCI_COMMAND)
1382 & PCI_COMMAND_MASTER);
1383 }
1384
1385 msi_write_config(d, addr, val_in, l);
1386 msix_write_config(d, addr, val_in, l);
1387}
1388
1389
1390
1391
1392
1393static void pci_irq_handler(void *opaque, int irq_num, int level)
1394{
1395 PCIDevice *pci_dev = opaque;
1396 int change;
1397
1398 change = level - pci_irq_state(pci_dev, irq_num);
1399 if (!change)
1400 return;
1401
1402 pci_set_irq_state(pci_dev, irq_num, level);
1403 pci_update_irq_status(pci_dev);
1404 if (pci_irq_disabled(pci_dev))
1405 return;
1406 pci_change_irq_level(pci_dev, irq_num, change);
1407}
1408
1409static inline int pci_intx(PCIDevice *pci_dev)
1410{
1411 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1412}
1413
1414qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1415{
1416 int intx = pci_intx(pci_dev);
1417
1418 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1419}
1420
1421void pci_set_irq(PCIDevice *pci_dev, int level)
1422{
1423 int intx = pci_intx(pci_dev);
1424 pci_irq_handler(pci_dev, intx, level);
1425}
1426
1427
1428void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1429{
1430 assert(pci_bus_is_root(bus));
1431 bus->route_intx_to_irq = route_intx_to_irq;
1432}
1433
1434PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1435{
1436 PCIBus *bus;
1437
1438 do {
1439 bus = pci_get_bus(dev);
1440 pin = bus->map_irq(dev, pin);
1441 dev = bus->parent_dev;
1442 } while (dev);
1443
1444 if (!bus->route_intx_to_irq) {
1445 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1446 object_get_typename(OBJECT(bus->qbus.parent)));
1447 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1448 }
1449
1450 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1451}
1452
1453bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1454{
1455 return old->mode != new->mode || old->irq != new->irq;
1456}
1457
1458void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1459{
1460 PCIDevice *dev;
1461 PCIBus *sec;
1462 int i;
1463
1464 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1465 dev = bus->devices[i];
1466 if (dev && dev->intx_routing_notifier) {
1467 dev->intx_routing_notifier(dev);
1468 }
1469 }
1470
1471 QLIST_FOREACH(sec, &bus->child, sibling) {
1472 pci_bus_fire_intx_routing_notifier(sec);
1473 }
1474}
1475
1476void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1477 PCIINTxRoutingNotifier notifier)
1478{
1479 dev->intx_routing_notifier = notifier;
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1496{
1497 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1498}
1499
1500
1501
1502
1503typedef struct {
1504 uint16_t class;
1505 const char *desc;
1506 const char *fw_name;
1507 uint16_t fw_ign_bits;
1508} pci_class_desc;
1509
1510static const pci_class_desc pci_class_descriptions[] =
1511{
1512 { 0x0001, "VGA controller", "display"},
1513 { 0x0100, "SCSI controller", "scsi"},
1514 { 0x0101, "IDE controller", "ide"},
1515 { 0x0102, "Floppy controller", "fdc"},
1516 { 0x0103, "IPI controller", "ipi"},
1517 { 0x0104, "RAID controller", "raid"},
1518 { 0x0106, "SATA controller"},
1519 { 0x0107, "SAS controller"},
1520 { 0x0180, "Storage controller"},
1521 { 0x0200, "Ethernet controller", "ethernet"},
1522 { 0x0201, "Token Ring controller", "token-ring"},
1523 { 0x0202, "FDDI controller", "fddi"},
1524 { 0x0203, "ATM controller", "atm"},
1525 { 0x0280, "Network controller"},
1526 { 0x0300, "VGA controller", "display", 0x00ff},
1527 { 0x0301, "XGA controller"},
1528 { 0x0302, "3D controller"},
1529 { 0x0380, "Display controller"},
1530 { 0x0400, "Video controller", "video"},
1531 { 0x0401, "Audio controller", "sound"},
1532 { 0x0402, "Phone"},
1533 { 0x0403, "Audio controller", "sound"},
1534 { 0x0480, "Multimedia controller"},
1535 { 0x0500, "RAM controller", "memory"},
1536 { 0x0501, "Flash controller", "flash"},
1537 { 0x0580, "Memory controller"},
1538 { 0x0600, "Host bridge", "host"},
1539 { 0x0601, "ISA bridge", "isa"},
1540 { 0x0602, "EISA bridge", "eisa"},
1541 { 0x0603, "MC bridge", "mca"},
1542 { 0x0604, "PCI bridge", "pci-bridge"},
1543 { 0x0605, "PCMCIA bridge", "pcmcia"},
1544 { 0x0606, "NUBUS bridge", "nubus"},
1545 { 0x0607, "CARDBUS bridge", "cardbus"},
1546 { 0x0608, "RACEWAY bridge"},
1547 { 0x0680, "Bridge"},
1548 { 0x0700, "Serial port", "serial"},
1549 { 0x0701, "Parallel port", "parallel"},
1550 { 0x0800, "Interrupt controller", "interrupt-controller"},
1551 { 0x0801, "DMA controller", "dma-controller"},
1552 { 0x0802, "Timer", "timer"},
1553 { 0x0803, "RTC", "rtc"},
1554 { 0x0900, "Keyboard", "keyboard"},
1555 { 0x0901, "Pen", "pen"},
1556 { 0x0902, "Mouse", "mouse"},
1557 { 0x0A00, "Dock station", "dock", 0x00ff},
1558 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1559 { 0x0c00, "Fireware contorller", "fireware"},
1560 { 0x0c01, "Access bus controller", "access-bus"},
1561 { 0x0c02, "SSA controller", "ssa"},
1562 { 0x0c03, "USB controller", "usb"},
1563 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1564 { 0x0c05, "SMBus"},
1565 { 0, NULL}
1566};
1567
1568static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1569 void (*fn)(PCIBus *b,
1570 PCIDevice *d,
1571 void *opaque),
1572 void *opaque)
1573{
1574 PCIDevice *d;
1575 int devfn;
1576
1577 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1578 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1579 if (d) {
1580 fn(bus, d, opaque);
1581 }
1582 }
1583}
1584
1585void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1586 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1587 void *opaque)
1588{
1589 bus = pci_find_bus_nr(bus, bus_num);
1590
1591 if (bus) {
1592 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1593 }
1594}
1595
1596static void pci_for_each_device_under_bus(PCIBus *bus,
1597 void (*fn)(PCIBus *b, PCIDevice *d,
1598 void *opaque),
1599 void *opaque)
1600{
1601 PCIDevice *d;
1602 int devfn;
1603
1604 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1605 d = bus->devices[devfn];
1606 if (d) {
1607 fn(bus, d, opaque);
1608 }
1609 }
1610}
1611
1612void pci_for_each_device(PCIBus *bus, int bus_num,
1613 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1614 void *opaque)
1615{
1616 bus = pci_find_bus_nr(bus, bus_num);
1617
1618 if (bus) {
1619 pci_for_each_device_under_bus(bus, fn, opaque);
1620 }
1621}
1622
1623static const pci_class_desc *get_class_desc(int class)
1624{
1625 const pci_class_desc *desc;
1626
1627 desc = pci_class_descriptions;
1628 while (desc->desc && class != desc->class) {
1629 desc++;
1630 }
1631
1632 return desc;
1633}
1634
1635static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1636
1637static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1638{
1639 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1640 int i;
1641
1642 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1643 const PCIIORegion *r = &dev->io_regions[i];
1644 PciMemoryRegionList *region;
1645
1646 if (!r->size) {
1647 continue;
1648 }
1649
1650 region = g_malloc0(sizeof(*region));
1651 region->value = g_malloc0(sizeof(*region->value));
1652
1653 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1654 region->value->type = g_strdup("io");
1655 } else {
1656 region->value->type = g_strdup("memory");
1657 region->value->has_prefetch = true;
1658 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1659 region->value->has_mem_type_64 = true;
1660 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1661 }
1662
1663 region->value->bar = i;
1664 region->value->address = r->addr;
1665 region->value->size = r->size;
1666
1667
1668 if (!cur_item) {
1669 head = cur_item = region;
1670 } else {
1671 cur_item->next = region;
1672 cur_item = region;
1673 }
1674 }
1675
1676 return head;
1677}
1678
1679static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1680 int bus_num)
1681{
1682 PciBridgeInfo *info;
1683 PciMemoryRange *range;
1684
1685 info = g_new0(PciBridgeInfo, 1);
1686
1687 info->bus = g_new0(PciBusInfo, 1);
1688 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1689 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1690 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1691
1692 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1693 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1694 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1695
1696 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1697 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1698 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1699
1700 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1701 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1702 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1703
1704 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1705 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1706 if (child_bus) {
1707 info->has_devices = true;
1708 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1709 }
1710 }
1711
1712 return info;
1713}
1714
1715static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1716 int bus_num)
1717{
1718 const pci_class_desc *desc;
1719 PciDeviceInfo *info;
1720 uint8_t type;
1721 int class;
1722
1723 info = g_new0(PciDeviceInfo, 1);
1724 info->bus = bus_num;
1725 info->slot = PCI_SLOT(dev->devfn);
1726 info->function = PCI_FUNC(dev->devfn);
1727
1728 info->class_info = g_new0(PciDeviceClass, 1);
1729 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1730 info->class_info->q_class = class;
1731 desc = get_class_desc(class);
1732 if (desc->desc) {
1733 info->class_info->has_desc = true;
1734 info->class_info->desc = g_strdup(desc->desc);
1735 }
1736
1737 info->id = g_new0(PciDeviceId, 1);
1738 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1739 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1740 info->regions = qmp_query_pci_regions(dev);
1741 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1742
1743 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1744 info->has_irq = true;
1745 info->irq = dev->config[PCI_INTERRUPT_LINE];
1746 }
1747
1748 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1749 if (type == PCI_HEADER_TYPE_BRIDGE) {
1750 info->has_pci_bridge = true;
1751 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1752 }
1753
1754 return info;
1755}
1756
1757static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1758{
1759 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1760 PCIDevice *dev;
1761 int devfn;
1762
1763 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1764 dev = bus->devices[devfn];
1765 if (dev) {
1766 info = g_malloc0(sizeof(*info));
1767 info->value = qmp_query_pci_device(dev, bus, bus_num);
1768
1769
1770 if (!cur_item) {
1771 head = cur_item = info;
1772 } else {
1773 cur_item->next = info;
1774 cur_item = info;
1775 }
1776 }
1777 }
1778
1779 return head;
1780}
1781
1782static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1783{
1784 PciInfo *info = NULL;
1785
1786 bus = pci_find_bus_nr(bus, bus_num);
1787 if (bus) {
1788 info = g_malloc0(sizeof(*info));
1789 info->bus = bus_num;
1790 info->devices = qmp_query_pci_devices(bus, bus_num);
1791 }
1792
1793 return info;
1794}
1795
1796PciInfoList *qmp_query_pci(Error **errp)
1797{
1798 PciInfoList *info, *head = NULL, *cur_item = NULL;
1799 PCIHostState *host_bridge;
1800
1801 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1802 info = g_malloc0(sizeof(*info));
1803 info->value = qmp_query_pci_bus(host_bridge->bus,
1804 pci_bus_num(host_bridge->bus));
1805
1806
1807 if (!cur_item) {
1808 head = cur_item = info;
1809 } else {
1810 cur_item->next = info;
1811 cur_item = info;
1812 }
1813 }
1814
1815 return head;
1816}
1817
1818
1819PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1820 const char *default_model,
1821 const char *default_devaddr)
1822{
1823 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1824 GSList *list;
1825 GPtrArray *pci_nic_models;
1826 PCIBus *bus;
1827 PCIDevice *pci_dev;
1828 DeviceState *dev;
1829 int devfn;
1830 int i;
1831
1832 if (nd->model && !strcmp(nd->model, "virtio")) {
1833 g_free(nd->model);
1834 nd->model = g_strdup("virtio-net-pci");
1835 }
1836
1837 list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false);
1838 pci_nic_models = g_ptr_array_new();
1839 while (list) {
1840 DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data,
1841 TYPE_DEVICE);
1842 GSList *next;
1843 if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) &&
1844 dc->user_creatable) {
1845 const char *name = object_class_get_name(list->data);
1846 g_ptr_array_add(pci_nic_models, (gpointer)name);
1847 }
1848 next = list->next;
1849 g_slist_free_1(list);
1850 list = next;
1851 }
1852 g_ptr_array_add(pci_nic_models, NULL);
1853
1854 if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) {
1855 exit(0);
1856 }
1857
1858 i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata,
1859 default_model);
1860 if (i < 0) {
1861 exit(1);
1862 }
1863
1864 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1865 if (!bus) {
1866 error_report("Invalid PCI device address %s for device %s",
1867 devaddr, nd->model);
1868 exit(1);
1869 }
1870
1871 pci_dev = pci_create(bus, devfn, nd->model);
1872 dev = &pci_dev->qdev;
1873 qdev_set_nic_properties(dev, nd);
1874 qdev_init_nofail(dev);
1875 g_ptr_array_free(pci_nic_models, true);
1876 return pci_dev;
1877}
1878
1879PCIDevice *pci_vga_init(PCIBus *bus)
1880{
1881 switch (vga_interface_type) {
1882 case VGA_CIRRUS:
1883 return pci_create_simple(bus, -1, "cirrus-vga");
1884 case VGA_QXL:
1885 return pci_create_simple(bus, -1, "qxl-vga");
1886 case VGA_STD:
1887 return pci_create_simple(bus, -1, "VGA");
1888 case VGA_VMWARE:
1889 return pci_create_simple(bus, -1, "vmware-svga");
1890 case VGA_VIRTIO:
1891 return pci_create_simple(bus, -1, "virtio-vga");
1892 case VGA_NONE:
1893 default:
1894
1895 return NULL;
1896 }
1897}
1898
1899
1900
1901static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1902{
1903 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1904 PCI_BRIDGE_CTL_BUS_RESET) &&
1905 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1906 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1907}
1908
1909
1910static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1911{
1912 int i;
1913
1914 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1915 PCIDevice *dev = bus->devices[i];
1916
1917 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1918 if (pci_secondary_bus_in_range(dev, bus_num)) {
1919 return true;
1920 }
1921 }
1922 }
1923
1924 return false;
1925}
1926
1927static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1928{
1929 PCIBus *sec;
1930
1931 if (!bus) {
1932 return NULL;
1933 }
1934
1935 if (pci_bus_num(bus) == bus_num) {
1936 return bus;
1937 }
1938
1939
1940 if (!pci_bus_is_root(bus) &&
1941 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1942 return NULL;
1943 }
1944
1945
1946 for (; bus; bus = sec) {
1947 QLIST_FOREACH(sec, &bus->child, sibling) {
1948 if (pci_bus_num(sec) == bus_num) {
1949 return sec;
1950 }
1951
1952 if (pci_bus_is_root(sec)) {
1953 if (pci_root_bus_in_range(sec, bus_num)) {
1954 break;
1955 }
1956 } else {
1957 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1958 break;
1959 }
1960 }
1961 }
1962 }
1963
1964 return NULL;
1965}
1966
1967void pci_for_each_bus_depth_first(PCIBus *bus,
1968 void *(*begin)(PCIBus *bus, void *parent_state),
1969 void (*end)(PCIBus *bus, void *state),
1970 void *parent_state)
1971{
1972 PCIBus *sec;
1973 void *state;
1974
1975 if (!bus) {
1976 return;
1977 }
1978
1979 if (begin) {
1980 state = begin(bus, parent_state);
1981 } else {
1982 state = parent_state;
1983 }
1984
1985 QLIST_FOREACH(sec, &bus->child, sibling) {
1986 pci_for_each_bus_depth_first(sec, begin, end, state);
1987 }
1988
1989 if (end) {
1990 end(bus, state);
1991 }
1992}
1993
1994
1995PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1996{
1997 bus = pci_find_bus_nr(bus, bus_num);
1998
1999 if (!bus)
2000 return NULL;
2001
2002 return bus->devices[devfn];
2003}
2004
2005static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2006{
2007 PCIDevice *pci_dev = (PCIDevice *)qdev;
2008 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2009 ObjectClass *klass = OBJECT_CLASS(pc);
2010 Error *local_err = NULL;
2011 bool is_default_rom;
2012
2013
2014
2015
2016 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
2017 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
2018 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2019 }
2020
2021 pci_dev = do_pci_register_device(pci_dev,
2022 object_get_typename(OBJECT(qdev)),
2023 pci_dev->devfn, errp);
2024 if (pci_dev == NULL)
2025 return;
2026
2027 if (pc->realize) {
2028 pc->realize(pci_dev, &local_err);
2029 if (local_err) {
2030 error_propagate(errp, local_err);
2031 do_pci_unregister_device(pci_dev);
2032 return;
2033 }
2034 }
2035
2036
2037 is_default_rom = false;
2038 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2039 pci_dev->romfile = g_strdup(pc->romfile);
2040 is_default_rom = true;
2041 }
2042
2043 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2044 if (local_err) {
2045 error_propagate(errp, local_err);
2046 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2047 return;
2048 }
2049}
2050
2051PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2052 const char *name)
2053{
2054 DeviceState *dev;
2055
2056 dev = qdev_create(&bus->qbus, name);
2057 qdev_prop_set_int32(dev, "addr", devfn);
2058 qdev_prop_set_bit(dev, "multifunction", multifunction);
2059 return PCI_DEVICE(dev);
2060}
2061
2062PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2063 bool multifunction,
2064 const char *name)
2065{
2066 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2067 qdev_init_nofail(&dev->qdev);
2068 return dev;
2069}
2070
2071PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2072{
2073 return pci_create_multifunction(bus, devfn, false, name);
2074}
2075
2076PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2077{
2078 return pci_create_simple_multifunction(bus, devfn, false, name);
2079}
2080
2081static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2082{
2083 int offset = PCI_CONFIG_HEADER_SIZE;
2084 int i;
2085 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2086 if (pdev->used[i])
2087 offset = i + 1;
2088 else if (i - offset + 1 == size)
2089 return offset;
2090 }
2091 return 0;
2092}
2093
2094static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2095 uint8_t *prev_p)
2096{
2097 uint8_t next, prev;
2098
2099 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2100 return 0;
2101
2102 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2103 prev = next + PCI_CAP_LIST_NEXT)
2104 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2105 break;
2106
2107 if (prev_p)
2108 *prev_p = prev;
2109 return next;
2110}
2111
2112static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2113{
2114 uint8_t next, prev, found = 0;
2115
2116 if (!(pdev->used[offset])) {
2117 return 0;
2118 }
2119
2120 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2121
2122 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2123 prev = next + PCI_CAP_LIST_NEXT) {
2124 if (next <= offset && next > found) {
2125 found = next;
2126 }
2127 }
2128 return found;
2129}
2130
2131
2132
2133static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2134{
2135 uint16_t vendor_id;
2136 uint16_t device_id;
2137 uint16_t rom_vendor_id;
2138 uint16_t rom_device_id;
2139 uint16_t rom_magic;
2140 uint16_t pcir_offset;
2141 uint8_t checksum;
2142
2143
2144
2145
2146
2147 rom_magic = pci_get_word(ptr);
2148 if (rom_magic != 0xaa55) {
2149 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2150 return;
2151 }
2152 pcir_offset = pci_get_word(ptr + 0x18);
2153 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2154 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2155 return;
2156 }
2157
2158 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2159 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2160 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2161 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2162
2163 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2164 vendor_id, device_id, rom_vendor_id, rom_device_id);
2165
2166 checksum = ptr[6];
2167
2168 if (vendor_id != rom_vendor_id) {
2169
2170 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2171 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2172 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2173 ptr[6] = checksum;
2174 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2175 }
2176
2177 if (device_id != rom_device_id) {
2178
2179 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2180 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2181 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2182 ptr[6] = checksum;
2183 pci_set_word(ptr + pcir_offset + 6, device_id);
2184 }
2185}
2186
2187
2188static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2189 Error **errp)
2190{
2191 int size;
2192 char *path;
2193 void *ptr;
2194 char name[32];
2195 const VMStateDescription *vmsd;
2196
2197 if (!pdev->romfile)
2198 return;
2199 if (strlen(pdev->romfile) == 0)
2200 return;
2201
2202 if (!pdev->rom_bar) {
2203
2204
2205
2206
2207 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2208
2209
2210
2211
2212
2213 if (DEVICE(pdev)->hotplugged) {
2214 error_setg(errp, "Hot-plugged device without ROM bar"
2215 " can't have an option ROM");
2216 return;
2217 }
2218
2219 if (class == 0x0300) {
2220 rom_add_vga(pdev->romfile);
2221 } else {
2222 rom_add_option(pdev->romfile, -1);
2223 }
2224 return;
2225 }
2226
2227 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2228 if (path == NULL) {
2229 path = g_strdup(pdev->romfile);
2230 }
2231
2232 size = get_image_size(path);
2233 if (size < 0) {
2234 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2235 g_free(path);
2236 return;
2237 } else if (size == 0) {
2238 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2239 g_free(path);
2240 return;
2241 }
2242 size = pow2ceil(size);
2243
2244 vmsd = qdev_get_vmsd(DEVICE(pdev));
2245
2246 if (vmsd) {
2247 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2248 } else {
2249 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2250 }
2251 pdev->has_rom = true;
2252 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2253 ptr = memory_region_get_ram_ptr(&pdev->rom);
2254 load_image(path, ptr);
2255 g_free(path);
2256
2257 if (is_default_rom) {
2258
2259 pci_patch_ids(pdev, ptr, size);
2260 }
2261
2262 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2263}
2264
2265static void pci_del_option_rom(PCIDevice *pdev)
2266{
2267 if (!pdev->has_rom)
2268 return;
2269
2270 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2271 pdev->has_rom = false;
2272}
2273
2274
2275
2276
2277
2278
2279
2280int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2281 uint8_t offset, uint8_t size,
2282 Error **errp)
2283{
2284 uint8_t *config;
2285 int i, overlapping_cap;
2286
2287 if (!offset) {
2288 offset = pci_find_space(pdev, size);
2289
2290 assert(offset);
2291 } else {
2292
2293
2294
2295
2296 for (i = offset; i < offset + size; i++) {
2297 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2298 if (overlapping_cap) {
2299 error_setg(errp, "%s:%02x:%02x.%x "
2300 "Attempt to add PCI capability %x at offset "
2301 "%x overlaps existing capability %x at offset %x",
2302 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
2303 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2304 cap_id, offset, overlapping_cap, i);
2305 return -EINVAL;
2306 }
2307 }
2308 }
2309
2310 config = pdev->config + offset;
2311 config[PCI_CAP_LIST_ID] = cap_id;
2312 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2313 pdev->config[PCI_CAPABILITY_LIST] = offset;
2314 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2315 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2316
2317 memset(pdev->wmask + offset, 0, size);
2318
2319 memset(pdev->cmask + offset, 0xFF, size);
2320 return offset;
2321}
2322
2323
2324void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2325{
2326 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2327 if (!offset)
2328 return;
2329 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2330
2331 memset(pdev->wmask + offset, 0xff, size);
2332 memset(pdev->w1cmask + offset, 0, size);
2333
2334 memset(pdev->cmask + offset, 0, size);
2335 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2336
2337 if (!pdev->config[PCI_CAPABILITY_LIST])
2338 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2339}
2340
2341uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2342{
2343 return pci_find_capability_list(pdev, cap_id, NULL);
2344}
2345
2346static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2347{
2348 PCIDevice *d = (PCIDevice *)dev;
2349 const pci_class_desc *desc;
2350 char ctxt[64];
2351 PCIIORegion *r;
2352 int i, class;
2353
2354 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2355 desc = pci_class_descriptions;
2356 while (desc->desc && class != desc->class)
2357 desc++;
2358 if (desc->desc) {
2359 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2360 } else {
2361 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2362 }
2363
2364 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2365 "pci id %04x:%04x (sub %04x:%04x)\n",
2366 indent, "", ctxt, pci_dev_bus_num(d),
2367 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2368 pci_get_word(d->config + PCI_VENDOR_ID),
2369 pci_get_word(d->config + PCI_DEVICE_ID),
2370 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2371 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2372 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2373 r = &d->io_regions[i];
2374 if (!r->size)
2375 continue;
2376 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2377 " [0x%"FMT_PCIBUS"]\n",
2378 indent, "",
2379 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2380 r->addr, r->addr + r->size - 1);
2381 }
2382}
2383
2384static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2385{
2386 PCIDevice *d = (PCIDevice *)dev;
2387 const char *name = NULL;
2388 const pci_class_desc *desc = pci_class_descriptions;
2389 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2390
2391 while (desc->desc &&
2392 (class & ~desc->fw_ign_bits) !=
2393 (desc->class & ~desc->fw_ign_bits)) {
2394 desc++;
2395 }
2396
2397 if (desc->desc) {
2398 name = desc->fw_name;
2399 }
2400
2401 if (name) {
2402 pstrcpy(buf, len, name);
2403 } else {
2404 snprintf(buf, len, "pci%04x,%04x",
2405 pci_get_word(d->config + PCI_VENDOR_ID),
2406 pci_get_word(d->config + PCI_DEVICE_ID));
2407 }
2408
2409 return buf;
2410}
2411
2412static char *pcibus_get_fw_dev_path(DeviceState *dev)
2413{
2414 PCIDevice *d = (PCIDevice *)dev;
2415 char path[50], name[33];
2416 int off;
2417
2418 off = snprintf(path, sizeof(path), "%s@%x",
2419 pci_dev_fw_name(dev, name, sizeof name),
2420 PCI_SLOT(d->devfn));
2421 if (PCI_FUNC(d->devfn))
2422 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2423 return g_strdup(path);
2424}
2425
2426static char *pcibus_get_dev_path(DeviceState *dev)
2427{
2428 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2429 PCIDevice *t;
2430 int slot_depth;
2431
2432
2433
2434
2435
2436 const char *root_bus_path;
2437 int root_bus_len;
2438 char slot[] = ":SS.F";
2439 int slot_len = sizeof slot - 1 ;
2440 int path_len;
2441 char *path, *p;
2442 int s;
2443
2444 root_bus_path = pci_root_bus_path(d);
2445 root_bus_len = strlen(root_bus_path);
2446
2447 ;
2448 slot_depth = 0;
2449 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2450 ++slot_depth;
2451 }
2452
2453 path_len = root_bus_len + slot_len * slot_depth;
2454
2455
2456 path = g_malloc(path_len + 1 );
2457 path[path_len] = '\0';
2458
2459 memcpy(path, root_bus_path, root_bus_len);
2460
2461
2462
2463 p = path + path_len;
2464 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2465 p -= slot_len;
2466 s = snprintf(slot, sizeof slot, ":%02x.%x",
2467 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2468 assert(s == slot_len);
2469 memcpy(p, slot, slot_len);
2470 }
2471
2472 return path;
2473}
2474
2475static int pci_qdev_find_recursive(PCIBus *bus,
2476 const char *id, PCIDevice **pdev)
2477{
2478 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2479 if (!qdev) {
2480 return -ENODEV;
2481 }
2482
2483
2484 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2485 *pdev = PCI_DEVICE(qdev);
2486 return 0;
2487 }
2488 return -EINVAL;
2489}
2490
2491int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2492{
2493 PCIHostState *host_bridge;
2494 int rc = -ENODEV;
2495
2496 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2497 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2498 if (!tmp) {
2499 rc = 0;
2500 break;
2501 }
2502 if (tmp != -ENODEV) {
2503 rc = tmp;
2504 }
2505 }
2506
2507 return rc;
2508}
2509
2510MemoryRegion *pci_address_space(PCIDevice *dev)
2511{
2512 return pci_get_bus(dev)->address_space_mem;
2513}
2514
2515MemoryRegion *pci_address_space_io(PCIDevice *dev)
2516{
2517 return pci_get_bus(dev)->address_space_io;
2518}
2519
2520static void pci_device_class_init(ObjectClass *klass, void *data)
2521{
2522 DeviceClass *k = DEVICE_CLASS(klass);
2523
2524 k->realize = pci_qdev_realize;
2525 k->unrealize = pci_qdev_unrealize;
2526 k->bus_type = TYPE_PCI_BUS;
2527 k->props = pci_props;
2528}
2529
2530static void pci_device_class_base_init(ObjectClass *klass, void *data)
2531{
2532 if (!object_class_is_abstract(klass)) {
2533 ObjectClass *conventional =
2534 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2535 ObjectClass *pcie =
2536 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2537 assert(conventional || pcie);
2538 }
2539}
2540
2541AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2542{
2543 PCIBus *bus = pci_get_bus(dev);
2544 PCIBus *iommu_bus = bus;
2545
2546 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2547 iommu_bus = pci_get_bus(iommu_bus->parent_dev);
2548 }
2549 if (iommu_bus && iommu_bus->iommu_fn) {
2550 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2551 }
2552 return &address_space_memory;
2553}
2554
2555void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2556{
2557 bus->iommu_fn = fn;
2558 bus->iommu_opaque = opaque;
2559}
2560
2561static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2562{
2563 Range *range = opaque;
2564 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2565 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2566 int i;
2567
2568 if (!(cmd & PCI_COMMAND_MEMORY)) {
2569 return;
2570 }
2571
2572 if (pc->is_bridge) {
2573 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2574 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2575
2576 base = MAX(base, 0x1ULL << 32);
2577
2578 if (limit >= base) {
2579 Range pref_range;
2580 range_set_bounds(&pref_range, base, limit);
2581 range_extend(range, &pref_range);
2582 }
2583 }
2584 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2585 PCIIORegion *r = &dev->io_regions[i];
2586 pcibus_t lob, upb;
2587 Range region_range;
2588
2589 if (!r->size ||
2590 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2591 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2592 continue;
2593 }
2594
2595 lob = pci_bar_address(dev, i, r->type, r->size);
2596 upb = lob + r->size - 1;
2597 if (lob == PCI_BAR_UNMAPPED) {
2598 continue;
2599 }
2600
2601 lob = MAX(lob, 0x1ULL << 32);
2602
2603 if (upb >= lob) {
2604 range_set_bounds(®ion_range, lob, upb);
2605 range_extend(range, ®ion_range);
2606 }
2607 }
2608}
2609
2610void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2611{
2612 range_make_empty(range);
2613 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2614}
2615
2616static bool pcie_has_upstream_port(PCIDevice *dev)
2617{
2618 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
2619
2620
2621
2622
2623
2624
2625 return parent_dev &&
2626 pci_is_express(parent_dev) &&
2627 parent_dev->exp.exp_cap &&
2628 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2629 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2630}
2631
2632PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2633{
2634 PCIBus *bus = pci_get_bus(pci_dev);
2635
2636 if(pcie_has_upstream_port(pci_dev)) {
2637
2638 return bus->devices[0];
2639 } else {
2640
2641 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2642 }
2643}
2644
2645MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2646{
2647 MSIMessage msg;
2648 if (msix_enabled(dev)) {
2649 msg = msix_get_message(dev, vector);
2650 } else if (msi_enabled(dev)) {
2651 msg = msi_get_message(dev, vector);
2652 } else {
2653
2654 error_report("%s: unknown interrupt type", __func__);
2655 abort();
2656 }
2657 return msg;
2658}
2659
2660static const TypeInfo pci_device_type_info = {
2661 .name = TYPE_PCI_DEVICE,
2662 .parent = TYPE_DEVICE,
2663 .instance_size = sizeof(PCIDevice),
2664 .abstract = true,
2665 .class_size = sizeof(PCIDeviceClass),
2666 .class_init = pci_device_class_init,
2667 .class_base_init = pci_device_class_base_init,
2668};
2669
2670static void pci_register_types(void)
2671{
2672 type_register_static(&pci_bus_info);
2673 type_register_static(&pcie_bus_info);
2674 type_register_static(&conventional_pci_interface_info);
2675 type_register_static(&pcie_interface_info);
2676 type_register_static(&pci_device_type_info);
2677}
2678
2679type_init(pci_register_types)
2680