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22#include "qemu/osdep.h"
23#include "hw/hw.h"
24#include "hw/ppc/ppc.h"
25#include "hw/ppc/ppc4xx.h"
26#include "hw/pci/pci.h"
27#include "hw/pci/pci_host.h"
28#include "exec/address-spaces.h"
29#include "trace.h"
30
31struct PCIMasterMap {
32 uint32_t la;
33 uint32_t ma;
34 uint32_t pcila;
35 uint32_t pciha;
36};
37
38struct PCITargetMap {
39 uint32_t ms;
40 uint32_t la;
41};
42
43#define PPC4xx_PCI_HOST_BRIDGE(obj) \
44 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
45
46#define PPC4xx_PCI_NR_PMMS 3
47#define PPC4xx_PCI_NR_PTMS 2
48
49struct PPC4xxPCIState {
50 PCIHostState parent_obj;
51
52 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
53 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
54 qemu_irq irq[4];
55
56 MemoryRegion container;
57 MemoryRegion iomem;
58};
59typedef struct PPC4xxPCIState PPC4xxPCIState;
60
61#define PCIC0_CFGADDR 0x0
62#define PCIC0_CFGDATA 0x4
63
64
65
66#define PCIL0_PMM0LA 0x0
67#define PCIL0_PMM0MA 0x4
68#define PCIL0_PMM0PCILA 0x8
69#define PCIL0_PMM0PCIHA 0xc
70#define PCIL0_PMM1LA 0x10
71#define PCIL0_PMM1MA 0x14
72#define PCIL0_PMM1PCILA 0x18
73#define PCIL0_PMM1PCIHA 0x1c
74#define PCIL0_PMM2LA 0x20
75#define PCIL0_PMM2MA 0x24
76#define PCIL0_PMM2PCILA 0x28
77#define PCIL0_PMM2PCIHA 0x2c
78
79
80
81#define PCIL0_PTM1MS 0x30
82#define PCIL0_PTM1LA 0x34
83#define PCIL0_PTM2MS 0x38
84#define PCIL0_PTM2LA 0x3c
85#define PCI_REG_BASE 0x800000
86#define PCI_REG_SIZE 0x40
87
88#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
89
90static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
91 uint64_t value, unsigned size)
92{
93 struct PPC4xxPCIState *pci = opaque;
94
95
96
97
98 switch (offset) {
99 case PCIL0_PMM0LA:
100 pci->pmm[0].la = value;
101 break;
102 case PCIL0_PMM0MA:
103 pci->pmm[0].ma = value;
104 break;
105 case PCIL0_PMM0PCIHA:
106 pci->pmm[0].pciha = value;
107 break;
108 case PCIL0_PMM0PCILA:
109 pci->pmm[0].pcila = value;
110 break;
111
112 case PCIL0_PMM1LA:
113 pci->pmm[1].la = value;
114 break;
115 case PCIL0_PMM1MA:
116 pci->pmm[1].ma = value;
117 break;
118 case PCIL0_PMM1PCIHA:
119 pci->pmm[1].pciha = value;
120 break;
121 case PCIL0_PMM1PCILA:
122 pci->pmm[1].pcila = value;
123 break;
124
125 case PCIL0_PMM2LA:
126 pci->pmm[2].la = value;
127 break;
128 case PCIL0_PMM2MA:
129 pci->pmm[2].ma = value;
130 break;
131 case PCIL0_PMM2PCIHA:
132 pci->pmm[2].pciha = value;
133 break;
134 case PCIL0_PMM2PCILA:
135 pci->pmm[2].pcila = value;
136 break;
137
138 case PCIL0_PTM1MS:
139 pci->ptm[0].ms = value;
140 break;
141 case PCIL0_PTM1LA:
142 pci->ptm[0].la = value;
143 break;
144 case PCIL0_PTM2MS:
145 pci->ptm[1].ms = value;
146 break;
147 case PCIL0_PTM2LA:
148 pci->ptm[1].la = value;
149 break;
150
151 default:
152 printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
153 (unsigned long)offset);
154 break;
155 }
156}
157
158static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
159 unsigned size)
160{
161 struct PPC4xxPCIState *pci = opaque;
162 uint32_t value;
163
164 switch (offset) {
165 case PCIL0_PMM0LA:
166 value = pci->pmm[0].la;
167 break;
168 case PCIL0_PMM0MA:
169 value = pci->pmm[0].ma;
170 break;
171 case PCIL0_PMM0PCIHA:
172 value = pci->pmm[0].pciha;
173 break;
174 case PCIL0_PMM0PCILA:
175 value = pci->pmm[0].pcila;
176 break;
177
178 case PCIL0_PMM1LA:
179 value = pci->pmm[1].la;
180 break;
181 case PCIL0_PMM1MA:
182 value = pci->pmm[1].ma;
183 break;
184 case PCIL0_PMM1PCIHA:
185 value = pci->pmm[1].pciha;
186 break;
187 case PCIL0_PMM1PCILA:
188 value = pci->pmm[1].pcila;
189 break;
190
191 case PCIL0_PMM2LA:
192 value = pci->pmm[2].la;
193 break;
194 case PCIL0_PMM2MA:
195 value = pci->pmm[2].ma;
196 break;
197 case PCIL0_PMM2PCIHA:
198 value = pci->pmm[2].pciha;
199 break;
200 case PCIL0_PMM2PCILA:
201 value = pci->pmm[2].pcila;
202 break;
203
204 case PCIL0_PTM1MS:
205 value = pci->ptm[0].ms;
206 break;
207 case PCIL0_PTM1LA:
208 value = pci->ptm[0].la;
209 break;
210 case PCIL0_PTM2MS:
211 value = pci->ptm[1].ms;
212 break;
213 case PCIL0_PTM2LA:
214 value = pci->ptm[1].la;
215 break;
216
217 default:
218 printf("%s: invalid PCI internal register 0x%lx\n", __func__,
219 (unsigned long)offset);
220 value = 0;
221 }
222
223 return value;
224}
225
226static const MemoryRegionOps pci_reg_ops = {
227 .read = ppc4xx_pci_reg_read4,
228 .write = ppc4xx_pci_reg_write4,
229 .endianness = DEVICE_LITTLE_ENDIAN,
230};
231
232static void ppc4xx_pci_reset(void *opaque)
233{
234 struct PPC4xxPCIState *pci = opaque;
235
236 memset(pci->pmm, 0, sizeof(pci->pmm));
237 memset(pci->ptm, 0, sizeof(pci->ptm));
238}
239
240
241
242static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
243{
244 int slot = pci_dev->devfn >> 3;
245
246 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
247
248 return slot - 1;
249}
250
251static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
252{
253 qemu_irq *pci_irqs = opaque;
254
255 trace_ppc4xx_pci_set_irq(irq_num);
256 if (irq_num < 0) {
257 fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
258 return;
259 }
260 qemu_set_irq(pci_irqs[irq_num], level);
261}
262
263static const VMStateDescription vmstate_pci_master_map = {
264 .name = "pci_master_map",
265 .version_id = 0,
266 .minimum_version_id = 0,
267 .fields = (VMStateField[]) {
268 VMSTATE_UINT32(la, struct PCIMasterMap),
269 VMSTATE_UINT32(ma, struct PCIMasterMap),
270 VMSTATE_UINT32(pcila, struct PCIMasterMap),
271 VMSTATE_UINT32(pciha, struct PCIMasterMap),
272 VMSTATE_END_OF_LIST()
273 }
274};
275
276static const VMStateDescription vmstate_pci_target_map = {
277 .name = "pci_target_map",
278 .version_id = 0,
279 .minimum_version_id = 0,
280 .fields = (VMStateField[]) {
281 VMSTATE_UINT32(ms, struct PCITargetMap),
282 VMSTATE_UINT32(la, struct PCITargetMap),
283 VMSTATE_END_OF_LIST()
284 }
285};
286
287static const VMStateDescription vmstate_ppc4xx_pci = {
288 .name = "ppc4xx_pci",
289 .version_id = 1,
290 .minimum_version_id = 1,
291 .fields = (VMStateField[]) {
292 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
293 vmstate_pci_master_map,
294 struct PCIMasterMap),
295 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
296 vmstate_pci_target_map,
297 struct PCITargetMap),
298 VMSTATE_END_OF_LIST()
299 }
300};
301
302
303static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
304{
305 PPC4xxPCIState *s;
306 PCIHostState *h;
307 PCIBus *b;
308 int i;
309
310 h = PCI_HOST_BRIDGE(dev);
311 s = PPC4xx_PCI_HOST_BRIDGE(dev);
312
313 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
314 sysbus_init_irq(dev, &s->irq[i]);
315 }
316
317 b = pci_register_root_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
318 ppc4xx_pci_map_irq, s->irq, get_system_memory(),
319 get_system_io(), 0, 4, TYPE_PCI_BUS);
320 h->bus = b;
321
322 pci_create_simple(b, 0, "ppc4xx-host-bridge");
323
324
325 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
326 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
327 "pci-conf-idx", 4);
328 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
329 "pci-conf-data", 4);
330 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
331 "pci.reg", PCI_REG_SIZE);
332 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
333 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
334 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
335 sysbus_init_mmio(dev, &s->container);
336 qemu_register_reset(ppc4xx_pci_reset, s);
337
338 return 0;
339}
340
341static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
342{
343 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
344 DeviceClass *dc = DEVICE_CLASS(klass);
345
346 dc->desc = "Host bridge";
347 k->vendor_id = PCI_VENDOR_ID_IBM;
348 k->device_id = PCI_DEVICE_ID_IBM_440GX;
349 k->class_id = PCI_CLASS_BRIDGE_OTHER;
350
351
352
353
354 dc->user_creatable = false;
355}
356
357static const TypeInfo ppc4xx_host_bridge_info = {
358 .name = "ppc4xx-host-bridge",
359 .parent = TYPE_PCI_DEVICE,
360 .instance_size = sizeof(PCIDevice),
361 .class_init = ppc4xx_host_bridge_class_init,
362 .interfaces = (InterfaceInfo[]) {
363 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
364 { },
365 },
366};
367
368static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
369{
370 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
371 DeviceClass *dc = DEVICE_CLASS(klass);
372
373 k->init = ppc4xx_pcihost_initfn;
374 dc->vmsd = &vmstate_ppc4xx_pci;
375}
376
377static const TypeInfo ppc4xx_pcihost_info = {
378 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
379 .parent = TYPE_PCI_HOST_BRIDGE,
380 .instance_size = sizeof(PPC4xxPCIState),
381 .class_init = ppc4xx_pcihost_class_init,
382};
383
384static void ppc4xx_pci_register_types(void)
385{
386 type_register_static(&ppc4xx_pcihost_info);
387 type_register_static(&ppc4xx_host_bridge_info);
388}
389
390type_init(ppc4xx_pci_register_types)
391
