qemu/hw/riscv/spike.c
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   1/*
   2 * QEMU RISC-V Spike Board
   3 *
   4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5 * Copyright (c) 2017-2018 SiFive, Inc.
   6 *
   7 * This provides a RISC-V Board with the following devices:
   8 *
   9 * 0) HTIF Console and Poweroff
  10 * 1) CLINT (Timer and IPI)
  11 * 2) PLIC (Platform Level Interrupt Controller)
  12 *
  13 * This program is free software; you can redistribute it and/or modify it
  14 * under the terms and conditions of the GNU General Public License,
  15 * version 2 or later, as published by the Free Software Foundation.
  16 *
  17 * This program is distributed in the hope it will be useful, but WITHOUT
  18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20 * more details.
  21 *
  22 * You should have received a copy of the GNU General Public License along with
  23 * this program.  If not, see <http://www.gnu.org/licenses/>.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "qemu/log.h"
  28#include "qemu/error-report.h"
  29#include "qapi/error.h"
  30#include "hw/hw.h"
  31#include "hw/boards.h"
  32#include "hw/loader.h"
  33#include "hw/sysbus.h"
  34#include "target/riscv/cpu.h"
  35#include "hw/riscv/riscv_htif.h"
  36#include "hw/riscv/riscv_hart.h"
  37#include "hw/riscv/sifive_clint.h"
  38#include "hw/riscv/spike.h"
  39#include "chardev/char.h"
  40#include "sysemu/arch_init.h"
  41#include "sysemu/device_tree.h"
  42#include "exec/address-spaces.h"
  43#include "elf.h"
  44
  45#include <libfdt.h>
  46
  47static const struct MemmapEntry {
  48    hwaddr base;
  49    hwaddr size;
  50} spike_memmap[] = {
  51    [SPIKE_MROM] =     {     0x1000,    0x11000 },
  52    [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
  53    [SPIKE_DRAM] =     { 0x80000000,        0x0 },
  54};
  55
  56static uint64_t load_kernel(const char *kernel_filename)
  57{
  58    uint64_t kernel_entry, kernel_high;
  59
  60    if (load_elf_ram_sym(kernel_filename, NULL, NULL,
  61            &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
  62            NULL, true, htif_symbol_callback) < 0) {
  63        error_report("qemu: could not load kernel '%s'", kernel_filename);
  64        exit(1);
  65    }
  66    return kernel_entry;
  67}
  68
  69static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
  70    uint64_t mem_size, const char *cmdline)
  71{
  72    void *fdt;
  73    int cpu;
  74    uint32_t *cells;
  75    char *nodename;
  76
  77    fdt = s->fdt = create_device_tree(&s->fdt_size);
  78    if (!fdt) {
  79        error_report("create_device_tree() failed");
  80        exit(1);
  81    }
  82
  83    qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  84    qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  85    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  86    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  87
  88    qemu_fdt_add_subnode(fdt, "/htif");
  89    qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
  90
  91    qemu_fdt_add_subnode(fdt, "/soc");
  92    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  93    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
  94    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  95    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
  96
  97    nodename = g_strdup_printf("/memory@%lx",
  98        (long)memmap[SPIKE_DRAM].base);
  99    qemu_fdt_add_subnode(fdt, nodename);
 100    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 101        memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
 102        mem_size >> 32, mem_size);
 103    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 104    g_free(nodename);
 105
 106    qemu_fdt_add_subnode(fdt, "/cpus");
 107    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 108        SIFIVE_CLINT_TIMEBASE_FREQ);
 109    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 110    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 111
 112    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 113        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 114        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 115        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 116        qemu_fdt_add_subnode(fdt, nodename);
 117        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 118                              SPIKE_CLOCK_FREQ);
 119        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 120        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 121        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 122        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 123        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 124        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 125        qemu_fdt_add_subnode(fdt, intc);
 126        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 127        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
 128        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 129        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 130        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 131        g_free(isa);
 132        g_free(intc);
 133        g_free(nodename);
 134    }
 135
 136    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 137    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 138        nodename =
 139            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 140        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 141        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 142        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 143        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 144        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 145        g_free(nodename);
 146    }
 147    nodename = g_strdup_printf("/soc/clint@%lx",
 148        (long)memmap[SPIKE_CLINT].base);
 149    qemu_fdt_add_subnode(fdt, nodename);
 150    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 151    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 152        0x0, memmap[SPIKE_CLINT].base,
 153        0x0, memmap[SPIKE_CLINT].size);
 154    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 155        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 156    g_free(cells);
 157    g_free(nodename);
 158
 159    qemu_fdt_add_subnode(fdt, "/chosen");
 160    qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 161 }
 162
 163static void spike_v1_10_0_board_init(MachineState *machine)
 164{
 165    const struct MemmapEntry *memmap = spike_memmap;
 166
 167    SpikeState *s = g_new0(SpikeState, 1);
 168    MemoryRegion *system_memory = get_system_memory();
 169    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 170    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 171    int i;
 172
 173    /* Initialize SOC */
 174    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
 175                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
 176    object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
 177                            &error_abort);
 178    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 179                            &error_abort);
 180    object_property_set_bool(OBJECT(&s->soc), true, "realized",
 181                            &error_abort);
 182
 183    /* register system main memory (actual RAM) */
 184    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
 185                           machine->ram_size, &error_fatal);
 186    memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
 187        main_mem);
 188
 189    /* create device tree */
 190    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 191
 192    /* boot rom */
 193    memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
 194                           memmap[SPIKE_MROM].size, &error_fatal);
 195    memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
 196                                mask_rom);
 197
 198    if (machine->kernel_filename) {
 199        load_kernel(machine->kernel_filename);
 200    }
 201
 202    /* reset vector */
 203    uint32_t reset_vec[8] = {
 204        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 205        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 206        0xf1402573,                  /*     csrr   a0, mhartid  */
 207#if defined(TARGET_RISCV32)
 208        0x0182a283,                  /*     lw     t0, 24(t0) */
 209#elif defined(TARGET_RISCV64)
 210        0x0182b283,                  /*     ld     t0, 24(t0) */
 211#endif
 212        0x00028067,                  /*     jr     t0 */
 213        0x00000000,
 214        memmap[SPIKE_DRAM].base,     /* start: .dword DRAM_BASE */
 215        0x00000000,
 216                                     /* dtb: */
 217    };
 218
 219    /* copy in the reset vector in little_endian byte order */
 220    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 221        reset_vec[i] = cpu_to_le32(reset_vec[i]);
 222    }
 223    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 224                          memmap[SPIKE_MROM].base, &address_space_memory);
 225
 226    /* copy in the device tree */
 227    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 228            memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
 229        error_report("not enough space to store device-tree");
 230        exit(1);
 231    }
 232    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 233    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 234                          memmap[SPIKE_MROM].base + sizeof(reset_vec),
 235                          &address_space_memory);
 236
 237    /* initialize HTIF using symbols found in load_kernel */
 238    htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 239
 240    /* Core Local Interruptor (timer and IPI) */
 241    sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 242        smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 243}
 244
 245static void spike_v1_09_1_board_init(MachineState *machine)
 246{
 247    const struct MemmapEntry *memmap = spike_memmap;
 248
 249    SpikeState *s = g_new0(SpikeState, 1);
 250    MemoryRegion *system_memory = get_system_memory();
 251    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 252    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 253    int i;
 254
 255    /* Initialize SOC */
 256    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
 257                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
 258    object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
 259                            &error_abort);
 260    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 261                            &error_abort);
 262    object_property_set_bool(OBJECT(&s->soc), true, "realized",
 263                            &error_abort);
 264
 265    /* register system main memory (actual RAM) */
 266    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
 267                           machine->ram_size, &error_fatal);
 268    memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
 269        main_mem);
 270
 271    /* boot rom */
 272    memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
 273                           memmap[SPIKE_MROM].size, &error_fatal);
 274    memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
 275                                mask_rom);
 276
 277    if (machine->kernel_filename) {
 278        load_kernel(machine->kernel_filename);
 279    }
 280
 281    /* reset vector */
 282    uint32_t reset_vec[8] = {
 283        0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
 284        0x00028067,                   /* jump to DRAM_BASE */
 285        0x00000000,                   /* reserved */
 286        memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
 287        0, 0, 0, 0                    /* trap vector */
 288    };
 289
 290    /* part one of config string - before memory size specified */
 291    const char *config_string_tmpl =
 292        "platform {\n"
 293        "  vendor ucb;\n"
 294        "  arch spike;\n"
 295        "};\n"
 296        "rtc {\n"
 297        "  addr 0x%" PRIx64 "x;\n"
 298        "};\n"
 299        "ram {\n"
 300        "  0 {\n"
 301        "    addr 0x%" PRIx64 "x;\n"
 302        "    size 0x%" PRIx64 "x;\n"
 303        "  };\n"
 304        "};\n"
 305        "core {\n"
 306        "  0" " {\n"
 307        "    " "0 {\n"
 308        "      isa %s;\n"
 309        "      timecmp 0x%" PRIx64 "x;\n"
 310        "      ipi 0x%" PRIx64 "x;\n"
 311        "    };\n"
 312        "  };\n"
 313        "};\n";
 314
 315    /* build config string with supplied memory size */
 316    char *isa = riscv_isa_string(&s->soc.harts[0]);
 317    size_t config_string_size = strlen(config_string_tmpl) + 48;
 318    char *config_string = malloc(config_string_size);
 319    snprintf(config_string, config_string_size, config_string_tmpl,
 320        (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
 321        (uint64_t)memmap[SPIKE_DRAM].base,
 322        (uint64_t)ram_size, isa,
 323        (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
 324        (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
 325    g_free(isa);
 326    size_t config_string_len = strlen(config_string);
 327
 328    /* copy in the reset vector in little_endian byte order */
 329    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 330        reset_vec[i] = cpu_to_le32(reset_vec[i]);
 331    }
 332    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 333                          memmap[SPIKE_MROM].base, &address_space_memory);
 334
 335    /* copy in the config string */
 336    rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
 337                          memmap[SPIKE_MROM].base + sizeof(reset_vec),
 338                          &address_space_memory);
 339
 340    /* initialize HTIF using symbols found in load_kernel */
 341    htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 342
 343    /* Core Local Interruptor (timer and IPI) */
 344    sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 345        smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 346}
 347
 348static void spike_v1_09_1_machine_init(MachineClass *mc)
 349{
 350    mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
 351    mc->init = spike_v1_09_1_board_init;
 352    mc->max_cpus = 1;
 353}
 354
 355static void spike_v1_10_0_machine_init(MachineClass *mc)
 356{
 357    mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
 358    mc->init = spike_v1_10_0_board_init;
 359    mc->max_cpus = 1;
 360    mc->is_default = 1;
 361}
 362
 363DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
 364DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
 365