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21#include "qemu/osdep.h"
22#include <linux/vfio.h>
23#include <sys/ioctl.h>
24
25#include "hw/pci/msi.h"
26#include "hw/pci/msix.h"
27#include "hw/pci/pci_bridge.h"
28#include "qemu/error-report.h"
29#include "qemu/option.h"
30#include "qemu/range.h"
31#include "qemu/units.h"
32#include "sysemu/kvm.h"
33#include "sysemu/sysemu.h"
34#include "pci.h"
35#include "trace.h"
36#include "qapi/error.h"
37
38#define MSIX_CAP_LENGTH 12
39
40static void vfio_disable_interrupts(VFIOPCIDevice *vdev);
41static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled);
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58static void vfio_intx_mmap_enable(void *opaque)
59{
60 VFIOPCIDevice *vdev = opaque;
61
62 if (vdev->intx.pending) {
63 timer_mod(vdev->intx.mmap_timer,
64 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
65 return;
66 }
67
68 vfio_mmap_set_enabled(vdev, true);
69}
70
71static void vfio_intx_interrupt(void *opaque)
72{
73 VFIOPCIDevice *vdev = opaque;
74
75 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) {
76 return;
77 }
78
79 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin);
80
81 vdev->intx.pending = true;
82 pci_irq_assert(&vdev->pdev);
83 vfio_mmap_set_enabled(vdev, false);
84 if (vdev->intx.mmap_timeout) {
85 timer_mod(vdev->intx.mmap_timer,
86 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
87 }
88}
89
90static void vfio_intx_eoi(VFIODevice *vbasedev)
91{
92 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
93
94 if (!vdev->intx.pending) {
95 return;
96 }
97
98 trace_vfio_intx_eoi(vbasedev->name);
99
100 vdev->intx.pending = false;
101 pci_irq_deassert(&vdev->pdev);
102 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
103}
104
105static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp)
106{
107#ifdef CONFIG_KVM
108 struct kvm_irqfd irqfd = {
109 .fd = event_notifier_get_fd(&vdev->intx.interrupt),
110 .gsi = vdev->intx.route.irq,
111 .flags = KVM_IRQFD_FLAG_RESAMPLE,
112 };
113 struct vfio_irq_set *irq_set;
114 int ret, argsz;
115 int32_t *pfd;
116
117 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() ||
118 vdev->intx.route.mode != PCI_INTX_ENABLED ||
119 !kvm_resamplefds_enabled()) {
120 return;
121 }
122
123
124 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev);
125 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
126 vdev->intx.pending = false;
127 pci_irq_deassert(&vdev->pdev);
128
129
130 if (event_notifier_init(&vdev->intx.unmask, 0)) {
131 error_setg(errp, "event_notifier_init failed eoi");
132 goto fail;
133 }
134
135
136 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask);
137
138 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
139 error_setg_errno(errp, errno, "failed to setup resample irqfd");
140 goto fail_irqfd;
141 }
142
143 argsz = sizeof(*irq_set) + sizeof(*pfd);
144
145 irq_set = g_malloc0(argsz);
146 irq_set->argsz = argsz;
147 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK;
148 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX;
149 irq_set->start = 0;
150 irq_set->count = 1;
151 pfd = (int32_t *)&irq_set->data;
152
153 *pfd = irqfd.resamplefd;
154
155 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
156 g_free(irq_set);
157 if (ret) {
158 error_setg_errno(errp, -ret, "failed to setup INTx unmask fd");
159 goto fail_vfio;
160 }
161
162
163 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
164
165 vdev->intx.kvm_accel = true;
166
167 trace_vfio_intx_enable_kvm(vdev->vbasedev.name);
168
169 return;
170
171fail_vfio:
172 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN;
173 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd);
174fail_irqfd:
175 event_notifier_cleanup(&vdev->intx.unmask);
176fail:
177 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev);
178 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
179#endif
180}
181
182static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev)
183{
184#ifdef CONFIG_KVM
185 struct kvm_irqfd irqfd = {
186 .fd = event_notifier_get_fd(&vdev->intx.interrupt),
187 .gsi = vdev->intx.route.irq,
188 .flags = KVM_IRQFD_FLAG_DEASSIGN,
189 };
190
191 if (!vdev->intx.kvm_accel) {
192 return;
193 }
194
195
196
197
198
199 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
200 vdev->intx.pending = false;
201 pci_irq_deassert(&vdev->pdev);
202
203
204 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
205 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
206 }
207
208
209 event_notifier_cleanup(&vdev->intx.unmask);
210
211
212 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev);
213
214 vdev->intx.kvm_accel = false;
215
216
217 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
218
219 trace_vfio_intx_disable_kvm(vdev->vbasedev.name);
220#endif
221}
222
223static void vfio_intx_update(PCIDevice *pdev)
224{
225 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
226 PCIINTxRoute route;
227 Error *err = NULL;
228
229 if (vdev->interrupt != VFIO_INT_INTx) {
230 return;
231 }
232
233 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin);
234
235 if (!pci_intx_route_changed(&vdev->intx.route, &route)) {
236 return;
237 }
238
239 trace_vfio_intx_update(vdev->vbasedev.name,
240 vdev->intx.route.irq, route.irq);
241
242 vfio_intx_disable_kvm(vdev);
243
244 vdev->intx.route = route;
245
246 if (route.mode != PCI_INTX_ENABLED) {
247 return;
248 }
249
250 vfio_intx_enable_kvm(vdev, &err);
251 if (err) {
252 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name);
253 }
254
255
256 vfio_intx_eoi(&vdev->vbasedev);
257}
258
259static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp)
260{
261 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1);
262 int ret, argsz, retval = 0;
263 struct vfio_irq_set *irq_set;
264 int32_t *pfd;
265 Error *err = NULL;
266
267 if (!pin) {
268 return 0;
269 }
270
271 vfio_disable_interrupts(vdev);
272
273 vdev->intx.pin = pin - 1;
274 pci_config_set_interrupt_pin(vdev->pdev.config, pin);
275
276#ifdef CONFIG_KVM
277
278
279
280
281 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) {
282 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev,
283 vdev->intx.pin);
284 }
285#endif
286
287 ret = event_notifier_init(&vdev->intx.interrupt, 0);
288 if (ret) {
289 error_setg_errno(errp, -ret, "event_notifier_init failed");
290 return ret;
291 }
292
293 argsz = sizeof(*irq_set) + sizeof(*pfd);
294
295 irq_set = g_malloc0(argsz);
296 irq_set->argsz = argsz;
297 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
298 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX;
299 irq_set->start = 0;
300 irq_set->count = 1;
301 pfd = (int32_t *)&irq_set->data;
302
303 *pfd = event_notifier_get_fd(&vdev->intx.interrupt);
304 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev);
305
306 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
307 if (ret) {
308 error_setg_errno(errp, -ret, "failed to setup INTx fd");
309 qemu_set_fd_handler(*pfd, NULL, NULL, vdev);
310 event_notifier_cleanup(&vdev->intx.interrupt);
311 retval = -errno;
312 goto cleanup;
313 }
314
315 vfio_intx_enable_kvm(vdev, &err);
316 if (err) {
317 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name);
318 }
319
320 vdev->interrupt = VFIO_INT_INTx;
321
322 trace_vfio_intx_enable(vdev->vbasedev.name);
323
324cleanup:
325 g_free(irq_set);
326
327 return retval;
328}
329
330static void vfio_intx_disable(VFIOPCIDevice *vdev)
331{
332 int fd;
333
334 timer_del(vdev->intx.mmap_timer);
335 vfio_intx_disable_kvm(vdev);
336 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
337 vdev->intx.pending = false;
338 pci_irq_deassert(&vdev->pdev);
339 vfio_mmap_set_enabled(vdev, true);
340
341 fd = event_notifier_get_fd(&vdev->intx.interrupt);
342 qemu_set_fd_handler(fd, NULL, NULL, vdev);
343 event_notifier_cleanup(&vdev->intx.interrupt);
344
345 vdev->interrupt = VFIO_INT_NONE;
346
347 trace_vfio_intx_disable(vdev->vbasedev.name);
348}
349
350
351
352
353static void vfio_msi_interrupt(void *opaque)
354{
355 VFIOMSIVector *vector = opaque;
356 VFIOPCIDevice *vdev = vector->vdev;
357 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector);
358 void (*notify)(PCIDevice *dev, unsigned vector);
359 MSIMessage msg;
360 int nr = vector - vdev->msi_vectors;
361
362 if (!event_notifier_test_and_clear(&vector->interrupt)) {
363 return;
364 }
365
366 if (vdev->interrupt == VFIO_INT_MSIX) {
367 get_msg = msix_get_message;
368 notify = msix_notify;
369
370
371 if (msix_is_masked(&vdev->pdev, nr)) {
372 set_bit(nr, vdev->msix->pending);
373 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true);
374 trace_vfio_msix_pba_enable(vdev->vbasedev.name);
375 }
376 } else if (vdev->interrupt == VFIO_INT_MSI) {
377 get_msg = msi_get_message;
378 notify = msi_notify;
379 } else {
380 abort();
381 }
382
383 msg = get_msg(&vdev->pdev, nr);
384 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data);
385 notify(&vdev->pdev, nr);
386}
387
388static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix)
389{
390 struct vfio_irq_set *irq_set;
391 int ret = 0, i, argsz;
392 int32_t *fds;
393
394 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds));
395
396 irq_set = g_malloc0(argsz);
397 irq_set->argsz = argsz;
398 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
399 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX;
400 irq_set->start = 0;
401 irq_set->count = vdev->nr_vectors;
402 fds = (int32_t *)&irq_set->data;
403
404 for (i = 0; i < vdev->nr_vectors; i++) {
405 int fd = -1;
406
407
408
409
410
411
412
413 if (vdev->msi_vectors[i].use) {
414 if (vdev->msi_vectors[i].virq < 0 ||
415 (msix && msix_is_masked(&vdev->pdev, i))) {
416 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt);
417 } else {
418 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt);
419 }
420 }
421
422 fds[i] = fd;
423 }
424
425 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
426
427 g_free(irq_set);
428
429 return ret;
430}
431
432static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
433 int vector_n, bool msix)
434{
435 int virq;
436
437 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) {
438 return;
439 }
440
441 if (event_notifier_init(&vector->kvm_interrupt, 0)) {
442 return;
443 }
444
445 virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev);
446 if (virq < 0) {
447 event_notifier_cleanup(&vector->kvm_interrupt);
448 return;
449 }
450
451 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
452 NULL, virq) < 0) {
453 kvm_irqchip_release_virq(kvm_state, virq);
454 event_notifier_cleanup(&vector->kvm_interrupt);
455 return;
456 }
457
458 vector->virq = virq;
459}
460
461static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector)
462{
463 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
464 vector->virq);
465 kvm_irqchip_release_virq(kvm_state, vector->virq);
466 vector->virq = -1;
467 event_notifier_cleanup(&vector->kvm_interrupt);
468}
469
470static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg,
471 PCIDevice *pdev)
472{
473 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev);
474 kvm_irqchip_commit_routes(kvm_state);
475}
476
477static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr,
478 MSIMessage *msg, IOHandler *handler)
479{
480 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
481 VFIOMSIVector *vector;
482 int ret;
483
484 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr);
485
486 vector = &vdev->msi_vectors[nr];
487
488 if (!vector->use) {
489 vector->vdev = vdev;
490 vector->virq = -1;
491 if (event_notifier_init(&vector->interrupt, 0)) {
492 error_report("vfio: Error: event_notifier_init failed");
493 }
494 vector->use = true;
495 msix_vector_use(pdev, nr);
496 }
497
498 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
499 handler, NULL, vector);
500
501
502
503
504
505 if (vector->virq >= 0) {
506 if (!msg) {
507 vfio_remove_kvm_msi_virq(vector);
508 } else {
509 vfio_update_kvm_msi_virq(vector, *msg, pdev);
510 }
511 } else {
512 if (msg) {
513 vfio_add_kvm_msi_virq(vdev, vector, nr, true);
514 }
515 }
516
517
518
519
520
521
522 if (vdev->nr_vectors < nr + 1) {
523 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
524 vdev->nr_vectors = nr + 1;
525 ret = vfio_enable_vectors(vdev, true);
526 if (ret) {
527 error_report("vfio: failed to enable vectors, %d", ret);
528 }
529 } else {
530 int argsz;
531 struct vfio_irq_set *irq_set;
532 int32_t *pfd;
533
534 argsz = sizeof(*irq_set) + sizeof(*pfd);
535
536 irq_set = g_malloc0(argsz);
537 irq_set->argsz = argsz;
538 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
539 VFIO_IRQ_SET_ACTION_TRIGGER;
540 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
541 irq_set->start = nr;
542 irq_set->count = 1;
543 pfd = (int32_t *)&irq_set->data;
544
545 if (vector->virq >= 0) {
546 *pfd = event_notifier_get_fd(&vector->kvm_interrupt);
547 } else {
548 *pfd = event_notifier_get_fd(&vector->interrupt);
549 }
550
551 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
552 g_free(irq_set);
553 if (ret) {
554 error_report("vfio: failed to modify vector, %d", ret);
555 }
556 }
557
558
559 clear_bit(nr, vdev->msix->pending);
560 if (find_first_bit(vdev->msix->pending,
561 vdev->nr_vectors) == vdev->nr_vectors) {
562 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
563 trace_vfio_msix_pba_disable(vdev->vbasedev.name);
564 }
565
566 return 0;
567}
568
569static int vfio_msix_vector_use(PCIDevice *pdev,
570 unsigned int nr, MSIMessage msg)
571{
572 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt);
573}
574
575static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr)
576{
577 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
578 VFIOMSIVector *vector = &vdev->msi_vectors[nr];
579
580 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr);
581
582
583
584
585
586
587
588
589
590 if (vector->virq >= 0) {
591 int argsz;
592 struct vfio_irq_set *irq_set;
593 int32_t *pfd;
594
595 argsz = sizeof(*irq_set) + sizeof(*pfd);
596
597 irq_set = g_malloc0(argsz);
598 irq_set->argsz = argsz;
599 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
600 VFIO_IRQ_SET_ACTION_TRIGGER;
601 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
602 irq_set->start = nr;
603 irq_set->count = 1;
604 pfd = (int32_t *)&irq_set->data;
605
606 *pfd = event_notifier_get_fd(&vector->interrupt);
607
608 ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
609
610 g_free(irq_set);
611 }
612}
613
614static void vfio_msix_enable(VFIOPCIDevice *vdev)
615{
616 vfio_disable_interrupts(vdev);
617
618 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries);
619
620 vdev->interrupt = VFIO_INT_MSIX;
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL);
636 vfio_msix_vector_release(&vdev->pdev, 0);
637
638 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use,
639 vfio_msix_vector_release, NULL)) {
640 error_report("vfio: msix_set_vector_notifiers failed");
641 }
642
643 trace_vfio_msix_enable(vdev->vbasedev.name);
644}
645
646static void vfio_msi_enable(VFIOPCIDevice *vdev)
647{
648 int ret, i;
649
650 vfio_disable_interrupts(vdev);
651
652 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev);
653retry:
654 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors);
655
656 for (i = 0; i < vdev->nr_vectors; i++) {
657 VFIOMSIVector *vector = &vdev->msi_vectors[i];
658
659 vector->vdev = vdev;
660 vector->virq = -1;
661 vector->use = true;
662
663 if (event_notifier_init(&vector->interrupt, 0)) {
664 error_report("vfio: Error: event_notifier_init failed");
665 }
666
667 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
668 vfio_msi_interrupt, NULL, vector);
669
670
671
672
673
674 vfio_add_kvm_msi_virq(vdev, vector, i, false);
675 }
676
677
678 vdev->interrupt = VFIO_INT_MSI;
679
680 ret = vfio_enable_vectors(vdev, false);
681 if (ret) {
682 if (ret < 0) {
683 error_report("vfio: Error: Failed to setup MSI fds: %m");
684 } else if (ret != vdev->nr_vectors) {
685 error_report("vfio: Error: Failed to enable %d "
686 "MSI vectors, retry with %d", vdev->nr_vectors, ret);
687 }
688
689 for (i = 0; i < vdev->nr_vectors; i++) {
690 VFIOMSIVector *vector = &vdev->msi_vectors[i];
691 if (vector->virq >= 0) {
692 vfio_remove_kvm_msi_virq(vector);
693 }
694 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
695 NULL, NULL, NULL);
696 event_notifier_cleanup(&vector->interrupt);
697 }
698
699 g_free(vdev->msi_vectors);
700
701 if (ret > 0 && ret != vdev->nr_vectors) {
702 vdev->nr_vectors = ret;
703 goto retry;
704 }
705 vdev->nr_vectors = 0;
706
707
708
709
710
711
712 error_report("vfio: Error: Failed to enable MSI");
713 vdev->interrupt = VFIO_INT_NONE;
714
715 return;
716 }
717
718 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors);
719}
720
721static void vfio_msi_disable_common(VFIOPCIDevice *vdev)
722{
723 Error *err = NULL;
724 int i;
725
726 for (i = 0; i < vdev->nr_vectors; i++) {
727 VFIOMSIVector *vector = &vdev->msi_vectors[i];
728 if (vdev->msi_vectors[i].use) {
729 if (vector->virq >= 0) {
730 vfio_remove_kvm_msi_virq(vector);
731 }
732 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
733 NULL, NULL, NULL);
734 event_notifier_cleanup(&vector->interrupt);
735 }
736 }
737
738 g_free(vdev->msi_vectors);
739 vdev->msi_vectors = NULL;
740 vdev->nr_vectors = 0;
741 vdev->interrupt = VFIO_INT_NONE;
742
743 vfio_intx_enable(vdev, &err);
744 if (err) {
745 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name);
746 }
747}
748
749static void vfio_msix_disable(VFIOPCIDevice *vdev)
750{
751 int i;
752
753 msix_unset_vector_notifiers(&vdev->pdev);
754
755
756
757
758
759 for (i = 0; i < vdev->nr_vectors; i++) {
760 if (vdev->msi_vectors[i].use) {
761 vfio_msix_vector_release(&vdev->pdev, i);
762 msix_vector_unuse(&vdev->pdev, i);
763 }
764 }
765
766 if (vdev->nr_vectors) {
767 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
768 }
769
770 vfio_msi_disable_common(vdev);
771
772 memset(vdev->msix->pending, 0,
773 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long));
774
775 trace_vfio_msix_disable(vdev->vbasedev.name);
776}
777
778static void vfio_msi_disable(VFIOPCIDevice *vdev)
779{
780 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX);
781 vfio_msi_disable_common(vdev);
782
783 trace_vfio_msi_disable(vdev->vbasedev.name);
784}
785
786static void vfio_update_msi(VFIOPCIDevice *vdev)
787{
788 int i;
789
790 for (i = 0; i < vdev->nr_vectors; i++) {
791 VFIOMSIVector *vector = &vdev->msi_vectors[i];
792 MSIMessage msg;
793
794 if (!vector->use || vector->virq < 0) {
795 continue;
796 }
797
798 msg = msi_get_message(&vdev->pdev, i);
799 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev);
800 }
801}
802
803static void vfio_pci_load_rom(VFIOPCIDevice *vdev)
804{
805 struct vfio_region_info *reg_info;
806 uint64_t size;
807 off_t off = 0;
808 ssize_t bytes;
809
810 if (vfio_get_region_info(&vdev->vbasedev,
811 VFIO_PCI_ROM_REGION_INDEX, ®_info)) {
812 error_report("vfio: Error getting ROM info: %m");
813 return;
814 }
815
816 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size,
817 (unsigned long)reg_info->offset,
818 (unsigned long)reg_info->flags);
819
820 vdev->rom_size = size = reg_info->size;
821 vdev->rom_offset = reg_info->offset;
822
823 g_free(reg_info);
824
825 if (!vdev->rom_size) {
826 vdev->rom_read_failed = true;
827 error_report("vfio-pci: Cannot read device rom at "
828 "%s", vdev->vbasedev.name);
829 error_printf("Device option ROM contents are probably invalid "
830 "(check dmesg).\nSkip option ROM probe with rombar=0, "
831 "or load from file with romfile=\n");
832 return;
833 }
834
835 vdev->rom = g_malloc(size);
836 memset(vdev->rom, 0xff, size);
837
838 while (size) {
839 bytes = pread(vdev->vbasedev.fd, vdev->rom + off,
840 size, vdev->rom_offset + off);
841 if (bytes == 0) {
842 break;
843 } else if (bytes > 0) {
844 off += bytes;
845 size -= bytes;
846 } else {
847 if (errno == EINTR || errno == EAGAIN) {
848 continue;
849 }
850 error_report("vfio: Error reading device ROM: %m");
851 break;
852 }
853 }
854
855
856
857
858
859
860
861 if (pci_get_word(vdev->rom) == 0xaa55 &&
862 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size &&
863 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) {
864 uint16_t vid, did;
865
866 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4);
867 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6);
868
869 if (vid == vdev->vendor_id && did != vdev->device_id) {
870 int i;
871 uint8_t csum, *data = vdev->rom;
872
873 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6,
874 vdev->device_id);
875 data[6] = 0;
876
877 for (csum = 0, i = 0; i < vdev->rom_size; i++) {
878 csum += data[i];
879 }
880
881 data[6] = -csum;
882 }
883 }
884}
885
886static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size)
887{
888 VFIOPCIDevice *vdev = opaque;
889 union {
890 uint8_t byte;
891 uint16_t word;
892 uint32_t dword;
893 uint64_t qword;
894 } val;
895 uint64_t data = 0;
896
897
898 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) {
899 vfio_pci_load_rom(vdev);
900 }
901
902 memcpy(&val, vdev->rom + addr,
903 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0);
904
905 switch (size) {
906 case 1:
907 data = val.byte;
908 break;
909 case 2:
910 data = le16_to_cpu(val.word);
911 break;
912 case 4:
913 data = le32_to_cpu(val.dword);
914 break;
915 default:
916 hw_error("vfio: unsupported read size, %d bytes\n", size);
917 break;
918 }
919
920 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data);
921
922 return data;
923}
924
925static void vfio_rom_write(void *opaque, hwaddr addr,
926 uint64_t data, unsigned size)
927{
928}
929
930static const MemoryRegionOps vfio_rom_ops = {
931 .read = vfio_rom_read,
932 .write = vfio_rom_write,
933 .endianness = DEVICE_LITTLE_ENDIAN,
934};
935
936static void vfio_pci_size_rom(VFIOPCIDevice *vdev)
937{
938 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK);
939 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS;
940 DeviceState *dev = DEVICE(vdev);
941 char *name;
942 int fd = vdev->vbasedev.fd;
943
944 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) {
945
946 if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) {
947 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n",
948 vdev->vbasedev.name);
949 }
950 return;
951 }
952
953
954
955
956
957 if (pread(fd, &orig, 4, offset) != 4 ||
958 pwrite(fd, &size, 4, offset) != 4 ||
959 pread(fd, &size, 4, offset) != 4 ||
960 pwrite(fd, &orig, 4, offset) != 4) {
961 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name);
962 return;
963 }
964
965 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1;
966
967 if (!size) {
968 return;
969 }
970
971 if (vfio_blacklist_opt_rom(vdev)) {
972 if (dev->opts && qemu_opt_get(dev->opts, "rombar")) {
973 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n",
974 vdev->vbasedev.name);
975 } else {
976 error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n",
977 vdev->vbasedev.name);
978 return;
979 }
980 }
981
982 trace_vfio_pci_size_rom(vdev->vbasedev.name, size);
983
984 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name);
985
986 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev),
987 &vfio_rom_ops, vdev, name, size);
988 g_free(name);
989
990 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT,
991 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom);
992
993 vdev->rom_read_failed = false;
994}
995
996void vfio_vga_write(void *opaque, hwaddr addr,
997 uint64_t data, unsigned size)
998{
999 VFIOVGARegion *region = opaque;
1000 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1001 union {
1002 uint8_t byte;
1003 uint16_t word;
1004 uint32_t dword;
1005 uint64_t qword;
1006 } buf;
1007 off_t offset = vga->fd_offset + region->offset + addr;
1008
1009 switch (size) {
1010 case 1:
1011 buf.byte = data;
1012 break;
1013 case 2:
1014 buf.word = cpu_to_le16(data);
1015 break;
1016 case 4:
1017 buf.dword = cpu_to_le32(data);
1018 break;
1019 default:
1020 hw_error("vfio: unsupported write size, %d bytes", size);
1021 break;
1022 }
1023
1024 if (pwrite(vga->fd, &buf, size, offset) != size) {
1025 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m",
1026 __func__, region->offset + addr, data, size);
1027 }
1028
1029 trace_vfio_vga_write(region->offset + addr, data, size);
1030}
1031
1032uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size)
1033{
1034 VFIOVGARegion *region = opaque;
1035 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1036 union {
1037 uint8_t byte;
1038 uint16_t word;
1039 uint32_t dword;
1040 uint64_t qword;
1041 } buf;
1042 uint64_t data = 0;
1043 off_t offset = vga->fd_offset + region->offset + addr;
1044
1045 if (pread(vga->fd, &buf, size, offset) != size) {
1046 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m",
1047 __func__, region->offset + addr, size);
1048 return (uint64_t)-1;
1049 }
1050
1051 switch (size) {
1052 case 1:
1053 data = buf.byte;
1054 break;
1055 case 2:
1056 data = le16_to_cpu(buf.word);
1057 break;
1058 case 4:
1059 data = le32_to_cpu(buf.dword);
1060 break;
1061 default:
1062 hw_error("vfio: unsupported read size, %d bytes", size);
1063 break;
1064 }
1065
1066 trace_vfio_vga_read(region->offset + addr, size, data);
1067
1068 return data;
1069}
1070
1071static const MemoryRegionOps vfio_vga_ops = {
1072 .read = vfio_vga_read,
1073 .write = vfio_vga_write,
1074 .endianness = DEVICE_LITTLE_ENDIAN,
1075};
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar)
1088{
1089 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
1090 VFIORegion *region = &vdev->bars[bar].region;
1091 MemoryRegion *mmap_mr, *region_mr, *base_mr;
1092 PCIIORegion *r;
1093 pcibus_t bar_addr;
1094 uint64_t size = region->size;
1095
1096
1097 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap ||
1098 region->mmaps[0].size != region->size) {
1099 return;
1100 }
1101
1102 r = &pdev->io_regions[bar];
1103 bar_addr = r->addr;
1104 base_mr = vdev->bars[bar].mr;
1105 region_mr = region->mem;
1106 mmap_mr = ®ion->mmaps[0].mem;
1107
1108
1109 if (bar_addr != PCI_BAR_UNMAPPED &&
1110 !(bar_addr & ~qemu_real_host_page_mask)) {
1111 size = qemu_real_host_page_size;
1112 }
1113
1114 memory_region_transaction_begin();
1115
1116 if (vdev->bars[bar].size < size) {
1117 memory_region_set_size(base_mr, size);
1118 }
1119 memory_region_set_size(region_mr, size);
1120 memory_region_set_size(mmap_mr, size);
1121 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) {
1122 memory_region_del_subregion(r->address_space, base_mr);
1123 memory_region_add_subregion_overlap(r->address_space,
1124 bar_addr, base_mr, 0);
1125 }
1126
1127 memory_region_transaction_commit();
1128}
1129
1130
1131
1132
1133uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len)
1134{
1135 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
1136 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val;
1137
1138 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len);
1139 emu_bits = le32_to_cpu(emu_bits);
1140
1141 if (emu_bits) {
1142 emu_val = pci_default_read_config(pdev, addr, len);
1143 }
1144
1145 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) {
1146 ssize_t ret;
1147
1148 ret = pread(vdev->vbasedev.fd, &phys_val, len,
1149 vdev->config_offset + addr);
1150 if (ret != len) {
1151 error_report("%s(%s, 0x%x, 0x%x) failed: %m",
1152 __func__, vdev->vbasedev.name, addr, len);
1153 return -errno;
1154 }
1155 phys_val = le32_to_cpu(phys_val);
1156 }
1157
1158 val = (emu_val & emu_bits) | (phys_val & ~emu_bits);
1159
1160 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val);
1161
1162 return val;
1163}
1164
1165void vfio_pci_write_config(PCIDevice *pdev,
1166 uint32_t addr, uint32_t val, int len)
1167{
1168 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
1169 uint32_t val_le = cpu_to_le32(val);
1170
1171 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len);
1172
1173
1174 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr)
1175 != len) {
1176 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m",
1177 __func__, vdev->vbasedev.name, addr, val, len);
1178 }
1179
1180
1181 if (pdev->cap_present & QEMU_PCI_CAP_MSI &&
1182 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) {
1183 int is_enabled, was_enabled = msi_enabled(pdev);
1184
1185 pci_default_write_config(pdev, addr, val, len);
1186
1187 is_enabled = msi_enabled(pdev);
1188
1189 if (!was_enabled) {
1190 if (is_enabled) {
1191 vfio_msi_enable(vdev);
1192 }
1193 } else {
1194 if (!is_enabled) {
1195 vfio_msi_disable(vdev);
1196 } else {
1197 vfio_update_msi(vdev);
1198 }
1199 }
1200 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX &&
1201 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) {
1202 int is_enabled, was_enabled = msix_enabled(pdev);
1203
1204 pci_default_write_config(pdev, addr, val, len);
1205
1206 is_enabled = msix_enabled(pdev);
1207
1208 if (!was_enabled && is_enabled) {
1209 vfio_msix_enable(vdev);
1210 } else if (was_enabled && !is_enabled) {
1211 vfio_msix_disable(vdev);
1212 }
1213 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) ||
1214 range_covers_byte(addr, len, PCI_COMMAND)) {
1215 pcibus_t old_addr[PCI_NUM_REGIONS - 1];
1216 int bar;
1217
1218 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1219 old_addr[bar] = pdev->io_regions[bar].addr;
1220 }
1221
1222 pci_default_write_config(pdev, addr, val, len);
1223
1224 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1225 if (old_addr[bar] != pdev->io_regions[bar].addr &&
1226 vdev->bars[bar].region.size > 0 &&
1227 vdev->bars[bar].region.size < qemu_real_host_page_size) {
1228 vfio_sub_page_bar_update_mapping(pdev, bar);
1229 }
1230 }
1231 } else {
1232
1233 pci_default_write_config(pdev, addr, val, len);
1234 }
1235}
1236
1237
1238
1239
1240static void vfio_disable_interrupts(VFIOPCIDevice *vdev)
1241{
1242
1243
1244
1245
1246
1247 if (vdev->interrupt == VFIO_INT_MSIX) {
1248 vfio_msix_disable(vdev);
1249 } else if (vdev->interrupt == VFIO_INT_MSI) {
1250 vfio_msi_disable(vdev);
1251 }
1252
1253 if (vdev->interrupt == VFIO_INT_INTx) {
1254 vfio_intx_disable(vdev);
1255 }
1256}
1257
1258static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1259{
1260 uint16_t ctrl;
1261 bool msi_64bit, msi_maskbit;
1262 int ret, entries;
1263 Error *err = NULL;
1264
1265 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl),
1266 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
1267 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS");
1268 return -errno;
1269 }
1270 ctrl = le16_to_cpu(ctrl);
1271
1272 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT);
1273 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT);
1274 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1);
1275
1276 trace_vfio_msi_setup(vdev->vbasedev.name, pos);
1277
1278 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err);
1279 if (ret < 0) {
1280 if (ret == -ENOTSUP) {
1281 return 0;
1282 }
1283 error_prepend(&err, "msi_init failed: ");
1284 error_propagate(errp, err);
1285 return ret;
1286 }
1287 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0);
1288
1289 return 0;
1290}
1291
1292static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev)
1293{
1294 off_t start, end;
1295 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region;
1296
1297
1298
1299
1300
1301 if (vfio_has_region_cap(&vdev->vbasedev, region->nr,
1302 VFIO_REGION_INFO_CAP_MSIX_MAPPABLE)) {
1303 return;
1304 }
1305
1306
1307
1308
1309
1310 if (region->nr_mmaps != 1 || region->mmaps[0].offset ||
1311 region->size != region->mmaps[0].size) {
1312 return;
1313 }
1314
1315
1316 start = vdev->msix->table_offset & qemu_real_host_page_mask;
1317 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset +
1318 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE));
1319
1320
1321
1322
1323
1324
1325
1326
1327 if (!start) {
1328 if (end >= region->size) {
1329 region->nr_mmaps = 0;
1330 g_free(region->mmaps);
1331 region->mmaps = NULL;
1332 trace_vfio_msix_fixup(vdev->vbasedev.name,
1333 vdev->msix->table_bar, 0, 0);
1334 } else {
1335 region->mmaps[0].offset = end;
1336 region->mmaps[0].size = region->size - end;
1337 trace_vfio_msix_fixup(vdev->vbasedev.name,
1338 vdev->msix->table_bar, region->mmaps[0].offset,
1339 region->mmaps[0].offset + region->mmaps[0].size);
1340 }
1341
1342
1343 } else if (end >= region->size) {
1344 region->mmaps[0].size = start;
1345 trace_vfio_msix_fixup(vdev->vbasedev.name,
1346 vdev->msix->table_bar, region->mmaps[0].offset,
1347 region->mmaps[0].offset + region->mmaps[0].size);
1348
1349
1350 } else {
1351 region->nr_mmaps = 2;
1352 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2);
1353
1354 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap));
1355
1356 region->mmaps[0].size = start;
1357 trace_vfio_msix_fixup(vdev->vbasedev.name,
1358 vdev->msix->table_bar, region->mmaps[0].offset,
1359 region->mmaps[0].offset + region->mmaps[0].size);
1360
1361 region->mmaps[1].offset = end;
1362 region->mmaps[1].size = region->size - end;
1363 trace_vfio_msix_fixup(vdev->vbasedev.name,
1364 vdev->msix->table_bar, region->mmaps[1].offset,
1365 region->mmaps[1].offset + region->mmaps[1].size);
1366 }
1367}
1368
1369static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp)
1370{
1371 int target_bar = -1;
1372 size_t msix_sz;
1373
1374 if (!vdev->msix || vdev->msix_relo == OFF_AUTOPCIBAR_OFF) {
1375 return;
1376 }
1377
1378
1379 msix_sz = (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) +
1380 (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8);
1381
1382 msix_sz = REAL_HOST_PAGE_ALIGN(msix_sz);
1383
1384 msix_sz = pow2ceil(msix_sz);
1385
1386 if (vdev->msix_relo == OFF_AUTOPCIBAR_AUTO) {
1387
1388
1389
1390
1391
1392
1393
1394
1395 if (target_bar < 0) {
1396 error_setg(errp, "No automatic MSI-X relocation available for "
1397 "device %04x:%04x", vdev->vendor_id, vdev->device_id);
1398 return;
1399 }
1400 } else {
1401 target_bar = (int)(vdev->msix_relo - OFF_AUTOPCIBAR_BAR0);
1402 }
1403
1404
1405 if (vdev->bars[target_bar].ioport) {
1406 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1407 "I/O port BAR", target_bar);
1408 return;
1409 }
1410
1411
1412 if (!vdev->bars[target_bar].size &&
1413 target_bar > 0 && vdev->bars[target_bar - 1].mem64) {
1414 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1415 "consumed by 64-bit BAR %d", target_bar, target_bar - 1);
1416 return;
1417 }
1418
1419
1420 if (vdev->bars[target_bar].size > 1 * GiB &&
1421 !vdev->bars[target_bar].mem64) {
1422 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1423 "no space to extend 32-bit BAR", target_bar);
1424 return;
1425 }
1426
1427
1428
1429
1430
1431
1432 if (!vdev->bars[target_bar].size) {
1433 if (target_bar < (PCI_ROM_SLOT - 1) &&
1434 !vdev->bars[target_bar + 1].size) {
1435 vdev->bars[target_bar].mem64 = true;
1436 vdev->bars[target_bar].type = PCI_BASE_ADDRESS_MEM_TYPE_64;
1437 }
1438 vdev->bars[target_bar].type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1439 vdev->bars[target_bar].size = msix_sz;
1440 vdev->msix->table_offset = 0;
1441 } else {
1442 vdev->bars[target_bar].size = MAX(vdev->bars[target_bar].size * 2,
1443 msix_sz * 2);
1444
1445
1446
1447
1448 vdev->msix->table_offset = vdev->bars[target_bar].size / 2;
1449 }
1450
1451 vdev->msix->table_bar = target_bar;
1452 vdev->msix->pba_bar = target_bar;
1453
1454 vdev->msix->pba_offset = vdev->msix->table_offset +
1455 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE);
1456
1457 trace_vfio_msix_relo(vdev->vbasedev.name,
1458 vdev->msix->table_bar, vdev->msix->table_offset);
1459}
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp)
1470{
1471 uint8_t pos;
1472 uint16_t ctrl;
1473 uint32_t table, pba;
1474 int fd = vdev->vbasedev.fd;
1475 VFIOMSIXInfo *msix;
1476
1477 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX);
1478 if (!pos) {
1479 return;
1480 }
1481
1482 if (pread(fd, &ctrl, sizeof(ctrl),
1483 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) {
1484 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS");
1485 return;
1486 }
1487
1488 if (pread(fd, &table, sizeof(table),
1489 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) {
1490 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE");
1491 return;
1492 }
1493
1494 if (pread(fd, &pba, sizeof(pba),
1495 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) {
1496 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA");
1497 return;
1498 }
1499
1500 ctrl = le16_to_cpu(ctrl);
1501 table = le32_to_cpu(table);
1502 pba = le32_to_cpu(pba);
1503
1504 msix = g_malloc0(sizeof(*msix));
1505 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
1506 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
1507 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
1508 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
1509 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
1510
1511
1512
1513
1514
1515
1516 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) {
1517
1518
1519
1520
1521
1522
1523 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO &&
1524 (vdev->device_id & 0xff00) == 0x5800) {
1525 msix->pba_offset = 0x1000;
1526 } else {
1527 error_setg(errp, "hardware reports invalid configuration, "
1528 "MSIX PBA outside of specified BAR");
1529 g_free(msix);
1530 return;
1531 }
1532 }
1533
1534 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar,
1535 msix->table_offset, msix->entries);
1536 vdev->msix = msix;
1537
1538 vfio_pci_fixup_msix_region(vdev);
1539
1540 vfio_pci_relocate_msix(vdev, errp);
1541}
1542
1543static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1544{
1545 int ret;
1546 Error *err = NULL;
1547
1548 vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) *
1549 sizeof(unsigned long));
1550 ret = msix_init(&vdev->pdev, vdev->msix->entries,
1551 vdev->bars[vdev->msix->table_bar].mr,
1552 vdev->msix->table_bar, vdev->msix->table_offset,
1553 vdev->bars[vdev->msix->pba_bar].mr,
1554 vdev->msix->pba_bar, vdev->msix->pba_offset, pos,
1555 &err);
1556 if (ret < 0) {
1557 if (ret == -ENOTSUP) {
1558 error_report_err(err);
1559 return 0;
1560 }
1561
1562 error_propagate(errp, err);
1563 return ret;
1564 }
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592 if (object_property_get_bool(OBJECT(qdev_get_machine()),
1593 "vfio-no-msix-emulation", NULL)) {
1594 memory_region_set_enabled(&vdev->pdev.msix_table_mmio, false);
1595 }
1596
1597 return 0;
1598}
1599
1600static void vfio_teardown_msi(VFIOPCIDevice *vdev)
1601{
1602 msi_uninit(&vdev->pdev);
1603
1604 if (vdev->msix) {
1605 msix_uninit(&vdev->pdev,
1606 vdev->bars[vdev->msix->table_bar].mr,
1607 vdev->bars[vdev->msix->pba_bar].mr);
1608 g_free(vdev->msix->pending);
1609 }
1610}
1611
1612
1613
1614
1615static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled)
1616{
1617 int i;
1618
1619 for (i = 0; i < PCI_ROM_SLOT; i++) {
1620 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled);
1621 }
1622}
1623
1624static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr)
1625{
1626 VFIOBAR *bar = &vdev->bars[nr];
1627
1628 uint32_t pci_bar;
1629 int ret;
1630
1631
1632 if (!bar->region.size) {
1633 return;
1634 }
1635
1636
1637 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar),
1638 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr));
1639 if (ret != sizeof(pci_bar)) {
1640 error_report("vfio: Failed to read BAR %d (%m)", nr);
1641 return;
1642 }
1643
1644 pci_bar = le32_to_cpu(pci_bar);
1645 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO);
1646 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64);
1647 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK :
1648 ~PCI_BASE_ADDRESS_MEM_MASK);
1649 bar->size = bar->region.size;
1650}
1651
1652static void vfio_bars_prepare(VFIOPCIDevice *vdev)
1653{
1654 int i;
1655
1656 for (i = 0; i < PCI_ROM_SLOT; i++) {
1657 vfio_bar_prepare(vdev, i);
1658 }
1659}
1660
1661static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)
1662{
1663 VFIOBAR *bar = &vdev->bars[nr];
1664 char *name;
1665
1666 if (!bar->size) {
1667 return;
1668 }
1669
1670 bar->mr = g_new0(MemoryRegion, 1);
1671 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr);
1672 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size);
1673 g_free(name);
1674
1675 if (bar->region.size) {
1676 memory_region_add_subregion(bar->mr, 0, bar->region.mem);
1677
1678 if (vfio_region_mmap(&bar->region)) {
1679 error_report("Failed to mmap %s BAR %d. Performance may be slow",
1680 vdev->vbasedev.name, nr);
1681 }
1682 }
1683
1684 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr);
1685}
1686
1687static void vfio_bars_register(VFIOPCIDevice *vdev)
1688{
1689 int i;
1690
1691 for (i = 0; i < PCI_ROM_SLOT; i++) {
1692 vfio_bar_register(vdev, i);
1693 }
1694}
1695
1696static void vfio_bars_exit(VFIOPCIDevice *vdev)
1697{
1698 int i;
1699
1700 for (i = 0; i < PCI_ROM_SLOT; i++) {
1701 VFIOBAR *bar = &vdev->bars[i];
1702
1703 vfio_bar_quirk_exit(vdev, i);
1704 vfio_region_exit(&bar->region);
1705 if (bar->region.size) {
1706 memory_region_del_subregion(bar->mr, bar->region.mem);
1707 }
1708 }
1709
1710 if (vdev->vga) {
1711 pci_unregister_vga(&vdev->pdev);
1712 vfio_vga_quirk_exit(vdev);
1713 }
1714}
1715
1716static void vfio_bars_finalize(VFIOPCIDevice *vdev)
1717{
1718 int i;
1719
1720 for (i = 0; i < PCI_ROM_SLOT; i++) {
1721 VFIOBAR *bar = &vdev->bars[i];
1722
1723 vfio_bar_quirk_finalize(vdev, i);
1724 vfio_region_finalize(&bar->region);
1725 if (bar->size) {
1726 object_unparent(OBJECT(bar->mr));
1727 g_free(bar->mr);
1728 }
1729 }
1730
1731 if (vdev->vga) {
1732 vfio_vga_quirk_finalize(vdev);
1733 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) {
1734 object_unparent(OBJECT(&vdev->vga->region[i].mem));
1735 }
1736 g_free(vdev->vga);
1737 }
1738}
1739
1740
1741
1742
1743static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos)
1744{
1745 uint8_t tmp;
1746 uint16_t next = PCI_CONFIG_SPACE_SIZE;
1747
1748 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp;
1749 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) {
1750 if (tmp > pos && tmp < next) {
1751 next = tmp;
1752 }
1753 }
1754
1755 return next - pos;
1756}
1757
1758
1759static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos)
1760{
1761 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE;
1762
1763 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp;
1764 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) {
1765 if (tmp > pos && tmp < next) {
1766 next = tmp;
1767 }
1768 }
1769
1770 return next - pos;
1771}
1772
1773static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask)
1774{
1775 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val);
1776}
1777
1778static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos,
1779 uint16_t val, uint16_t mask)
1780{
1781 vfio_set_word_bits(vdev->pdev.config + pos, val, mask);
1782 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask);
1783 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask);
1784}
1785
1786static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask)
1787{
1788 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val);
1789}
1790
1791static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos,
1792 uint32_t val, uint32_t mask)
1793{
1794 vfio_set_long_bits(vdev->pdev.config + pos, val, mask);
1795 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask);
1796 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask);
1797}
1798
1799static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
1800 Error **errp)
1801{
1802 uint16_t flags;
1803 uint8_t type;
1804
1805 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS);
1806 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4;
1807
1808 if (type != PCI_EXP_TYPE_ENDPOINT &&
1809 type != PCI_EXP_TYPE_LEG_END &&
1810 type != PCI_EXP_TYPE_RC_END) {
1811
1812 error_setg(errp, "assignment of PCIe type 0x%x "
1813 "devices is not currently supported", type);
1814 return -EINVAL;
1815 }
1816
1817 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) {
1818 PCIBus *bus = pci_get_bus(&vdev->pdev);
1819 PCIDevice *bridge;
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841 while (!pci_bus_is_root(bus)) {
1842 bridge = pci_bridge_get_device(bus);
1843 bus = pci_get_bus(bridge);
1844 }
1845
1846 if (pci_bus_is_express(bus)) {
1847 return 0;
1848 }
1849
1850 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) {
1851
1852
1853
1854
1855 if (type == PCI_EXP_TYPE_ENDPOINT) {
1856 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
1857 PCI_EXP_TYPE_RC_END << 4,
1858 PCI_EXP_FLAGS_TYPE);
1859
1860
1861 if (size > PCI_EXP_LNKCTL) {
1862 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0);
1863 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
1864 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0);
1865
1866#ifndef PCI_EXP_LNKCAP2
1867#define PCI_EXP_LNKCAP2 44
1868#endif
1869#ifndef PCI_EXP_LNKSTA2
1870#define PCI_EXP_LNKSTA2 50
1871#endif
1872
1873 if (size > PCI_EXP_LNKCAP2) {
1874 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0);
1875 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0);
1876 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0);
1877 }
1878 }
1879
1880 } else if (type == PCI_EXP_TYPE_LEG_END) {
1881
1882
1883
1884
1885 return 0;
1886 }
1887
1888 } else {
1889
1890
1891
1892
1893 if (type == PCI_EXP_TYPE_RC_END) {
1894 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
1895 PCI_EXP_TYPE_ENDPOINT << 4,
1896 PCI_EXP_FLAGS_TYPE);
1897 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP,
1898 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0);
1899 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
1900 }
1901
1902
1903 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA,
1904 pci_get_word(vdev->pdev.config + pos +
1905 PCI_EXP_LNKSTA),
1906 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS);
1907 }
1908
1909
1910
1911
1912
1913
1914
1915
1916 if ((flags & PCI_EXP_FLAGS_VERS) == 0) {
1917 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
1918 1, PCI_EXP_FLAGS_VERS);
1919 }
1920
1921 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size,
1922 errp);
1923 if (pos < 0) {
1924 return pos;
1925 }
1926
1927 vdev->pdev.exp.exp_cap = pos;
1928
1929 return pos;
1930}
1931
1932static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos)
1933{
1934 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP);
1935
1936 if (cap & PCI_EXP_DEVCAP_FLR) {
1937 trace_vfio_check_pcie_flr(vdev->vbasedev.name);
1938 vdev->has_flr = true;
1939 }
1940}
1941
1942static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos)
1943{
1944 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL);
1945
1946 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) {
1947 trace_vfio_check_pm_reset(vdev->vbasedev.name);
1948 vdev->has_pm_reset = true;
1949 }
1950}
1951
1952static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos)
1953{
1954 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP);
1955
1956 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) {
1957 trace_vfio_check_af_flr(vdev->vbasedev.name);
1958 vdev->has_flr = true;
1959 }
1960}
1961
1962static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp)
1963{
1964 PCIDevice *pdev = &vdev->pdev;
1965 uint8_t cap_id, next, size;
1966 int ret;
1967
1968 cap_id = pdev->config[pos];
1969 next = pdev->config[pos + PCI_CAP_LIST_NEXT];
1970
1971
1972
1973
1974
1975
1976
1977 size = vfio_std_cap_max_size(pdev, pos);
1978
1979
1980
1981
1982
1983
1984
1985
1986 if (next) {
1987 ret = vfio_add_std_cap(vdev, next, errp);
1988 if (ret) {
1989 return ret;
1990 }
1991 } else {
1992
1993 pdev->config[PCI_CAPABILITY_LIST] = 0;
1994 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff;
1995 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1996
1997 ret = vfio_add_virt_caps(vdev, errp);
1998 if (ret) {
1999 return ret;
2000 }
2001 }
2002
2003
2004 size = MIN(size, vfio_std_cap_max_size(pdev, pos));
2005
2006
2007 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff);
2008
2009 switch (cap_id) {
2010 case PCI_CAP_ID_MSI:
2011 ret = vfio_msi_setup(vdev, pos, errp);
2012 break;
2013 case PCI_CAP_ID_EXP:
2014 vfio_check_pcie_flr(vdev, pos);
2015 ret = vfio_setup_pcie_cap(vdev, pos, size, errp);
2016 break;
2017 case PCI_CAP_ID_MSIX:
2018 ret = vfio_msix_setup(vdev, pos, errp);
2019 break;
2020 case PCI_CAP_ID_PM:
2021 vfio_check_pm_reset(vdev, pos);
2022 vdev->pm_cap = pos;
2023 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2024 break;
2025 case PCI_CAP_ID_AF:
2026 vfio_check_af_flr(vdev, pos);
2027 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2028 break;
2029 default:
2030 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2031 break;
2032 }
2033
2034 if (ret < 0) {
2035 error_prepend(errp,
2036 "failed to add PCI capability 0x%x[0x%x]@0x%x: ",
2037 cap_id, size, pos);
2038 return ret;
2039 }
2040
2041 return 0;
2042}
2043
2044static void vfio_add_ext_cap(VFIOPCIDevice *vdev)
2045{
2046 PCIDevice *pdev = &vdev->pdev;
2047 uint32_t header;
2048 uint16_t cap_id, next, size;
2049 uint8_t cap_ver;
2050 uint8_t *config;
2051
2052
2053 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) ||
2054 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) {
2055 return;
2056 }
2057
2058
2059
2060
2061
2062
2063
2064 config = g_memdup(pdev->config, vdev->config_size);
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE,
2091 PCI_EXT_CAP(0xFFFF, 0, 0));
2092 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
2093 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0);
2094
2095 for (next = PCI_CONFIG_SPACE_SIZE; next;
2096 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) {
2097 header = pci_get_long(config + next);
2098 cap_id = PCI_EXT_CAP_ID(header);
2099 cap_ver = PCI_EXT_CAP_VER(header);
2100
2101
2102
2103
2104
2105
2106
2107 size = vfio_ext_cap_max_size(config, next);
2108
2109
2110 pci_long_test_and_set_mask(vdev->emulated_config_bits + next,
2111 PCI_EXT_CAP_NEXT_MASK);
2112
2113 switch (cap_id) {
2114 case 0:
2115 case PCI_EXT_CAP_ID_SRIOV:
2116 case PCI_EXT_CAP_ID_ARI:
2117 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next);
2118 break;
2119 default:
2120 pcie_add_capability(pdev, cap_id, cap_ver, next, size);
2121 }
2122
2123 }
2124
2125
2126 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) {
2127 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0);
2128 }
2129
2130 g_free(config);
2131 return;
2132}
2133
2134static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp)
2135{
2136 PCIDevice *pdev = &vdev->pdev;
2137 int ret;
2138
2139 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) ||
2140 !pdev->config[PCI_CAPABILITY_LIST]) {
2141 return 0;
2142 }
2143
2144 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp);
2145 if (ret) {
2146 return ret;
2147 }
2148
2149 vfio_add_ext_cap(vdev);
2150 return 0;
2151}
2152
2153static void vfio_pci_pre_reset(VFIOPCIDevice *vdev)
2154{
2155 PCIDevice *pdev = &vdev->pdev;
2156 uint16_t cmd;
2157
2158 vfio_disable_interrupts(vdev);
2159
2160
2161 if (vdev->pm_cap) {
2162 uint16_t pmcsr;
2163 uint8_t state;
2164
2165 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
2166 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2167 if (state) {
2168 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2169 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2);
2170
2171 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
2172 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2173 if (state) {
2174 error_report("vfio: Unable to power on device, stuck in D%d",
2175 state);
2176 }
2177 }
2178 }
2179
2180
2181
2182
2183
2184 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2);
2185 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
2186 PCI_COMMAND_INTX_DISABLE);
2187 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2);
2188}
2189
2190static void vfio_pci_post_reset(VFIOPCIDevice *vdev)
2191{
2192 Error *err = NULL;
2193 int nr;
2194
2195 vfio_intx_enable(vdev, &err);
2196 if (err) {
2197 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name);
2198 }
2199
2200 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) {
2201 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr);
2202 uint32_t val = 0;
2203 uint32_t len = sizeof(val);
2204
2205 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) {
2206 error_report("%s(%s) reset bar %d failed: %m", __func__,
2207 vdev->vbasedev.name, nr);
2208 }
2209 }
2210
2211 vfio_quirk_reset(vdev);
2212}
2213
2214static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name)
2215{
2216 char tmp[13];
2217
2218 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain,
2219 addr->bus, addr->slot, addr->function);
2220
2221 return (strcmp(tmp, name) == 0);
2222}
2223
2224static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single)
2225{
2226 VFIOGroup *group;
2227 struct vfio_pci_hot_reset_info *info;
2228 struct vfio_pci_dependent_device *devices;
2229 struct vfio_pci_hot_reset *reset;
2230 int32_t *fds;
2231 int ret, i, count;
2232 bool multi = false;
2233
2234 trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi");
2235
2236 if (!single) {
2237 vfio_pci_pre_reset(vdev);
2238 }
2239 vdev->vbasedev.needs_reset = false;
2240
2241 info = g_malloc0(sizeof(*info));
2242 info->argsz = sizeof(*info);
2243
2244 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2245 if (ret && errno != ENOSPC) {
2246 ret = -errno;
2247 if (!vdev->has_pm_reset) {
2248 error_report("vfio: Cannot reset device %s, "
2249 "no available reset mechanism.", vdev->vbasedev.name);
2250 }
2251 goto out_single;
2252 }
2253
2254 count = info->count;
2255 info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices)));
2256 info->argsz = sizeof(*info) + (count * sizeof(*devices));
2257 devices = &info->devices[0];
2258
2259 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2260 if (ret) {
2261 ret = -errno;
2262 error_report("vfio: hot reset info failed: %m");
2263 goto out_single;
2264 }
2265
2266 trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name);
2267
2268
2269 for (i = 0; i < info->count; i++) {
2270 PCIHostDeviceAddress host;
2271 VFIOPCIDevice *tmp;
2272 VFIODevice *vbasedev_iter;
2273
2274 host.domain = devices[i].segment;
2275 host.bus = devices[i].bus;
2276 host.slot = PCI_SLOT(devices[i].devfn);
2277 host.function = PCI_FUNC(devices[i].devfn);
2278
2279 trace_vfio_pci_hot_reset_dep_devices(host.domain,
2280 host.bus, host.slot, host.function, devices[i].group_id);
2281
2282 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) {
2283 continue;
2284 }
2285
2286 QLIST_FOREACH(group, &vfio_group_list, next) {
2287 if (group->groupid == devices[i].group_id) {
2288 break;
2289 }
2290 }
2291
2292 if (!group) {
2293 if (!vdev->has_pm_reset) {
2294 error_report("vfio: Cannot reset device %s, "
2295 "depends on group %d which is not owned.",
2296 vdev->vbasedev.name, devices[i].group_id);
2297 }
2298 ret = -EPERM;
2299 goto out;
2300 }
2301
2302
2303 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) {
2304 if (!vbasedev_iter->dev->realized ||
2305 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) {
2306 continue;
2307 }
2308 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev);
2309 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) {
2310 if (single) {
2311 ret = -EINVAL;
2312 goto out_single;
2313 }
2314 vfio_pci_pre_reset(tmp);
2315 tmp->vbasedev.needs_reset = false;
2316 multi = true;
2317 break;
2318 }
2319 }
2320 }
2321
2322 if (!single && !multi) {
2323 ret = -EINVAL;
2324 goto out_single;
2325 }
2326
2327
2328 count = 0;
2329 QLIST_FOREACH(group, &vfio_group_list, next) {
2330 for (i = 0; i < info->count; i++) {
2331 if (group->groupid == devices[i].group_id) {
2332 count++;
2333 break;
2334 }
2335 }
2336 }
2337
2338 reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds)));
2339 reset->argsz = sizeof(*reset) + (count * sizeof(*fds));
2340 fds = &reset->group_fds[0];
2341
2342
2343 QLIST_FOREACH(group, &vfio_group_list, next) {
2344 for (i = 0; i < info->count; i++) {
2345 if (group->groupid == devices[i].group_id) {
2346 fds[reset->count++] = group->fd;
2347 break;
2348 }
2349 }
2350 }
2351
2352
2353 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset);
2354 g_free(reset);
2355
2356 trace_vfio_pci_hot_reset_result(vdev->vbasedev.name,
2357 ret ? "%m" : "Success");
2358
2359out:
2360
2361 for (i = 0; i < info->count; i++) {
2362 PCIHostDeviceAddress host;
2363 VFIOPCIDevice *tmp;
2364 VFIODevice *vbasedev_iter;
2365
2366 host.domain = devices[i].segment;
2367 host.bus = devices[i].bus;
2368 host.slot = PCI_SLOT(devices[i].devfn);
2369 host.function = PCI_FUNC(devices[i].devfn);
2370
2371 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) {
2372 continue;
2373 }
2374
2375 QLIST_FOREACH(group, &vfio_group_list, next) {
2376 if (group->groupid == devices[i].group_id) {
2377 break;
2378 }
2379 }
2380
2381 if (!group) {
2382 break;
2383 }
2384
2385 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) {
2386 if (!vbasedev_iter->dev->realized ||
2387 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) {
2388 continue;
2389 }
2390 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev);
2391 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) {
2392 vfio_pci_post_reset(tmp);
2393 break;
2394 }
2395 }
2396 }
2397out_single:
2398 if (!single) {
2399 vfio_pci_post_reset(vdev);
2400 }
2401 g_free(info);
2402
2403 return ret;
2404}
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev)
2422{
2423 return vfio_pci_hot_reset(vdev, true);
2424}
2425
2426static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev)
2427{
2428 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2429 return vfio_pci_hot_reset(vdev, false);
2430}
2431
2432static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev)
2433{
2434 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2435 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) {
2436 vbasedev->needs_reset = true;
2437 }
2438}
2439
2440static VFIODeviceOps vfio_pci_ops = {
2441 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset,
2442 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi,
2443 .vfio_eoi = vfio_intx_eoi,
2444};
2445
2446int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp)
2447{
2448 VFIODevice *vbasedev = &vdev->vbasedev;
2449 struct vfio_region_info *reg_info;
2450 int ret;
2451
2452 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info);
2453 if (ret) {
2454 error_setg_errno(errp, -ret,
2455 "failed getting region info for VGA region index %d",
2456 VFIO_PCI_VGA_REGION_INDEX);
2457 return ret;
2458 }
2459
2460 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) ||
2461 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) ||
2462 reg_info->size < 0xbffff + 1) {
2463 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx",
2464 (unsigned long)reg_info->flags,
2465 (unsigned long)reg_info->size);
2466 g_free(reg_info);
2467 return -EINVAL;
2468 }
2469
2470 vdev->vga = g_new0(VFIOVGA, 1);
2471
2472 vdev->vga->fd_offset = reg_info->offset;
2473 vdev->vga->fd = vdev->vbasedev.fd;
2474
2475 g_free(reg_info);
2476
2477 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE;
2478 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM;
2479 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks);
2480
2481 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2482 OBJECT(vdev), &vfio_vga_ops,
2483 &vdev->vga->region[QEMU_PCI_VGA_MEM],
2484 "vfio-vga-mmio@0xa0000",
2485 QEMU_PCI_VGA_MEM_SIZE);
2486
2487 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE;
2488 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO;
2489 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks);
2490
2491 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2492 OBJECT(vdev), &vfio_vga_ops,
2493 &vdev->vga->region[QEMU_PCI_VGA_IO_LO],
2494 "vfio-vga-io@0x3b0",
2495 QEMU_PCI_VGA_IO_LO_SIZE);
2496
2497 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE;
2498 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI;
2499 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks);
2500
2501 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem,
2502 OBJECT(vdev), &vfio_vga_ops,
2503 &vdev->vga->region[QEMU_PCI_VGA_IO_HI],
2504 "vfio-vga-io@0x3c0",
2505 QEMU_PCI_VGA_IO_HI_SIZE);
2506
2507 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2508 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2509 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem);
2510
2511 return 0;
2512}
2513
2514static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp)
2515{
2516 VFIODevice *vbasedev = &vdev->vbasedev;
2517 struct vfio_region_info *reg_info;
2518 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
2519 int i, ret = -1;
2520
2521
2522 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) {
2523 error_setg(errp, "this isn't a PCI device");
2524 return;
2525 }
2526
2527 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) {
2528 error_setg(errp, "unexpected number of io regions %u",
2529 vbasedev->num_regions);
2530 return;
2531 }
2532
2533 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) {
2534 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs);
2535 return;
2536 }
2537
2538 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) {
2539 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i);
2540
2541 ret = vfio_region_setup(OBJECT(vdev), vbasedev,
2542 &vdev->bars[i].region, i, name);
2543 g_free(name);
2544
2545 if (ret) {
2546 error_setg_errno(errp, -ret, "failed to get region %d info", i);
2547 return;
2548 }
2549
2550 QLIST_INIT(&vdev->bars[i].quirks);
2551 }
2552
2553 ret = vfio_get_region_info(vbasedev,
2554 VFIO_PCI_CONFIG_REGION_INDEX, ®_info);
2555 if (ret) {
2556 error_setg_errno(errp, -ret, "failed to get config info");
2557 return;
2558 }
2559
2560 trace_vfio_populate_device_config(vdev->vbasedev.name,
2561 (unsigned long)reg_info->size,
2562 (unsigned long)reg_info->offset,
2563 (unsigned long)reg_info->flags);
2564
2565 vdev->config_size = reg_info->size;
2566 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
2567 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
2568 }
2569 vdev->config_offset = reg_info->offset;
2570
2571 g_free(reg_info);
2572
2573 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) {
2574 ret = vfio_populate_vga(vdev, errp);
2575 if (ret) {
2576 error_append_hint(errp, "device does not support "
2577 "requested feature x-vga\n");
2578 return;
2579 }
2580 }
2581
2582 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX;
2583
2584 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
2585 if (ret) {
2586
2587 trace_vfio_populate_device_get_irq_info_failure();
2588 } else if (irq_info.count == 1) {
2589 vdev->pci_aer = true;
2590 } else {
2591 error_report(WARN_PREFIX
2592 "Could not enable error recovery for the device",
2593 vbasedev->name);
2594 }
2595}
2596
2597static void vfio_put_device(VFIOPCIDevice *vdev)
2598{
2599 g_free(vdev->vbasedev.name);
2600 g_free(vdev->msix);
2601
2602 vfio_put_base_device(&vdev->vbasedev);
2603}
2604
2605static void vfio_err_notifier_handler(void *opaque)
2606{
2607 VFIOPCIDevice *vdev = opaque;
2608
2609 if (!event_notifier_test_and_clear(&vdev->err_notifier)) {
2610 return;
2611 }
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name);
2623
2624 vm_stop(RUN_STATE_INTERNAL_ERROR);
2625}
2626
2627
2628
2629
2630
2631
2632
2633static void vfio_register_err_notifier(VFIOPCIDevice *vdev)
2634{
2635 int ret;
2636 int argsz;
2637 struct vfio_irq_set *irq_set;
2638 int32_t *pfd;
2639
2640 if (!vdev->pci_aer) {
2641 return;
2642 }
2643
2644 if (event_notifier_init(&vdev->err_notifier, 0)) {
2645 error_report("vfio: Unable to init event notifier for error detection");
2646 vdev->pci_aer = false;
2647 return;
2648 }
2649
2650 argsz = sizeof(*irq_set) + sizeof(*pfd);
2651
2652 irq_set = g_malloc0(argsz);
2653 irq_set->argsz = argsz;
2654 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
2655 VFIO_IRQ_SET_ACTION_TRIGGER;
2656 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX;
2657 irq_set->start = 0;
2658 irq_set->count = 1;
2659 pfd = (int32_t *)&irq_set->data;
2660
2661 *pfd = event_notifier_get_fd(&vdev->err_notifier);
2662 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev);
2663
2664 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
2665 if (ret) {
2666 error_report("vfio: Failed to set up error notification");
2667 qemu_set_fd_handler(*pfd, NULL, NULL, vdev);
2668 event_notifier_cleanup(&vdev->err_notifier);
2669 vdev->pci_aer = false;
2670 }
2671 g_free(irq_set);
2672}
2673
2674static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev)
2675{
2676 int argsz;
2677 struct vfio_irq_set *irq_set;
2678 int32_t *pfd;
2679 int ret;
2680
2681 if (!vdev->pci_aer) {
2682 return;
2683 }
2684
2685 argsz = sizeof(*irq_set) + sizeof(*pfd);
2686
2687 irq_set = g_malloc0(argsz);
2688 irq_set->argsz = argsz;
2689 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
2690 VFIO_IRQ_SET_ACTION_TRIGGER;
2691 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX;
2692 irq_set->start = 0;
2693 irq_set->count = 1;
2694 pfd = (int32_t *)&irq_set->data;
2695 *pfd = -1;
2696
2697 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
2698 if (ret) {
2699 error_report("vfio: Failed to de-assign error fd: %m");
2700 }
2701 g_free(irq_set);
2702 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier),
2703 NULL, NULL, vdev);
2704 event_notifier_cleanup(&vdev->err_notifier);
2705}
2706
2707static void vfio_req_notifier_handler(void *opaque)
2708{
2709 VFIOPCIDevice *vdev = opaque;
2710 Error *err = NULL;
2711
2712 if (!event_notifier_test_and_clear(&vdev->req_notifier)) {
2713 return;
2714 }
2715
2716 qdev_unplug(&vdev->pdev.qdev, &err);
2717 if (err) {
2718 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name);
2719 }
2720}
2721
2722static void vfio_register_req_notifier(VFIOPCIDevice *vdev)
2723{
2724 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info),
2725 .index = VFIO_PCI_REQ_IRQ_INDEX };
2726 int argsz;
2727 struct vfio_irq_set *irq_set;
2728 int32_t *pfd;
2729
2730 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) {
2731 return;
2732 }
2733
2734 if (ioctl(vdev->vbasedev.fd,
2735 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) {
2736 return;
2737 }
2738
2739 if (event_notifier_init(&vdev->req_notifier, 0)) {
2740 error_report("vfio: Unable to init event notifier for device request");
2741 return;
2742 }
2743
2744 argsz = sizeof(*irq_set) + sizeof(*pfd);
2745
2746 irq_set = g_malloc0(argsz);
2747 irq_set->argsz = argsz;
2748 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
2749 VFIO_IRQ_SET_ACTION_TRIGGER;
2750 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX;
2751 irq_set->start = 0;
2752 irq_set->count = 1;
2753 pfd = (int32_t *)&irq_set->data;
2754
2755 *pfd = event_notifier_get_fd(&vdev->req_notifier);
2756 qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev);
2757
2758 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) {
2759 error_report("vfio: Failed to set up device request notification");
2760 qemu_set_fd_handler(*pfd, NULL, NULL, vdev);
2761 event_notifier_cleanup(&vdev->req_notifier);
2762 } else {
2763 vdev->req_enabled = true;
2764 }
2765
2766 g_free(irq_set);
2767}
2768
2769static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev)
2770{
2771 int argsz;
2772 struct vfio_irq_set *irq_set;
2773 int32_t *pfd;
2774
2775 if (!vdev->req_enabled) {
2776 return;
2777 }
2778
2779 argsz = sizeof(*irq_set) + sizeof(*pfd);
2780
2781 irq_set = g_malloc0(argsz);
2782 irq_set->argsz = argsz;
2783 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
2784 VFIO_IRQ_SET_ACTION_TRIGGER;
2785 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX;
2786 irq_set->start = 0;
2787 irq_set->count = 1;
2788 pfd = (int32_t *)&irq_set->data;
2789 *pfd = -1;
2790
2791 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) {
2792 error_report("vfio: Failed to de-assign device request fd: %m");
2793 }
2794 g_free(irq_set);
2795 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier),
2796 NULL, NULL, vdev);
2797 event_notifier_cleanup(&vdev->req_notifier);
2798
2799 vdev->req_enabled = false;
2800}
2801
2802static void vfio_realize(PCIDevice *pdev, Error **errp)
2803{
2804 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
2805 VFIODevice *vbasedev_iter;
2806 VFIOGroup *group;
2807 char *tmp, group_path[PATH_MAX], *group_name;
2808 Error *err = NULL;
2809 ssize_t len;
2810 struct stat st;
2811 int groupid;
2812 int i, ret;
2813
2814 if (!vdev->vbasedev.sysfsdev) {
2815 if (!(~vdev->host.domain || ~vdev->host.bus ||
2816 ~vdev->host.slot || ~vdev->host.function)) {
2817 error_setg(errp, "No provided host device");
2818 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F "
2819 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n");
2820 return;
2821 }
2822 vdev->vbasedev.sysfsdev =
2823 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x",
2824 vdev->host.domain, vdev->host.bus,
2825 vdev->host.slot, vdev->host.function);
2826 }
2827
2828 if (stat(vdev->vbasedev.sysfsdev, &st) < 0) {
2829 error_setg_errno(errp, errno, "no such host device");
2830 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.sysfsdev);
2831 return;
2832 }
2833
2834 vdev->vbasedev.name = g_path_get_basename(vdev->vbasedev.sysfsdev);
2835 vdev->vbasedev.ops = &vfio_pci_ops;
2836 vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI;
2837 vdev->vbasedev.dev = &vdev->pdev.qdev;
2838
2839 tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev);
2840 len = readlink(tmp, group_path, sizeof(group_path));
2841 g_free(tmp);
2842
2843 if (len <= 0 || len >= sizeof(group_path)) {
2844 error_setg_errno(errp, len < 0 ? errno : ENAMETOOLONG,
2845 "no iommu_group found");
2846 goto error;
2847 }
2848
2849 group_path[len] = 0;
2850
2851 group_name = basename(group_path);
2852 if (sscanf(group_name, "%d", &groupid) != 1) {
2853 error_setg_errno(errp, errno, "failed to read %s", group_path);
2854 goto error;
2855 }
2856
2857 trace_vfio_realize(vdev->vbasedev.name, groupid);
2858
2859 group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev), errp);
2860 if (!group) {
2861 goto error;
2862 }
2863
2864 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) {
2865 if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) {
2866 error_setg(errp, "device is already attached");
2867 vfio_put_group(group);
2868 goto error;
2869 }
2870 }
2871
2872 ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev, errp);
2873 if (ret) {
2874 vfio_put_group(group);
2875 goto error;
2876 }
2877
2878 vfio_populate_device(vdev, &err);
2879 if (err) {
2880 error_propagate(errp, err);
2881 goto error;
2882 }
2883
2884
2885 ret = pread(vdev->vbasedev.fd, vdev->pdev.config,
2886 MIN(pci_config_size(&vdev->pdev), vdev->config_size),
2887 vdev->config_offset);
2888 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) {
2889 ret = ret < 0 ? -errno : -EFAULT;
2890 error_setg_errno(errp, -ret, "failed to read device config space");
2891 goto error;
2892 }
2893
2894
2895 vdev->emulated_config_bits = g_malloc0(vdev->config_size);
2896
2897
2898 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4);
2899
2900 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4);
2901
2902
2903
2904
2905
2906
2907 if (vdev->vendor_id != PCI_ANY_ID) {
2908 if (vdev->vendor_id >= 0xffff) {
2909 error_setg(errp, "invalid PCI vendor ID provided");
2910 goto error;
2911 }
2912 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0);
2913 trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id);
2914 } else {
2915 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2916 }
2917
2918 if (vdev->device_id != PCI_ANY_ID) {
2919 if (vdev->device_id > 0xffff) {
2920 error_setg(errp, "invalid PCI device ID provided");
2921 goto error;
2922 }
2923 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0);
2924 trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id);
2925 } else {
2926 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2927 }
2928
2929 if (vdev->sub_vendor_id != PCI_ANY_ID) {
2930 if (vdev->sub_vendor_id > 0xffff) {
2931 error_setg(errp, "invalid PCI subsystem vendor ID provided");
2932 goto error;
2933 }
2934 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID,
2935 vdev->sub_vendor_id, ~0);
2936 trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name,
2937 vdev->sub_vendor_id);
2938 }
2939
2940 if (vdev->sub_device_id != PCI_ANY_ID) {
2941 if (vdev->sub_device_id > 0xffff) {
2942 error_setg(errp, "invalid PCI subsystem device ID provided");
2943 goto error;
2944 }
2945 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0);
2946 trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name,
2947 vdev->sub_device_id);
2948 }
2949
2950
2951 vdev->emulated_config_bits[PCI_HEADER_TYPE] =
2952 PCI_HEADER_TYPE_MULTI_FUNCTION;
2953
2954
2955 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
2956 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
2957 } else {
2958 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
2959 }
2960
2961
2962
2963
2964
2965
2966 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24);
2967 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4);
2968
2969 vfio_pci_size_rom(vdev);
2970
2971 vfio_bars_prepare(vdev);
2972
2973 vfio_msix_early_setup(vdev, &err);
2974 if (err) {
2975 error_propagate(errp, err);
2976 goto error;
2977 }
2978
2979 vfio_bars_register(vdev);
2980
2981 ret = vfio_add_capabilities(vdev, errp);
2982 if (ret) {
2983 goto out_teardown;
2984 }
2985
2986 if (vdev->vga) {
2987 vfio_vga_quirk_setup(vdev);
2988 }
2989
2990 for (i = 0; i < PCI_ROM_SLOT; i++) {
2991 vfio_bar_quirk_setup(vdev, i);
2992 }
2993
2994 if (!vdev->igd_opregion &&
2995 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) {
2996 struct vfio_region_info *opregion;
2997
2998 if (vdev->pdev.qdev.hotplugged) {
2999 error_setg(errp,
3000 "cannot support IGD OpRegion feature on hotplugged "
3001 "device");
3002 goto out_teardown;
3003 }
3004
3005 ret = vfio_get_dev_region_info(&vdev->vbasedev,
3006 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
3007 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion);
3008 if (ret) {
3009 error_setg_errno(errp, -ret,
3010 "does not support requested IGD OpRegion feature");
3011 goto out_teardown;
3012 }
3013
3014 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp);
3015 g_free(opregion);
3016 if (ret) {
3017 goto out_teardown;
3018 }
3019 }
3020
3021
3022 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) {
3023 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff,
3024 MSIX_CAP_LENGTH);
3025 }
3026
3027 if (pdev->cap_present & QEMU_PCI_CAP_MSI) {
3028 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff,
3029 vdev->msi_cap_size);
3030 }
3031
3032 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) {
3033 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3034 vfio_intx_mmap_enable, vdev);
3035 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update);
3036 ret = vfio_intx_enable(vdev, errp);
3037 if (ret) {
3038 goto out_teardown;
3039 }
3040 }
3041
3042 if (vdev->display != ON_OFF_AUTO_OFF) {
3043 ret = vfio_display_probe(vdev, errp);
3044 if (ret) {
3045 goto out_teardown;
3046 }
3047 }
3048
3049 vfio_register_err_notifier(vdev);
3050 vfio_register_req_notifier(vdev);
3051 vfio_setup_resetfn_quirk(vdev);
3052
3053 return;
3054
3055out_teardown:
3056 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3057 vfio_teardown_msi(vdev);
3058 vfio_bars_exit(vdev);
3059error:
3060 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.name);
3061}
3062
3063static void vfio_instance_finalize(Object *obj)
3064{
3065 PCIDevice *pci_dev = PCI_DEVICE(obj);
3066 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev);
3067 VFIOGroup *group = vdev->vbasedev.group;
3068
3069 vfio_display_finalize(vdev);
3070 vfio_bars_finalize(vdev);
3071 g_free(vdev->emulated_config_bits);
3072 g_free(vdev->rom);
3073
3074
3075
3076
3077
3078
3079
3080 vfio_put_device(vdev);
3081 vfio_put_group(group);
3082}
3083
3084static void vfio_exitfn(PCIDevice *pdev)
3085{
3086 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
3087
3088 vfio_unregister_req_notifier(vdev);
3089 vfio_unregister_err_notifier(vdev);
3090 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3091 vfio_disable_interrupts(vdev);
3092 if (vdev->intx.mmap_timer) {
3093 timer_free(vdev->intx.mmap_timer);
3094 }
3095 vfio_teardown_msi(vdev);
3096 vfio_bars_exit(vdev);
3097}
3098
3099static void vfio_pci_reset(DeviceState *dev)
3100{
3101 PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
3102 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev);
3103
3104 trace_vfio_pci_reset(vdev->vbasedev.name);
3105
3106 vfio_pci_pre_reset(vdev);
3107
3108 if (vdev->display != ON_OFF_AUTO_OFF) {
3109 vfio_display_reset(vdev);
3110 }
3111
3112 if (vdev->resetfn && !vdev->resetfn(vdev)) {
3113 goto post_reset;
3114 }
3115
3116 if (vdev->vbasedev.reset_works &&
3117 (vdev->has_flr || !vdev->has_pm_reset) &&
3118 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3119 trace_vfio_pci_reset_flr(vdev->vbasedev.name);
3120 goto post_reset;
3121 }
3122
3123
3124 if (!vfio_pci_hot_reset_one(vdev)) {
3125 goto post_reset;
3126 }
3127
3128
3129 if (vdev->vbasedev.reset_works && vdev->has_pm_reset &&
3130 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3131 trace_vfio_pci_reset_pm(vdev->vbasedev.name);
3132 goto post_reset;
3133 }
3134
3135post_reset:
3136 vfio_pci_post_reset(vdev);
3137}
3138
3139static void vfio_instance_init(Object *obj)
3140{
3141 PCIDevice *pci_dev = PCI_DEVICE(obj);
3142 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj));
3143
3144 device_add_bootindex_property(obj, &vdev->bootindex,
3145 "bootindex", NULL,
3146 &pci_dev->qdev, NULL);
3147 vdev->host.domain = ~0U;
3148 vdev->host.bus = ~0U;
3149 vdev->host.slot = ~0U;
3150 vdev->host.function = ~0U;
3151
3152 vdev->nv_gpudirect_clique = 0xFF;
3153
3154
3155
3156 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
3157}
3158
3159static Property vfio_pci_dev_properties[] = {
3160 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host),
3161 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev),
3162 DEFINE_PROP_ON_OFF_AUTO("display", VFIOPCIDevice,
3163 display, ON_OFF_AUTO_OFF),
3164 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice,
3165 intx.mmap_timeout, 1100),
3166 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features,
3167 VFIO_FEATURE_ENABLE_VGA_BIT, false),
3168 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features,
3169 VFIO_FEATURE_ENABLE_REQ_BIT, true),
3170 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features,
3171 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false),
3172 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false),
3173 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false),
3174 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false),
3175 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false),
3176 DEFINE_PROP_BOOL("x-no-geforce-quirks", VFIOPCIDevice,
3177 no_geforce_quirks, false),
3178 DEFINE_PROP_BOOL("x-no-kvm-ioeventfd", VFIOPCIDevice, no_kvm_ioeventfd,
3179 false),
3180 DEFINE_PROP_BOOL("x-no-vfio-ioeventfd", VFIOPCIDevice, no_vfio_ioeventfd,
3181 false),
3182 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID),
3183 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID),
3184 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice,
3185 sub_vendor_id, PCI_ANY_ID),
3186 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice,
3187 sub_device_id, PCI_ANY_ID),
3188 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0),
3189 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice,
3190 nv_gpudirect_clique,
3191 qdev_prop_nv_gpudirect_clique, uint8_t),
3192 DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_relo,
3193 OFF_AUTOPCIBAR_OFF),
3194
3195
3196
3197
3198
3199 DEFINE_PROP_END_OF_LIST(),
3200};
3201
3202static const VMStateDescription vfio_pci_vmstate = {
3203 .name = "vfio-pci",
3204 .unmigratable = 1,
3205};
3206
3207static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
3208{
3209 DeviceClass *dc = DEVICE_CLASS(klass);
3210 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass);
3211
3212 dc->reset = vfio_pci_reset;
3213 dc->props = vfio_pci_dev_properties;
3214 dc->vmsd = &vfio_pci_vmstate;
3215 dc->desc = "VFIO-based PCI device assignment";
3216 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
3217 pdc->realize = vfio_realize;
3218 pdc->exit = vfio_exitfn;
3219 pdc->config_read = vfio_pci_read_config;
3220 pdc->config_write = vfio_pci_write_config;
3221}
3222
3223static const TypeInfo vfio_pci_dev_info = {
3224 .name = "vfio-pci",
3225 .parent = TYPE_PCI_DEVICE,
3226 .instance_size = sizeof(VFIOPCIDevice),
3227 .class_init = vfio_pci_dev_class_init,
3228 .instance_init = vfio_instance_init,
3229 .instance_finalize = vfio_instance_finalize,
3230 .interfaces = (InterfaceInfo[]) {
3231 { INTERFACE_PCIE_DEVICE },
3232 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3233 { }
3234 },
3235};
3236
3237static void register_vfio_pci_dev_type(void)
3238{
3239 type_register_static(&vfio_pci_dev_info);
3240}
3241
3242type_init(register_vfio_pci_dev_type)
3243