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12#ifndef HW_VFIO_VFIO_PCI_H
13#define HW_VFIO_VFIO_PCI_H
14
15#include "qemu-common.h"
16#include "exec/memory.h"
17#include "hw/pci/pci.h"
18#include "hw/vfio/vfio-common.h"
19#include "qemu/event_notifier.h"
20#include "qemu/queue.h"
21#include "qemu/timer.h"
22
23#define PCI_ANY_ID (~0)
24
25struct VFIOPCIDevice;
26
27typedef struct VFIOIOEventFD {
28 QLIST_ENTRY(VFIOIOEventFD) next;
29 MemoryRegion *mr;
30 hwaddr addr;
31 unsigned size;
32 uint64_t data;
33 EventNotifier e;
34 VFIORegion *region;
35 hwaddr region_addr;
36 bool dynamic;
37 bool vfio;
38} VFIOIOEventFD;
39
40typedef struct VFIOQuirk {
41 QLIST_ENTRY(VFIOQuirk) next;
42 void *data;
43 QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
44 int nr_mem;
45 MemoryRegion *mem;
46 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
47} VFIOQuirk;
48
49typedef struct VFIOBAR {
50 VFIORegion region;
51 MemoryRegion *mr;
52 size_t size;
53 uint8_t type;
54 bool ioport;
55 bool mem64;
56 QLIST_HEAD(, VFIOQuirk) quirks;
57} VFIOBAR;
58
59typedef struct VFIOVGARegion {
60 MemoryRegion mem;
61 off_t offset;
62 int nr;
63 QLIST_HEAD(, VFIOQuirk) quirks;
64} VFIOVGARegion;
65
66typedef struct VFIOVGA {
67 off_t fd_offset;
68 int fd;
69 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
70} VFIOVGA;
71
72typedef struct VFIOINTx {
73 bool pending;
74 bool kvm_accel;
75 uint8_t pin;
76 EventNotifier interrupt;
77 EventNotifier unmask;
78 PCIINTxRoute route;
79 uint32_t mmap_timeout;
80 QEMUTimer *mmap_timer;
81} VFIOINTx;
82
83typedef struct VFIOMSIVector {
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91
92
93 EventNotifier interrupt;
94 EventNotifier kvm_interrupt;
95 struct VFIOPCIDevice *vdev;
96 int virq;
97 bool use;
98} VFIOMSIVector;
99
100enum {
101 VFIO_INT_NONE = 0,
102 VFIO_INT_INTx = 1,
103 VFIO_INT_MSI = 2,
104 VFIO_INT_MSIX = 3,
105};
106
107
108typedef struct VFIOMSIXInfo {
109 uint8_t table_bar;
110 uint8_t pba_bar;
111 uint16_t entries;
112 uint32_t table_offset;
113 uint32_t pba_offset;
114 unsigned long *pending;
115} VFIOMSIXInfo;
116
117typedef struct VFIOPCIDevice {
118 PCIDevice pdev;
119 VFIODevice vbasedev;
120 VFIOINTx intx;
121 unsigned int config_size;
122 uint8_t *emulated_config_bits;
123 off_t config_offset;
124 unsigned int rom_size;
125 off_t rom_offset;
126 void *rom;
127 int msi_cap_size;
128 VFIOMSIVector *msi_vectors;
129 VFIOMSIXInfo *msix;
130 int nr_vectors;
131 int interrupt;
132 VFIOBAR bars[PCI_NUM_REGIONS - 1];
133 VFIOVGA *vga;
134 void *igd_opregion;
135 PCIHostDeviceAddress host;
136 EventNotifier err_notifier;
137 EventNotifier req_notifier;
138 int (*resetfn)(struct VFIOPCIDevice *);
139 uint32_t vendor_id;
140 uint32_t device_id;
141 uint32_t sub_vendor_id;
142 uint32_t sub_device_id;
143 uint32_t features;
144#define VFIO_FEATURE_ENABLE_VGA_BIT 0
145#define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
146#define VFIO_FEATURE_ENABLE_REQ_BIT 1
147#define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
148#define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
149#define VFIO_FEATURE_ENABLE_IGD_OPREGION \
150 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
151 OnOffAuto display;
152 int32_t bootindex;
153 uint32_t igd_gms;
154 OffAutoPCIBAR msix_relo;
155 uint8_t pm_cap;
156 uint8_t nv_gpudirect_clique;
157 bool pci_aer;
158 bool req_enabled;
159 bool has_flr;
160 bool has_pm_reset;
161 bool rom_read_failed;
162 bool no_kvm_intx;
163 bool no_kvm_msi;
164 bool no_kvm_msix;
165 bool no_geforce_quirks;
166 bool no_kvm_ioeventfd;
167 bool no_vfio_ioeventfd;
168 VFIODisplay *dpy;
169} VFIOPCIDevice;
170
171uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
172void vfio_pci_write_config(PCIDevice *pdev,
173 uint32_t addr, uint32_t val, int len);
174
175uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
176void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
177
178bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev);
179void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
180void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
181void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
182void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
183void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
184void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
185void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
186int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
187void vfio_quirk_reset(VFIOPCIDevice *vdev);
188
189extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
190
191int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
192
193int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
194 struct vfio_region_info *info,
195 Error **errp);
196
197void vfio_display_reset(VFIOPCIDevice *vdev);
198int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
199void vfio_display_finalize(VFIOPCIDevice *vdev);
200
201#endif
202