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28#include "qemu/osdep.h"
29#include "qemu/units.h"
30#include "qapi/error.h"
31#include "cpu.h"
32#include "sysemu/sysemu.h"
33#include "hw/boards.h"
34#include "hw/loader.h"
35#include "elf.h"
36#include "exec/memory.h"
37#include "exec/address-spaces.h"
38#include "hw/char/serial.h"
39#include "net/net.h"
40#include "hw/sysbus.h"
41#include "hw/block/flash.h"
42#include "chardev/char.h"
43#include "sysemu/device_tree.h"
44#include "qemu/error-report.h"
45#include "qemu/option.h"
46#include "bootparam.h"
47#include "xtensa_memory.h"
48
49typedef struct XtfpgaFlashDesc {
50 hwaddr base;
51 size_t size;
52 size_t boot_base;
53 size_t sector_size;
54} XtfpgaFlashDesc;
55
56typedef struct XtfpgaBoardDesc {
57 const XtfpgaFlashDesc *flash;
58 size_t sram_size;
59 const hwaddr *io;
60} XtfpgaBoardDesc;
61
62typedef struct XtfpgaFpgaState {
63 MemoryRegion iomem;
64 uint32_t leds;
65 uint32_t switches;
66} XtfpgaFpgaState;
67
68static void xtfpga_fpga_reset(void *opaque)
69{
70 XtfpgaFpgaState *s = opaque;
71
72 s->leds = 0;
73 s->switches = 0;
74}
75
76static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
77 unsigned size)
78{
79 XtfpgaFpgaState *s = opaque;
80
81 switch (addr) {
82 case 0x0:
83 return 0x09272011;
84
85 case 0x4:
86 return 10000000;
87
88 case 0x8:
89 return s->leds;
90
91 case 0xc:
92 return s->switches;
93 }
94 return 0;
95}
96
97static void xtfpga_fpga_write(void *opaque, hwaddr addr,
98 uint64_t val, unsigned size)
99{
100 XtfpgaFpgaState *s = opaque;
101
102 switch (addr) {
103 case 0x8:
104 s->leds = val;
105 break;
106
107 case 0x10:
108 if (val == 0xdead) {
109 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
110 }
111 break;
112 }
113}
114
115static const MemoryRegionOps xtfpga_fpga_ops = {
116 .read = xtfpga_fpga_read,
117 .write = xtfpga_fpga_write,
118 .endianness = DEVICE_NATIVE_ENDIAN,
119};
120
121static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
122 hwaddr base)
123{
124 XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
125
126 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
127 "xtfpga.fpga", 0x10000);
128 memory_region_add_subregion(address_space, base, &s->iomem);
129 xtfpga_fpga_reset(s);
130 qemu_register_reset(xtfpga_fpga_reset, s);
131 return s;
132}
133
134static void xtfpga_net_init(MemoryRegion *address_space,
135 hwaddr base,
136 hwaddr descriptors,
137 hwaddr buffers,
138 qemu_irq irq, NICInfo *nd)
139{
140 DeviceState *dev;
141 SysBusDevice *s;
142 MemoryRegion *ram;
143
144 dev = qdev_create(NULL, "open_eth");
145 qdev_set_nic_properties(dev, nd);
146 qdev_init_nofail(dev);
147
148 s = SYS_BUS_DEVICE(dev);
149 sysbus_connect_irq(s, 0, irq);
150 memory_region_add_subregion(address_space, base,
151 sysbus_mmio_get_region(s, 0));
152 memory_region_add_subregion(address_space, descriptors,
153 sysbus_mmio_get_region(s, 1));
154
155 ram = g_malloc(sizeof(*ram));
156 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
157 &error_fatal);
158 vmstate_register_ram_global(ram);
159 memory_region_add_subregion(address_space, buffers, ram);
160}
161
162static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
163 const XtfpgaBoardDesc *board,
164 DriveInfo *dinfo, int be)
165{
166 SysBusDevice *s;
167 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
168
169 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
170 &error_abort);
171 qdev_prop_set_uint32(dev, "num-blocks",
172 board->flash->size / board->flash->sector_size);
173 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
174 qdev_prop_set_uint8(dev, "width", 2);
175 qdev_prop_set_bit(dev, "big-endian", be);
176 qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
177 qdev_init_nofail(dev);
178 s = SYS_BUS_DEVICE(dev);
179 memory_region_add_subregion(address_space, board->flash->base,
180 sysbus_mmio_get_region(s, 0));
181 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
182}
183
184static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
185{
186 XtensaCPU *cpu = opaque;
187
188 return cpu_get_phys_page_debug(CPU(cpu), addr);
189}
190
191static void xtfpga_reset(void *opaque)
192{
193 XtensaCPU *cpu = opaque;
194
195 cpu_reset(CPU(cpu));
196}
197
198static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
199 unsigned size)
200{
201 return 0;
202}
203
204static void xtfpga_io_write(void *opaque, hwaddr addr,
205 uint64_t val, unsigned size)
206{
207}
208
209static const MemoryRegionOps xtfpga_io_ops = {
210 .read = xtfpga_io_read,
211 .write = xtfpga_io_write,
212 .endianness = DEVICE_NATIVE_ENDIAN,
213};
214
215static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
216{
217#ifdef TARGET_WORDS_BIGENDIAN
218 int be = 1;
219#else
220 int be = 0;
221#endif
222 MemoryRegion *system_memory = get_system_memory();
223 XtensaCPU *cpu = NULL;
224 CPUXtensaState *env = NULL;
225 MemoryRegion *system_io;
226 DriveInfo *dinfo;
227 pflash_t *flash = NULL;
228 QemuOpts *machine_opts = qemu_get_machine_opts();
229 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
230 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
231 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
232 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
233 const unsigned system_io_size = 224 * MiB;
234 int n;
235
236 for (n = 0; n < smp_cpus; n++) {
237 cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
238 env = &cpu->env;
239
240 env->sregs[PRID] = n;
241 qemu_register_reset(xtfpga_reset, cpu);
242
243
244
245 cpu_reset(CPU(cpu));
246 }
247
248 if (env) {
249 XtensaMemory sysram = env->config->sysram;
250
251 sysram.location[0].size = machine->ram_size;
252 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
253 system_memory);
254 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
255 system_memory);
256 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
257 system_memory);
258 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
259 system_memory);
260 xtensa_create_memory_regions(&sysram, "xtensa.sysram",
261 system_memory);
262 }
263
264 system_io = g_malloc(sizeof(*system_io));
265 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
266 system_io_size);
267 memory_region_add_subregion(system_memory, board->io[0], system_io);
268 if (board->io[1]) {
269 MemoryRegion *io = g_malloc(sizeof(*io));
270
271 memory_region_init_alias(io, NULL, "xtfpga.io.cached",
272 system_io, 0, system_io_size);
273 memory_region_add_subregion(system_memory, board->io[1], io);
274 }
275 xtfpga_fpga_init(system_io, 0x0d020000);
276 if (nd_table[0].used) {
277 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
278 xtensa_get_extint(env, 1), nd_table);
279 }
280
281 serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
282 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
283
284 dinfo = drive_get(IF_PFLASH, 0, 0);
285 if (dinfo) {
286 flash = xtfpga_flash_init(system_io, board, dinfo, be);
287 }
288
289
290 if (kernel_filename) {
291 uint32_t entry_point = env->pc;
292 size_t bp_size = 3 * get_tag_size(0);
293 uint32_t tagptr = env->config->sysrom.location[0].addr +
294 board->sram_size;
295 uint32_t cur_tagptr;
296 BpMemInfo memory_location = {
297 .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
298 .start = tswap32(env->config->sysram.location[0].addr),
299 .end = tswap32(env->config->sysram.location[0].addr +
300 machine->ram_size),
301 };
302 uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
303 machine->ram_size : 0x08000000;
304 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
305
306 lowmem_end += env->config->sysram.location[0].addr;
307 cur_lowmem += env->config->sysram.location[0].addr;
308
309 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
310 system_memory);
311
312 if (kernel_cmdline) {
313 bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
314 }
315 if (dtb_filename) {
316 bp_size += get_tag_size(sizeof(uint32_t));
317 }
318 if (initrd_filename) {
319 bp_size += get_tag_size(sizeof(BpMemInfo));
320 }
321
322
323 tagptr = (tagptr - bp_size) & ~0xff;
324 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
325 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
326 sizeof(memory_location), &memory_location);
327
328 if (kernel_cmdline) {
329 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
330 strlen(kernel_cmdline) + 1, kernel_cmdline);
331 }
332#ifdef CONFIG_FDT
333 if (dtb_filename) {
334 int fdt_size;
335 void *fdt = load_device_tree(dtb_filename, &fdt_size);
336 uint32_t dtb_addr = tswap32(cur_lowmem);
337
338 if (!fdt) {
339 error_report("could not load DTB '%s'", dtb_filename);
340 exit(EXIT_FAILURE);
341 }
342
343 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
344 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
345 sizeof(dtb_addr), &dtb_addr);
346 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
347 }
348#else
349 if (dtb_filename) {
350 error_report("could not load DTB '%s': "
351 "FDT support is not configured in QEMU",
352 dtb_filename);
353 exit(EXIT_FAILURE);
354 }
355#endif
356 if (initrd_filename) {
357 BpMemInfo initrd_location = { 0 };
358 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
359 lowmem_end - cur_lowmem);
360
361 if (initrd_size < 0) {
362 initrd_size = load_image_targphys(initrd_filename,
363 cur_lowmem,
364 lowmem_end - cur_lowmem);
365 }
366 if (initrd_size < 0) {
367 error_report("could not load initrd '%s'", initrd_filename);
368 exit(EXIT_FAILURE);
369 }
370 initrd_location.start = tswap32(cur_lowmem);
371 initrd_location.end = tswap32(cur_lowmem + initrd_size);
372 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
373 sizeof(initrd_location), &initrd_location);
374 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
375 }
376 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
377 env->regs[2] = tagptr;
378
379 uint64_t elf_entry;
380 uint64_t elf_lowaddr;
381 int success = load_elf(kernel_filename, translate_phys_addr, cpu,
382 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
383 if (success > 0) {
384 entry_point = elf_entry;
385 } else {
386 hwaddr ep;
387 int is_linux;
388 success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
389 translate_phys_addr, cpu);
390 if (success > 0 && is_linux) {
391 entry_point = ep;
392 } else {
393 error_report("could not load kernel '%s'",
394 kernel_filename);
395 exit(EXIT_FAILURE);
396 }
397 }
398 if (entry_point != env->pc) {
399 uint8_t boot[] = {
400#ifdef TARGET_WORDS_BIGENDIAN
401 0x60, 0x00, 0x08,
402 0x00,
403 0x00, 0x00, 0x00, 0x00,
404 0x00, 0x00, 0x00, 0x00,
405
406 0x10, 0xff, 0xfe,
407 0x12, 0xff, 0xfe,
408 0x0a, 0x00, 0x00,
409#else
410 0x06, 0x02, 0x00,
411 0x00,
412 0x00, 0x00, 0x00, 0x00,
413 0x00, 0x00, 0x00, 0x00,
414
415 0x01, 0xfe, 0xff,
416 0x21, 0xfe, 0xff,
417 0xa0, 0x00, 0x00,
418#endif
419 };
420 uint32_t entry_pc = tswap32(entry_point);
421 uint32_t entry_a2 = tswap32(tagptr);
422
423 memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
424 memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
425 cpu_physical_memory_write(env->pc, boot, sizeof(boot));
426 }
427 } else {
428 if (flash) {
429 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
430 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
431 uint32_t size = env->config->sysrom.location[0].size;
432
433 if (board->flash->size - board->flash->boot_base < size) {
434 size = board->flash->size - board->flash->boot_base;
435 }
436
437 memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
438 flash_mr, board->flash->boot_base, size);
439 memory_region_add_subregion(system_memory,
440 env->config->sysrom.location[0].addr,
441 flash_io);
442 } else {
443 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
444 system_memory);
445 }
446 }
447}
448
449static const hwaddr xtfpga_mmu_io[2] = {
450 0xf0000000,
451};
452
453static const hwaddr xtfpga_nommu_io[2] = {
454 0x90000000,
455 0x70000000,
456};
457
458static const XtfpgaFlashDesc lx60_flash = {
459 .base = 0x08000000,
460 .size = 0x00400000,
461 .sector_size = 0x10000,
462};
463
464static void xtfpga_lx60_init(MachineState *machine)
465{
466 static const XtfpgaBoardDesc lx60_board = {
467 .flash = &lx60_flash,
468 .sram_size = 0x20000,
469 .io = xtfpga_mmu_io,
470 };
471 xtfpga_init(&lx60_board, machine);
472}
473
474static void xtfpga_lx60_nommu_init(MachineState *machine)
475{
476 static const XtfpgaBoardDesc lx60_board = {
477 .flash = &lx60_flash,
478 .sram_size = 0x20000,
479 .io = xtfpga_nommu_io,
480 };
481 xtfpga_init(&lx60_board, machine);
482}
483
484static const XtfpgaFlashDesc lx200_flash = {
485 .base = 0x08000000,
486 .size = 0x01000000,
487 .sector_size = 0x20000,
488};
489
490static void xtfpga_lx200_init(MachineState *machine)
491{
492 static const XtfpgaBoardDesc lx200_board = {
493 .flash = &lx200_flash,
494 .sram_size = 0x2000000,
495 .io = xtfpga_mmu_io,
496 };
497 xtfpga_init(&lx200_board, machine);
498}
499
500static void xtfpga_lx200_nommu_init(MachineState *machine)
501{
502 static const XtfpgaBoardDesc lx200_board = {
503 .flash = &lx200_flash,
504 .sram_size = 0x2000000,
505 .io = xtfpga_nommu_io,
506 };
507 xtfpga_init(&lx200_board, machine);
508}
509
510static const XtfpgaFlashDesc ml605_flash = {
511 .base = 0x08000000,
512 .size = 0x01000000,
513 .sector_size = 0x20000,
514};
515
516static void xtfpga_ml605_init(MachineState *machine)
517{
518 static const XtfpgaBoardDesc ml605_board = {
519 .flash = &ml605_flash,
520 .sram_size = 0x2000000,
521 .io = xtfpga_mmu_io,
522 };
523 xtfpga_init(&ml605_board, machine);
524}
525
526static void xtfpga_ml605_nommu_init(MachineState *machine)
527{
528 static const XtfpgaBoardDesc ml605_board = {
529 .flash = &ml605_flash,
530 .sram_size = 0x2000000,
531 .io = xtfpga_nommu_io,
532 };
533 xtfpga_init(&ml605_board, machine);
534}
535
536static const XtfpgaFlashDesc kc705_flash = {
537 .base = 0x00000000,
538 .size = 0x08000000,
539 .boot_base = 0x06000000,
540 .sector_size = 0x20000,
541};
542
543static void xtfpga_kc705_init(MachineState *machine)
544{
545 static const XtfpgaBoardDesc kc705_board = {
546 .flash = &kc705_flash,
547 .sram_size = 0x2000000,
548 .io = xtfpga_mmu_io,
549 };
550 xtfpga_init(&kc705_board, machine);
551}
552
553static void xtfpga_kc705_nommu_init(MachineState *machine)
554{
555 static const XtfpgaBoardDesc kc705_board = {
556 .flash = &kc705_flash,
557 .sram_size = 0x2000000,
558 .io = xtfpga_nommu_io,
559 };
560 xtfpga_init(&kc705_board, machine);
561}
562
563static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
564{
565 MachineClass *mc = MACHINE_CLASS(oc);
566
567 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
568 mc->init = xtfpga_lx60_init;
569 mc->max_cpus = 4;
570 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
571}
572
573static const TypeInfo xtfpga_lx60_type = {
574 .name = MACHINE_TYPE_NAME("lx60"),
575 .parent = TYPE_MACHINE,
576 .class_init = xtfpga_lx60_class_init,
577};
578
579static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
580{
581 MachineClass *mc = MACHINE_CLASS(oc);
582
583 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
584 mc->init = xtfpga_lx60_nommu_init;
585 mc->max_cpus = 4;
586 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
587}
588
589static const TypeInfo xtfpga_lx60_nommu_type = {
590 .name = MACHINE_TYPE_NAME("lx60-nommu"),
591 .parent = TYPE_MACHINE,
592 .class_init = xtfpga_lx60_nommu_class_init,
593};
594
595static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
596{
597 MachineClass *mc = MACHINE_CLASS(oc);
598
599 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
600 mc->init = xtfpga_lx200_init;
601 mc->max_cpus = 4;
602 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
603}
604
605static const TypeInfo xtfpga_lx200_type = {
606 .name = MACHINE_TYPE_NAME("lx200"),
607 .parent = TYPE_MACHINE,
608 .class_init = xtfpga_lx200_class_init,
609};
610
611static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
612{
613 MachineClass *mc = MACHINE_CLASS(oc);
614
615 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
616 mc->init = xtfpga_lx200_nommu_init;
617 mc->max_cpus = 4;
618 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
619}
620
621static const TypeInfo xtfpga_lx200_nommu_type = {
622 .name = MACHINE_TYPE_NAME("lx200-nommu"),
623 .parent = TYPE_MACHINE,
624 .class_init = xtfpga_lx200_nommu_class_init,
625};
626
627static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
628{
629 MachineClass *mc = MACHINE_CLASS(oc);
630
631 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
632 mc->init = xtfpga_ml605_init;
633 mc->max_cpus = 4;
634 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
635}
636
637static const TypeInfo xtfpga_ml605_type = {
638 .name = MACHINE_TYPE_NAME("ml605"),
639 .parent = TYPE_MACHINE,
640 .class_init = xtfpga_ml605_class_init,
641};
642
643static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
644{
645 MachineClass *mc = MACHINE_CLASS(oc);
646
647 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
648 mc->init = xtfpga_ml605_nommu_init;
649 mc->max_cpus = 4;
650 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
651}
652
653static const TypeInfo xtfpga_ml605_nommu_type = {
654 .name = MACHINE_TYPE_NAME("ml605-nommu"),
655 .parent = TYPE_MACHINE,
656 .class_init = xtfpga_ml605_nommu_class_init,
657};
658
659static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
660{
661 MachineClass *mc = MACHINE_CLASS(oc);
662
663 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
664 mc->init = xtfpga_kc705_init;
665 mc->max_cpus = 4;
666 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
667}
668
669static const TypeInfo xtfpga_kc705_type = {
670 .name = MACHINE_TYPE_NAME("kc705"),
671 .parent = TYPE_MACHINE,
672 .class_init = xtfpga_kc705_class_init,
673};
674
675static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
676{
677 MachineClass *mc = MACHINE_CLASS(oc);
678
679 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
680 mc->init = xtfpga_kc705_nommu_init;
681 mc->max_cpus = 4;
682 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
683}
684
685static const TypeInfo xtfpga_kc705_nommu_type = {
686 .name = MACHINE_TYPE_NAME("kc705-nommu"),
687 .parent = TYPE_MACHINE,
688 .class_init = xtfpga_kc705_nommu_class_init,
689};
690
691static void xtfpga_machines_init(void)
692{
693 type_register_static(&xtfpga_lx60_type);
694 type_register_static(&xtfpga_lx200_type);
695 type_register_static(&xtfpga_ml605_type);
696 type_register_static(&xtfpga_kc705_type);
697 type_register_static(&xtfpga_lx60_nommu_type);
698 type_register_static(&xtfpga_lx200_nommu_type);
699 type_register_static(&xtfpga_ml605_nommu_type);
700 type_register_static(&xtfpga_kc705_nommu_type);
701}
702
703type_init(xtfpga_machines_init)
704
