1/* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 * 23 */ 24 25#ifndef EXYNOS4210_H 26#define EXYNOS4210_H 27 28#include "qemu-common.h" 29#include "exec/memory.h" 30#include "target/arm/cpu-qom.h" 31 32#define EXYNOS4210_NCPUS 2 33 34#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 35#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 36#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ 37 38#define EXYNOS4210_IROM_BASE_ADDR 0x00000000 39#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ 40#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 41#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ 42 43#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 44#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ 45 46/* Secondary CPU startup code is in IROM memory */ 47#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR 48#define EXYNOS4210_SMP_BOOT_SIZE 0x1000 49#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR 50/* Secondary CPU polling address to get loader start from */ 51#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 52 53#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 54#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 55 56/* 57 * exynos4210 IRQ subsystem stub definitions. 58 */ 59#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ 60 61#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 62#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 63#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ 64 (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) 65#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ 66 (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) 67 68#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) 69#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 70#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 71 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 72 73/* IRQs number for external and internal GIC */ 74#define EXYNOS4210_EXT_GIC_NIRQ (160-32) 75#define EXYNOS4210_INT_GIC_NIRQ 64 76 77#define EXYNOS4210_I2C_NUMBER 9 78 79typedef struct Exynos4210Irq { 80 qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 81 qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; 82 qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; 83 qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; 84 qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 85} Exynos4210Irq; 86 87typedef struct Exynos4210State { 88 ARMCPU *cpu[EXYNOS4210_NCPUS]; 89 Exynos4210Irq irqs; 90 qemu_irq *irq_table; 91 92 MemoryRegion chipid_mem; 93 MemoryRegion iram_mem; 94 MemoryRegion irom_mem; 95 MemoryRegion irom_alias_mem; 96 MemoryRegion boot_secondary; 97 MemoryRegion bootreg_mem; 98 I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; 99} Exynos4210State; 100 101void exynos4210_write_secondary(ARMCPU *cpu, 102 const struct arm_boot_info *info); 103 104Exynos4210State *exynos4210_init(MemoryRegion *system_mem); 105 106/* Initialize exynos4210 IRQ subsystem stub */ 107qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); 108 109/* Initialize board IRQs. 110 * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ 111void exynos4210_init_board_irqs(Exynos4210Irq *s); 112 113/* Get IRQ number from exynos4210 IRQ subsystem stub. 114 * To identify IRQ source use internal combiner group and bit number 115 * grp - group number 116 * bit - bit number inside group */ 117uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); 118 119/* 120 * Get Combiner input GPIO into irqs structure 121 */ 122void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, 123 int ext); 124 125/* 126 * exynos4210 UART 127 */ 128DeviceState *exynos4210_uart_create(hwaddr addr, 129 int fifo_size, 130 int channel, 131 Chardev *chr, 132 qemu_irq irq); 133 134#endif /* EXYNOS4210_H */ 135