LXR qemu/include/hw/net/cadence

   1/*
   2 * QEMU Cadence GEM emulation
   3 *
   4 * Copyright (c) 2011 Xilinx, Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef CADENCE_GEM_H
  26
  27#define TYPE_CADENCE_GEM "cadence_gem"
  28#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
  29
  30#include "net/net.h"
  31#include "hw/sysbus.h"
  32
  33#define CADENCE_GEM_MAXREG        (0x00000800 / 4) /* Last valid GEM address */
  34
  35#define MAX_PRIORITY_QUEUES             8
  36#define MAX_TYPE1_SCREENERS             16
  37#define MAX_TYPE2_SCREENERS             16
  38
  39typedef struct CadenceGEMState {
  40    /*< private >*/
  41    SysBusDevice parent_obj;
  42
  43    /*< public >*/
  44    MemoryRegion iomem;
  45    NICState *nic;
  46    NICConf conf;
  47    qemu_irq irq[MAX_PRIORITY_QUEUES];
  48
  49    /* Static properties */
  50    uint8_t num_priority_queues;
  51    uint8_t num_type1_screeners;
  52    uint8_t num_type2_screeners;
  53    uint32_t revision;
  54
  55    /* GEM registers backing store */
  56    uint32_t regs[CADENCE_GEM_MAXREG];
  57    /* Mask of register bits which are write only */
  58    uint32_t regs_wo[CADENCE_GEM_MAXREG];
  59    /* Mask of register bits which are read only */
  60    uint32_t regs_ro[CADENCE_GEM_MAXREG];
  61    /* Mask of register bits which are clear on read */
  62    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
  63    /* Mask of register bits which are write 1 to clear */
  64    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
  65
  66    /* PHY registers backing store */
  67    uint16_t phy_regs[32];
  68
  69    uint8_t phy_loop; /* Are we in phy loopback? */
  70
  71    /* The current DMA descriptor pointers */
  72    uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
  73    uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
  74
  75    uint8_t can_rx_state; /* Debug only */
  76
  77    unsigned rx_desc[MAX_PRIORITY_QUEUES][2];
  78
  79    bool sar_active[4];
  80} CadenceGEMState;
  81
  82#define CADENCE_GEM_H
  83#endif
  84