1/* 2 * S/390 channel I/O instructions 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10*/ 11 12#ifndef S390X_IOINST_H 13#define S390X_IOINST_H 14 15/* 16 * Channel I/O related definitions, as defined in the Principles 17 * Of Operation (and taken from the Linux implementation). 18 */ 19 20/* subchannel status word (command mode only) */ 21typedef struct SCSW { 22 uint16_t flags; 23 uint16_t ctrl; 24 uint32_t cpa; 25 uint8_t dstat; 26 uint8_t cstat; 27 uint16_t count; 28} QEMU_PACKED SCSW; 29 30#define SCSW_FLAGS_MASK_KEY 0xf000 31#define SCSW_FLAGS_MASK_SCTL 0x0800 32#define SCSW_FLAGS_MASK_ESWF 0x0400 33#define SCSW_FLAGS_MASK_CC 0x0300 34#define SCSW_FLAGS_MASK_FMT 0x0080 35#define SCSW_FLAGS_MASK_PFCH 0x0040 36#define SCSW_FLAGS_MASK_ISIC 0x0020 37#define SCSW_FLAGS_MASK_ALCC 0x0010 38#define SCSW_FLAGS_MASK_SSI 0x0008 39#define SCSW_FLAGS_MASK_ZCC 0x0004 40#define SCSW_FLAGS_MASK_ECTL 0x0002 41#define SCSW_FLAGS_MASK_PNO 0x0001 42 43#define SCSW_CTRL_MASK_FCTL 0x7000 44#define SCSW_CTRL_MASK_ACTL 0x0fe0 45#define SCSW_CTRL_MASK_STCTL 0x001f 46 47#define SCSW_FCTL_CLEAR_FUNC 0x1000 48#define SCSW_FCTL_HALT_FUNC 0x2000 49#define SCSW_FCTL_START_FUNC 0x4000 50 51#define SCSW_ACTL_SUSP 0x0020 52#define SCSW_ACTL_DEVICE_ACTIVE 0x0040 53#define SCSW_ACTL_SUBCH_ACTIVE 0x0080 54#define SCSW_ACTL_CLEAR_PEND 0x0100 55#define SCSW_ACTL_HALT_PEND 0x0200 56#define SCSW_ACTL_START_PEND 0x0400 57#define SCSW_ACTL_RESUME_PEND 0x0800 58 59#define SCSW_STCTL_STATUS_PEND 0x0001 60#define SCSW_STCTL_SECONDARY 0x0002 61#define SCSW_STCTL_PRIMARY 0x0004 62#define SCSW_STCTL_INTERMEDIATE 0x0008 63#define SCSW_STCTL_ALERT 0x0010 64 65#define SCSW_DSTAT_ATTENTION 0x80 66#define SCSW_DSTAT_STAT_MOD 0x40 67#define SCSW_DSTAT_CU_END 0x20 68#define SCSW_DSTAT_BUSY 0x10 69#define SCSW_DSTAT_CHANNEL_END 0x08 70#define SCSW_DSTAT_DEVICE_END 0x04 71#define SCSW_DSTAT_UNIT_CHECK 0x02 72#define SCSW_DSTAT_UNIT_EXCEP 0x01 73 74#define SCSW_CSTAT_PCI 0x80 75#define SCSW_CSTAT_INCORR_LEN 0x40 76#define SCSW_CSTAT_PROG_CHECK 0x20 77#define SCSW_CSTAT_PROT_CHECK 0x10 78#define SCSW_CSTAT_DATA_CHECK 0x08 79#define SCSW_CSTAT_CHN_CTRL_CHK 0x04 80#define SCSW_CSTAT_INTF_CTRL_CHK 0x02 81#define SCSW_CSTAT_CHAIN_CHECK 0x01 82 83/* path management control word */ 84typedef struct PMCW { 85 uint32_t intparm; 86 uint16_t flags; 87 uint16_t devno; 88 uint8_t lpm; 89 uint8_t pnom; 90 uint8_t lpum; 91 uint8_t pim; 92 uint16_t mbi; 93 uint8_t pom; 94 uint8_t pam; 95 uint8_t chpid[8]; 96 uint32_t chars; 97} QEMU_PACKED PMCW; 98 99#define PMCW_FLAGS_MASK_QF 0x8000 100#define PMCW_FLAGS_MASK_W 0x4000 101#define PMCW_FLAGS_MASK_ISC 0x3800 102#define PMCW_FLAGS_MASK_ENA 0x0080 103#define PMCW_FLAGS_MASK_LM 0x0060 104#define PMCW_FLAGS_MASK_MME 0x0018 105#define PMCW_FLAGS_MASK_MP 0x0004 106#define PMCW_FLAGS_MASK_TF 0x0002 107#define PMCW_FLAGS_MASK_DNV 0x0001 108#define PMCW_FLAGS_MASK_INVALID 0x0700 109 110#define PMCW_CHARS_MASK_ST 0x00e00000 111#define PMCW_CHARS_MASK_MBFC 0x00000004 112#define PMCW_CHARS_MASK_XMWME 0x00000002 113#define PMCW_CHARS_MASK_CSENSE 0x00000001 114#define PMCW_CHARS_MASK_INVALID 0xff1ffff8 115 116/* subchannel information block */ 117typedef struct SCHIB { 118 PMCW pmcw; 119 SCSW scsw; 120 uint64_t mba; 121 uint8_t mda[4]; 122} QEMU_PACKED SCHIB; 123 124/* interruption response block */ 125typedef struct IRB { 126 SCSW scsw; 127 uint32_t esw[5]; 128 uint32_t ecw[8]; 129 uint32_t emw[8]; 130} QEMU_PACKED IRB; 131 132/* operation request block */ 133typedef struct ORB { 134 uint32_t intparm; 135 uint16_t ctrl0; 136 uint8_t lpm; 137 uint8_t ctrl1; 138 uint32_t cpa; 139} QEMU_PACKED ORB; 140 141#define ORB_CTRL0_MASK_KEY 0xf000 142#define ORB_CTRL0_MASK_SPND 0x0800 143#define ORB_CTRL0_MASK_STR 0x0400 144#define ORB_CTRL0_MASK_MOD 0x0200 145#define ORB_CTRL0_MASK_SYNC 0x0100 146#define ORB_CTRL0_MASK_FMT 0x0080 147#define ORB_CTRL0_MASK_PFCH 0x0040 148#define ORB_CTRL0_MASK_ISIC 0x0020 149#define ORB_CTRL0_MASK_ALCC 0x0010 150#define ORB_CTRL0_MASK_SSIC 0x0008 151#define ORB_CTRL0_MASK_C64 0x0002 152#define ORB_CTRL0_MASK_I2K 0x0001 153#define ORB_CTRL0_MASK_INVALID 0x0004 154 155#define ORB_CTRL1_MASK_ILS 0x80 156#define ORB_CTRL1_MASK_MIDAW 0x40 157#define ORB_CTRL1_MASK_ORBX 0x01 158#define ORB_CTRL1_MASK_INVALID 0x3e 159 160/* channel command word (type 0) */ 161typedef struct CCW0 { 162 uint8_t cmd_code; 163 uint8_t cda0; 164 uint16_t cda1; 165 uint8_t flags; 166 uint8_t reserved; 167 uint16_t count; 168} QEMU_PACKED CCW0; 169 170/* channel command word (type 1) */ 171typedef struct CCW1 { 172 uint8_t cmd_code; 173 uint8_t flags; 174 uint16_t count; 175 uint32_t cda; 176} QEMU_PACKED CCW1; 177 178#define CCW_FLAG_DC 0x80 179#define CCW_FLAG_CC 0x40 180#define CCW_FLAG_SLI 0x20 181#define CCW_FLAG_SKIP 0x10 182#define CCW_FLAG_PCI 0x08 183#define CCW_FLAG_IDA 0x04 184#define CCW_FLAG_SUSPEND 0x02 185#define CCW_FLAG_MIDA 0x01 186 187#define CCW_CMD_NOOP 0x03 188#define CCW_CMD_BASIC_SENSE 0x04 189#define CCW_CMD_TIC 0x08 190#define CCW_CMD_SENSE_ID 0xe4 191 192typedef struct CRW { 193 uint16_t flags; 194 uint16_t rsid; 195} QEMU_PACKED CRW; 196 197#define CRW_FLAGS_MASK_S 0x4000 198#define CRW_FLAGS_MASK_R 0x2000 199#define CRW_FLAGS_MASK_C 0x1000 200#define CRW_FLAGS_MASK_RSC 0x0f00 201#define CRW_FLAGS_MASK_A 0x0080 202#define CRW_FLAGS_MASK_ERC 0x003f 203 204#define CRW_ERC_EVENT 0x00 /* event information pending */ 205#define CRW_ERC_AVAIL 0x01 /* available */ 206#define CRW_ERC_INIT 0x02 /* initialized */ 207#define CRW_ERC_TERROR 0x03 /* temporary error */ 208#define CRW_ERC_IPI 0x04 /* installed parm initialized */ 209#define CRW_ERC_TERM 0x05 /* terminal */ 210#define CRW_ERC_PERRN 0x06 /* perm. error, facility not init */ 211#define CRW_ERC_PERRI 0x07 /* perm. error, facility init */ 212#define CRW_ERC_PMOD 0x08 /* installed parameters modified */ 213#define CRW_ERC_IPR 0x0A /* installed parameters restored */ 214 215#define CRW_RSC_SUBCH 0x3 216#define CRW_RSC_CHP 0x4 217#define CRW_RSC_CSS 0xb 218 219/* I/O interruption code */ 220typedef struct IOIntCode { 221 uint32_t subsys_id; 222 uint32_t intparm; 223 uint32_t interrupt_id; 224} QEMU_PACKED IOIntCode; 225 226/* schid disintegration */ 227#define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16) 228#define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19) 229#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24) 230#define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17) 231#define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff) 232 233#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 27) 234#define ISC_TO_ISC_BITS(_isc) ((0x80 >> _isc) << 24) 235 236#define IO_INT_WORD_AI 0x80000000 237 238int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid, 239 int *schid); 240 241#endif 242