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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25
26#if defined(TARGET_AARCH64)
27
28# define TARGET_LONG_BITS 64
29#else
30# define TARGET_LONG_BITS 32
31#endif
32
33
34#define TCG_GUEST_DEFAULT_MO (0)
35
36#define CPUArchState struct CPUARMState
37
38#include "qemu-common.h"
39#include "cpu-qom.h"
40#include "exec/cpu-defs.h"
41
42#define EXCP_UDEF 1
43#define EXCP_SWI 2
44#define EXCP_PREFETCH_ABORT 3
45#define EXCP_DATA_ABORT 4
46#define EXCP_IRQ 5
47#define EXCP_FIQ 6
48#define EXCP_BKPT 7
49#define EXCP_EXCEPTION_EXIT 8
50#define EXCP_KERNEL_TRAP 9
51#define EXCP_HVC 11
52#define EXCP_HYP_TRAP 12
53#define EXCP_SMC 13
54#define EXCP_VIRQ 14
55#define EXCP_VFIQ 15
56#define EXCP_SEMIHOST 16
57#define EXCP_NOCP 17
58#define EXCP_INVSTATE 18
59
60
61#define ARMV7M_EXCP_RESET 1
62#define ARMV7M_EXCP_NMI 2
63#define ARMV7M_EXCP_HARD 3
64#define ARMV7M_EXCP_MEM 4
65#define ARMV7M_EXCP_BUS 5
66#define ARMV7M_EXCP_USAGE 6
67#define ARMV7M_EXCP_SECURE 7
68#define ARMV7M_EXCP_SVC 11
69#define ARMV7M_EXCP_DEBUG 12
70#define ARMV7M_EXCP_PENDSV 14
71#define ARMV7M_EXCP_SYSTICK 15
72
73
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80
81
82enum {
83 M_REG_NS = 0,
84 M_REG_S = 1,
85 M_REG_NUM_BANKS = 2,
86};
87
88
89#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
90#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
91#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
92
93
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97
98
99#ifdef HOST_WORDS_BIGENDIAN
100#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
101#define offsetofhigh32(S, M) offsetof(S, M)
102#else
103#define offsetoflow32(S, M) offsetof(S, M)
104#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
105#endif
106
107
108#define ARM_CPU_IRQ 0
109#define ARM_CPU_FIQ 1
110#define ARM_CPU_VIRQ 2
111#define ARM_CPU_VFIQ 3
112
113#define NB_MMU_MODES 8
114
115
116
117
118#define TARGET_INSN_START_EXTRA_WORDS 2
119
120
121
122
123
124
125#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
126#define ARM_INSN_START_WORD2_SHIFT 14
127
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141
142
143typedef struct DynamicGDBXMLInfo {
144 char *desc;
145 int num_cpregs;
146 uint32_t *cpregs_keys;
147} DynamicGDBXMLInfo;
148
149
150typedef struct ARMGenericTimer {
151 uint64_t cval;
152 uint64_t ctl;
153} ARMGenericTimer;
154
155#define GTIMER_PHYS 0
156#define GTIMER_VIRT 1
157#define GTIMER_HYP 2
158#define GTIMER_SEC 3
159#define NUM_GTIMERS 4
160
161typedef struct {
162 uint64_t raw_tcr;
163 uint32_t mask;
164 uint32_t base_mask;
165} TCR;
166
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192
193#ifdef TARGET_AARCH64
194# define ARM_MAX_VQ 16
195#else
196# define ARM_MAX_VQ 1
197#endif
198
199typedef struct ARMVectorReg {
200 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
201} ARMVectorReg;
202
203
204#ifdef TARGET_AARCH64
205typedef struct ARMPredicateReg {
206 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
207} ARMPredicateReg;
208#endif
209
210
211typedef struct CPUARMState {
212
213 uint32_t regs[16];
214
215
216
217
218
219
220 uint64_t xregs[32];
221 uint64_t pc;
222
223
224
225
226
227
228
229
230
231
232
233 uint32_t pstate;
234 uint32_t aarch64;
235
236
237
238
239 uint32_t uncached_cpsr;
240 uint32_t spsr;
241
242
243 uint64_t banked_spsr[8];
244 uint32_t banked_r13[8];
245 uint32_t banked_r14[8];
246
247
248 uint32_t usr_regs[5];
249 uint32_t fiq_regs[5];
250
251
252 uint32_t CF;
253 uint32_t VF;
254 uint32_t NF;
255 uint32_t ZF;
256 uint32_t QF;
257 uint32_t GE;
258 uint32_t thumb;
259 uint32_t condexec_bits;
260 uint64_t daif;
261
262 uint64_t elr_el[4];
263 uint64_t sp_el[4];
264
265
266 struct {
267 uint32_t c0_cpuid;
268 union {
269 struct {
270 uint64_t _unused_csselr0;
271 uint64_t csselr_ns;
272 uint64_t _unused_csselr1;
273 uint64_t csselr_s;
274 };
275 uint64_t csselr_el[4];
276 };
277 union {
278 struct {
279 uint64_t _unused_sctlr;
280 uint64_t sctlr_ns;
281 uint64_t hsctlr;
282 uint64_t sctlr_s;
283 };
284 uint64_t sctlr_el[4];
285 };
286 uint64_t cpacr_el1;
287 uint64_t cptr_el[4];
288 uint32_t c1_xscaleauxcr;
289 uint64_t sder;
290 uint32_t nsacr;
291 union {
292 struct {
293 uint64_t _unused_ttbr0_0;
294 uint64_t ttbr0_ns;
295 uint64_t _unused_ttbr0_1;
296 uint64_t ttbr0_s;
297 };
298 uint64_t ttbr0_el[4];
299 };
300 union {
301 struct {
302 uint64_t _unused_ttbr1_0;
303 uint64_t ttbr1_ns;
304 uint64_t _unused_ttbr1_1;
305 uint64_t ttbr1_s;
306 };
307 uint64_t ttbr1_el[4];
308 };
309 uint64_t vttbr_el2;
310
311 TCR tcr_el[4];
312 TCR vtcr_el2;
313 uint32_t c2_data;
314 uint32_t c2_insn;
315 union {
316
317
318 struct {
319 uint64_t dacr_ns;
320 uint64_t dacr_s;
321 };
322 struct {
323 uint64_t dacr32_el2;
324 };
325 };
326 uint32_t pmsav5_data_ap;
327 uint32_t pmsav5_insn_ap;
328 uint64_t hcr_el2;
329 uint64_t scr_el3;
330 union {
331 struct {
332 uint64_t ifsr_ns;
333 uint64_t ifsr_s;
334 };
335 struct {
336 uint64_t ifsr32_el2;
337 };
338 };
339 union {
340 struct {
341 uint64_t _unused_dfsr;
342 uint64_t dfsr_ns;
343 uint64_t hsr;
344 uint64_t dfsr_s;
345 };
346 uint64_t esr_el[4];
347 };
348 uint32_t c6_region[8];
349 union {
350 struct {
351 uint64_t _unused_far0;
352#ifdef HOST_WORDS_BIGENDIAN
353 uint32_t ifar_ns;
354 uint32_t dfar_ns;
355 uint32_t ifar_s;
356 uint32_t dfar_s;
357#else
358 uint32_t dfar_ns;
359 uint32_t ifar_ns;
360 uint32_t dfar_s;
361 uint32_t ifar_s;
362#endif
363 uint64_t _unused_far3;
364 };
365 uint64_t far_el[4];
366 };
367 uint64_t hpfar_el2;
368 uint64_t hstr_el2;
369 union {
370 struct {
371 uint64_t _unused_par_0;
372 uint64_t par_ns;
373 uint64_t _unused_par_1;
374 uint64_t par_s;
375 };
376 uint64_t par_el[4];
377 };
378
379 uint32_t c9_insn;
380 uint32_t c9_data;
381 uint64_t c9_pmcr;
382 uint64_t c9_pmcnten;
383 uint64_t c9_pmovsr;
384 uint64_t c9_pmuserenr;
385 uint64_t c9_pmselr;
386 uint64_t c9_pminten;
387 union {
388 struct {
389#ifdef HOST_WORDS_BIGENDIAN
390 uint64_t _unused_mair_0;
391 uint32_t mair1_ns;
392 uint32_t mair0_ns;
393 uint64_t _unused_mair_1;
394 uint32_t mair1_s;
395 uint32_t mair0_s;
396#else
397 uint64_t _unused_mair_0;
398 uint32_t mair0_ns;
399 uint32_t mair1_ns;
400 uint64_t _unused_mair_1;
401 uint32_t mair0_s;
402 uint32_t mair1_s;
403#endif
404 };
405 uint64_t mair_el[4];
406 };
407 union {
408 struct {
409 uint64_t _unused_vbar;
410 uint64_t vbar_ns;
411 uint64_t hvbar;
412 uint64_t vbar_s;
413 };
414 uint64_t vbar_el[4];
415 };
416 uint32_t mvbar;
417 struct {
418 uint32_t fcseidr_ns;
419 uint32_t fcseidr_s;
420 };
421 union {
422 struct {
423 uint64_t _unused_contextidr_0;
424 uint64_t contextidr_ns;
425 uint64_t _unused_contextidr_1;
426 uint64_t contextidr_s;
427 };
428 uint64_t contextidr_el[4];
429 };
430 union {
431 struct {
432 uint64_t tpidrurw_ns;
433 uint64_t tpidrprw_ns;
434 uint64_t htpidr;
435 uint64_t _tpidr_el3;
436 };
437 uint64_t tpidr_el[4];
438 };
439
440 uint64_t tpidrurw_s;
441 uint64_t tpidrprw_s;
442 uint64_t tpidruro_s;
443
444 union {
445 uint64_t tpidruro_ns;
446 uint64_t tpidrro_el[1];
447 };
448 uint64_t c14_cntfrq;
449 uint64_t c14_cntkctl;
450 uint32_t cnthctl_el2;
451 uint64_t cntvoff_el2;
452 ARMGenericTimer c14_timer[NUM_GTIMERS];
453 uint32_t c15_cpar;
454 uint32_t c15_ticonfig;
455 uint32_t c15_i_max;
456 uint32_t c15_i_min;
457 uint32_t c15_threadid;
458 uint32_t c15_config_base_address;
459 uint32_t c15_diagnostic;
460 uint32_t c15_power_diagnostic;
461 uint32_t c15_power_control;
462 uint64_t dbgbvr[16];
463 uint64_t dbgbcr[16];
464 uint64_t dbgwvr[16];
465 uint64_t dbgwcr[16];
466 uint64_t mdscr_el1;
467 uint64_t oslsr_el1;
468 uint64_t mdcr_el2;
469 uint64_t mdcr_el3;
470
471
472
473 uint64_t c15_ccnt;
474 uint64_t pmccfiltr_el0;
475 uint64_t vpidr_el2;
476 uint64_t vmpidr_el2;
477 } cp15;
478
479 struct {
480
481
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486
487
488
489
490
491 uint32_t other_sp;
492 uint32_t other_ss_msp;
493 uint32_t other_ss_psp;
494 uint32_t vecbase[M_REG_NUM_BANKS];
495 uint32_t basepri[M_REG_NUM_BANKS];
496 uint32_t control[M_REG_NUM_BANKS];
497 uint32_t ccr[M_REG_NUM_BANKS];
498 uint32_t cfsr[M_REG_NUM_BANKS];
499 uint32_t hfsr;
500 uint32_t dfsr;
501 uint32_t sfsr;
502 uint32_t mmfar[M_REG_NUM_BANKS];
503 uint32_t bfar;
504 uint32_t sfar;
505 unsigned mpu_ctrl[M_REG_NUM_BANKS];
506 int exception;
507 uint32_t primask[M_REG_NUM_BANKS];
508 uint32_t faultmask[M_REG_NUM_BANKS];
509 uint32_t aircr;
510 uint32_t secure;
511 uint32_t csselr[M_REG_NUM_BANKS];
512 uint32_t scr[M_REG_NUM_BANKS];
513 uint32_t msplim[M_REG_NUM_BANKS];
514 uint32_t psplim[M_REG_NUM_BANKS];
515 } v7m;
516
517
518
519
520
521
522
523 struct {
524 uint32_t syndrome;
525 uint32_t fsr;
526 uint64_t vaddress;
527 uint32_t target_el;
528
529
530
531 } exception;
532
533
534 uint32_t teecr;
535 uint32_t teehbr;
536
537
538 struct {
539 ARMVectorReg zregs[32];
540
541#ifdef TARGET_AARCH64
542
543#define FFR_PRED_NUM 16
544 ARMPredicateReg pregs[17];
545
546 ARMPredicateReg preg_tmp;
547#endif
548
549 uint32_t xregs[16];
550
551 int vec_len;
552 int vec_stride;
553
554
555 uint32_t scratch[8];
556
557
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577
578 float_status fp_status;
579 float_status fp_status_f16;
580 float_status standard_fp_status;
581
582
583 uint64_t zcr_el[4];
584 } vfp;
585 uint64_t exclusive_addr;
586 uint64_t exclusive_val;
587 uint64_t exclusive_high;
588
589
590 struct {
591 uint64_t regs[16];
592 uint64_t val;
593
594 uint32_t cregs[16];
595 } iwmmxt;
596
597#if defined(CONFIG_USER_ONLY)
598
599 int eabi;
600#endif
601
602 struct CPUBreakpoint *cpu_breakpoint[16];
603 struct CPUWatchpoint *cpu_watchpoint[16];
604
605
606 struct {} end_reset_fields;
607
608 CPU_COMMON
609
610
611
612
613 uint64_t features;
614
615
616 struct {
617 uint32_t *drbar;
618 uint32_t *drsr;
619 uint32_t *dracr;
620 uint32_t rnr[M_REG_NUM_BANKS];
621 } pmsav7;
622
623
624 struct {
625
626
627
628
629
630 uint32_t *rbar[M_REG_NUM_BANKS];
631 uint32_t *rlar[M_REG_NUM_BANKS];
632 uint32_t mair0[M_REG_NUM_BANKS];
633 uint32_t mair1[M_REG_NUM_BANKS];
634 } pmsav8;
635
636
637 struct {
638 uint32_t *rbar;
639 uint32_t *rlar;
640 uint32_t rnr;
641 uint32_t ctrl;
642 } sau;
643
644 void *nvic;
645 const struct arm_boot_info *boot_info;
646
647 void *gicv3state;
648} CPUARMState;
649
650
651
652
653
654
655typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
656typedef struct ARMELChangeHook ARMELChangeHook;
657struct ARMELChangeHook {
658 ARMELChangeHookFn *hook;
659 void *opaque;
660 QLIST_ENTRY(ARMELChangeHook) node;
661};
662
663
664
665typedef enum ARMPSCIState {
666 PSCI_ON = 0,
667 PSCI_OFF = 1,
668 PSCI_ON_PENDING = 2
669} ARMPSCIState;
670
671
672
673
674
675
676
677struct ARMCPU {
678
679 CPUState parent_obj;
680
681
682 CPUARMState env;
683
684
685 GHashTable *cp_regs;
686
687
688
689
690
691
692
693 uint64_t *cpreg_indexes;
694
695 uint64_t *cpreg_values;
696
697 int32_t cpreg_array_len;
698
699
700
701
702 uint64_t *cpreg_vmstate_indexes;
703 uint64_t *cpreg_vmstate_values;
704 int32_t cpreg_vmstate_array_len;
705
706 DynamicGDBXMLInfo dyn_xml;
707
708
709 QEMUTimer *gt_timer[NUM_GTIMERS];
710
711 qemu_irq gt_timer_outputs[NUM_GTIMERS];
712
713 qemu_irq gicv3_maintenance_interrupt;
714
715 qemu_irq pmu_interrupt;
716
717
718 MemoryRegion *secure_memory;
719
720
721 Object *idau;
722
723
724 const char *dtb_compatible;
725
726
727
728
729
730 uint32_t psci_version;
731
732
733 bool start_powered_off;
734
735
736 ARMPSCIState power_state;
737
738
739 bool has_el2;
740
741 bool has_el3;
742
743 bool has_pmu;
744
745
746 bool has_mpu;
747
748 uint32_t pmsav7_dregion;
749
750 uint32_t sau_sregion;
751
752
753
754
755 uint32_t psci_conduit;
756
757
758 uint32_t init_svtor;
759
760
761
762
763 uint32_t kvm_target;
764
765
766 uint32_t kvm_init_features[7];
767
768
769 bool mp_is_up;
770
771
772
773
774 bool host_cpu_probe_failed;
775
776
777
778
779 int32_t core_count;
780
781
782
783
784
785
786
787
788
789
790
791 uint32_t midr;
792 uint32_t revidr;
793 uint32_t reset_fpsid;
794 uint32_t mvfr0;
795 uint32_t mvfr1;
796 uint32_t mvfr2;
797 uint32_t ctr;
798 uint32_t reset_sctlr;
799 uint32_t id_pfr0;
800 uint32_t id_pfr1;
801 uint32_t id_dfr0;
802 uint32_t pmceid0;
803 uint32_t pmceid1;
804 uint32_t id_afr0;
805 uint32_t id_mmfr0;
806 uint32_t id_mmfr1;
807 uint32_t id_mmfr2;
808 uint32_t id_mmfr3;
809 uint32_t id_mmfr4;
810 uint32_t id_isar0;
811 uint32_t id_isar1;
812 uint32_t id_isar2;
813 uint32_t id_isar3;
814 uint32_t id_isar4;
815 uint32_t id_isar5;
816 uint32_t id_isar6;
817 uint64_t id_aa64pfr0;
818 uint64_t id_aa64pfr1;
819 uint64_t id_aa64dfr0;
820 uint64_t id_aa64dfr1;
821 uint64_t id_aa64afr0;
822 uint64_t id_aa64afr1;
823 uint64_t id_aa64isar0;
824 uint64_t id_aa64isar1;
825 uint64_t id_aa64mmfr0;
826 uint64_t id_aa64mmfr1;
827 uint32_t dbgdidr;
828 uint32_t clidr;
829 uint64_t mp_affinity;
830
831
832
833 uint32_t ccsidr[16];
834 uint64_t reset_cbar;
835 uint32_t reset_auxcr;
836 bool reset_hivecs;
837
838 uint32_t dcz_blocksize;
839 uint64_t rvbar;
840
841
842 int gic_num_lrs;
843 int gic_vpribits;
844 int gic_vprebits;
845
846
847
848
849
850
851 bool cfgend;
852
853 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
854 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
855
856 int32_t node_id;
857
858
859 uint8_t device_irq_level;
860};
861
862static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
863{
864 return container_of(env, ARMCPU, env);
865}
866
867uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
868
869#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
870
871#define ENV_OFFSET offsetof(ARMCPU, env)
872
873#ifndef CONFIG_USER_ONLY
874extern const struct VMStateDescription vmstate_arm_cpu;
875#endif
876
877void arm_cpu_do_interrupt(CPUState *cpu);
878void arm_v7m_cpu_do_interrupt(CPUState *cpu);
879bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
880
881void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
882 int flags);
883
884hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
885 MemTxAttrs *attrs);
886
887int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
888int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
889
890
891
892
893int arm_gen_dynamic_xml(CPUState *cpu);
894
895
896
897
898
899const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
900
901int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
902 int cpuid, void *opaque);
903int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
904 int cpuid, void *opaque);
905
906#ifdef TARGET_AARCH64
907int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
908int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
909void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
910#endif
911
912target_ulong do_arm_semihosting(CPUARMState *env);
913void aarch64_sync_32_to_64(CPUARMState *env);
914void aarch64_sync_64_to_32(CPUARMState *env);
915
916static inline bool is_a64(CPUARMState *env)
917{
918 return env->aarch64;
919}
920
921
922
923
924int cpu_arm_signal_handler(int host_signum, void *pinfo,
925 void *puc);
926
927
928
929
930
931
932
933
934
935
936void pmccntr_sync(CPUARMState *env);
937
938
939
940
941
942
943
944#define SCTLR_M (1U << 0)
945#define SCTLR_A (1U << 1)
946#define SCTLR_C (1U << 2)
947#define SCTLR_W (1U << 3)
948#define SCTLR_SA (1U << 3)
949#define SCTLR_P (1U << 4)
950#define SCTLR_SA0 (1U << 4)
951#define SCTLR_D (1U << 5)
952#define SCTLR_CP15BEN (1U << 5)
953#define SCTLR_L (1U << 6)
954#define SCTLR_B (1U << 7)
955#define SCTLR_ITD (1U << 7)
956#define SCTLR_S (1U << 8)
957#define SCTLR_SED (1U << 8)
958#define SCTLR_R (1U << 9)
959#define SCTLR_UMA (1U << 9)
960#define SCTLR_F (1U << 10)
961#define SCTLR_SW (1U << 10)
962#define SCTLR_Z (1U << 11)
963#define SCTLR_I (1U << 12)
964#define SCTLR_V (1U << 13)
965#define SCTLR_RR (1U << 14)
966#define SCTLR_DZE (1U << 14)
967#define SCTLR_L4 (1U << 15)
968#define SCTLR_UCT (1U << 15)
969#define SCTLR_DT (1U << 16)
970#define SCTLR_nTWI (1U << 16)
971#define SCTLR_HA (1U << 17)
972#define SCTLR_BR (1U << 17)
973#define SCTLR_IT (1U << 18)
974#define SCTLR_nTWE (1U << 18)
975#define SCTLR_WXN (1U << 19)
976#define SCTLR_ST (1U << 20)
977#define SCTLR_UWXN (1U << 20)
978#define SCTLR_FI (1U << 21)
979#define SCTLR_U (1U << 22)
980#define SCTLR_XP (1U << 23)
981#define SCTLR_VE (1U << 24)
982#define SCTLR_E0E (1U << 24)
983#define SCTLR_EE (1U << 25)
984#define SCTLR_L2 (1U << 26)
985#define SCTLR_UCI (1U << 26)
986#define SCTLR_NMFI (1U << 27)
987#define SCTLR_TRE (1U << 28)
988#define SCTLR_AFE (1U << 29)
989#define SCTLR_TE (1U << 30)
990
991#define CPTR_TCPAC (1U << 31)
992#define CPTR_TTA (1U << 20)
993#define CPTR_TFP (1U << 10)
994#define CPTR_TZ (1U << 8)
995#define CPTR_EZ (1U << 8)
996
997#define MDCR_EPMAD (1U << 21)
998#define MDCR_EDAD (1U << 20)
999#define MDCR_SPME (1U << 17)
1000#define MDCR_SDD (1U << 16)
1001#define MDCR_SPD (3U << 14)
1002#define MDCR_TDRA (1U << 11)
1003#define MDCR_TDOSA (1U << 10)
1004#define MDCR_TDA (1U << 9)
1005#define MDCR_TDE (1U << 8)
1006#define MDCR_HPME (1U << 7)
1007#define MDCR_TPM (1U << 6)
1008#define MDCR_TPMCR (1U << 5)
1009
1010
1011#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1012
1013#define CPSR_M (0x1fU)
1014#define CPSR_T (1U << 5)
1015#define CPSR_F (1U << 6)
1016#define CPSR_I (1U << 7)
1017#define CPSR_A (1U << 8)
1018#define CPSR_E (1U << 9)
1019#define CPSR_IT_2_7 (0xfc00U)
1020#define CPSR_GE (0xfU << 16)
1021#define CPSR_IL (1U << 20)
1022
1023
1024
1025
1026
1027#define CPSR_RESERVED (0x7U << 21)
1028#define CPSR_J (1U << 24)
1029#define CPSR_IT_0_1 (3U << 25)
1030#define CPSR_Q (1U << 27)
1031#define CPSR_V (1U << 28)
1032#define CPSR_C (1U << 29)
1033#define CPSR_Z (1U << 30)
1034#define CPSR_N (1U << 31)
1035#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1036#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1037
1038#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1039#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1040 | CPSR_NZCV)
1041
1042#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1043
1044#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1045
1046#define CPSR_ERET_MASK (~CPSR_RESERVED)
1047
1048
1049#define XPSR_EXCP 0x1ffU
1050#define XPSR_SPREALIGN (1U << 9)
1051#define XPSR_IT_2_7 CPSR_IT_2_7
1052#define XPSR_GE CPSR_GE
1053#define XPSR_SFPA (1U << 20)
1054#define XPSR_T (1U << 24)
1055#define XPSR_IT_0_1 CPSR_IT_0_1
1056#define XPSR_Q CPSR_Q
1057#define XPSR_V CPSR_V
1058#define XPSR_C CPSR_C
1059#define XPSR_Z CPSR_Z
1060#define XPSR_N CPSR_N
1061#define XPSR_NZCV CPSR_NZCV
1062#define XPSR_IT CPSR_IT
1063
1064#define TTBCR_N (7U << 0)
1065#define TTBCR_T0SZ (7U << 0)
1066#define TTBCR_PD0 (1U << 4)
1067#define TTBCR_PD1 (1U << 5)
1068#define TTBCR_EPD0 (1U << 7)
1069#define TTBCR_IRGN0 (3U << 8)
1070#define TTBCR_ORGN0 (3U << 10)
1071#define TTBCR_SH0 (3U << 12)
1072#define TTBCR_T1SZ (3U << 16)
1073#define TTBCR_A1 (1U << 22)
1074#define TTBCR_EPD1 (1U << 23)
1075#define TTBCR_IRGN1 (3U << 24)
1076#define TTBCR_ORGN1 (3U << 26)
1077#define TTBCR_SH1 (1U << 28)
1078#define TTBCR_EAE (1U << 31)
1079
1080
1081
1082
1083
1084#define PSTATE_SP (1U)
1085#define PSTATE_M (0xFU)
1086#define PSTATE_nRW (1U << 4)
1087#define PSTATE_F (1U << 6)
1088#define PSTATE_I (1U << 7)
1089#define PSTATE_A (1U << 8)
1090#define PSTATE_D (1U << 9)
1091#define PSTATE_IL (1U << 20)
1092#define PSTATE_SS (1U << 21)
1093#define PSTATE_V (1U << 28)
1094#define PSTATE_C (1U << 29)
1095#define PSTATE_Z (1U << 30)
1096#define PSTATE_N (1U << 31)
1097#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1098#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1099#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
1100
1101#define PSTATE_MODE_EL3h 13
1102#define PSTATE_MODE_EL3t 12
1103#define PSTATE_MODE_EL2h 9
1104#define PSTATE_MODE_EL2t 8
1105#define PSTATE_MODE_EL1h 5
1106#define PSTATE_MODE_EL1t 4
1107#define PSTATE_MODE_EL0t 0
1108
1109
1110
1111
1112void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1113
1114
1115static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1116{
1117 return (el << 2) | handler;
1118}
1119
1120
1121
1122
1123
1124static inline uint32_t pstate_read(CPUARMState *env)
1125{
1126 int ZF;
1127
1128 ZF = (env->ZF == 0);
1129 return (env->NF & 0x80000000) | (ZF << 30)
1130 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1131 | env->pstate | env->daif;
1132}
1133
1134static inline void pstate_write(CPUARMState *env, uint32_t val)
1135{
1136 env->ZF = (~val) & PSTATE_Z;
1137 env->NF = val;
1138 env->CF = (val >> 29) & 1;
1139 env->VF = (val << 3) & 0x80000000;
1140 env->daif = val & PSTATE_DAIF;
1141 env->pstate = val & ~CACHED_PSTATE_BITS;
1142}
1143
1144
1145uint32_t cpsr_read(CPUARMState *env);
1146
1147typedef enum CPSRWriteType {
1148 CPSRWriteByInstr = 0,
1149 CPSRWriteExceptionReturn = 1,
1150 CPSRWriteRaw = 2,
1151 CPSRWriteByGDBStub = 3,
1152} CPSRWriteType;
1153
1154
1155void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1156 CPSRWriteType write_type);
1157
1158
1159static inline uint32_t xpsr_read(CPUARMState *env)
1160{
1161 int ZF;
1162 ZF = (env->ZF == 0);
1163 return (env->NF & 0x80000000) | (ZF << 30)
1164 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1165 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1166 | ((env->condexec_bits & 0xfc) << 8)
1167 | env->v7m.exception;
1168}
1169
1170
1171static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1172{
1173 if (mask & XPSR_NZCV) {
1174 env->ZF = (~val) & XPSR_Z;
1175 env->NF = val;
1176 env->CF = (val >> 29) & 1;
1177 env->VF = (val << 3) & 0x80000000;
1178 }
1179 if (mask & XPSR_Q) {
1180 env->QF = ((val & XPSR_Q) != 0);
1181 }
1182 if (mask & XPSR_T) {
1183 env->thumb = ((val & XPSR_T) != 0);
1184 }
1185 if (mask & XPSR_IT_0_1) {
1186 env->condexec_bits &= ~3;
1187 env->condexec_bits |= (val >> 25) & 3;
1188 }
1189 if (mask & XPSR_IT_2_7) {
1190 env->condexec_bits &= 3;
1191 env->condexec_bits |= (val >> 8) & 0xfc;
1192 }
1193 if (mask & XPSR_EXCP) {
1194
1195 write_v7m_exception(env, val & XPSR_EXCP);
1196 }
1197}
1198
1199#define HCR_VM (1ULL << 0)
1200#define HCR_SWIO (1ULL << 1)
1201#define HCR_PTW (1ULL << 2)
1202#define HCR_FMO (1ULL << 3)
1203#define HCR_IMO (1ULL << 4)
1204#define HCR_AMO (1ULL << 5)
1205#define HCR_VF (1ULL << 6)
1206#define HCR_VI (1ULL << 7)
1207#define HCR_VSE (1ULL << 8)
1208#define HCR_FB (1ULL << 9)
1209#define HCR_BSU_MASK (3ULL << 10)
1210#define HCR_DC (1ULL << 12)
1211#define HCR_TWI (1ULL << 13)
1212#define HCR_TWE (1ULL << 14)
1213#define HCR_TID0 (1ULL << 15)
1214#define HCR_TID1 (1ULL << 16)
1215#define HCR_TID2 (1ULL << 17)
1216#define HCR_TID3 (1ULL << 18)
1217#define HCR_TSC (1ULL << 19)
1218#define HCR_TIDCP (1ULL << 20)
1219#define HCR_TACR (1ULL << 21)
1220#define HCR_TSW (1ULL << 22)
1221#define HCR_TPC (1ULL << 23)
1222#define HCR_TPU (1ULL << 24)
1223#define HCR_TTLB (1ULL << 25)
1224#define HCR_TVM (1ULL << 26)
1225#define HCR_TGE (1ULL << 27)
1226#define HCR_TDZ (1ULL << 28)
1227#define HCR_HCD (1ULL << 29)
1228#define HCR_TRVM (1ULL << 30)
1229#define HCR_RW (1ULL << 31)
1230#define HCR_CD (1ULL << 32)
1231#define HCR_ID (1ULL << 33)
1232#define HCR_MASK ((1ULL << 34) - 1)
1233
1234#define SCR_NS (1U << 0)
1235#define SCR_IRQ (1U << 1)
1236#define SCR_FIQ (1U << 2)
1237#define SCR_EA (1U << 3)
1238#define SCR_FW (1U << 4)
1239#define SCR_AW (1U << 5)
1240#define SCR_NET (1U << 6)
1241#define SCR_SMD (1U << 7)
1242#define SCR_HCE (1U << 8)
1243#define SCR_SIF (1U << 9)
1244#define SCR_RW (1U << 10)
1245#define SCR_ST (1U << 11)
1246#define SCR_TWI (1U << 12)
1247#define SCR_TWE (1U << 13)
1248#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1249#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1250
1251
1252uint32_t vfp_get_fpscr(CPUARMState *env);
1253void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1254
1255
1256
1257
1258
1259
1260
1261
1262#define FPSR_MASK 0xf800009f
1263#define FPCR_MASK 0x07f79f00
1264
1265#define FPCR_FZ16 (1 << 19)
1266#define FPCR_FZ (1 << 24)
1267#define FPCR_DN (1 << 25)
1268
1269static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1270{
1271 return vfp_get_fpscr(env) & FPSR_MASK;
1272}
1273
1274static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1275{
1276 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1277 vfp_set_fpscr(env, new_fpscr);
1278}
1279
1280static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1281{
1282 return vfp_get_fpscr(env) & FPCR_MASK;
1283}
1284
1285static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1286{
1287 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1288 vfp_set_fpscr(env, new_fpscr);
1289}
1290
1291enum arm_cpu_mode {
1292 ARM_CPU_MODE_USR = 0x10,
1293 ARM_CPU_MODE_FIQ = 0x11,
1294 ARM_CPU_MODE_IRQ = 0x12,
1295 ARM_CPU_MODE_SVC = 0x13,
1296 ARM_CPU_MODE_MON = 0x16,
1297 ARM_CPU_MODE_ABT = 0x17,
1298 ARM_CPU_MODE_HYP = 0x1a,
1299 ARM_CPU_MODE_UND = 0x1b,
1300 ARM_CPU_MODE_SYS = 0x1f
1301};
1302
1303
1304#define ARM_VFP_FPSID 0
1305#define ARM_VFP_FPSCR 1
1306#define ARM_VFP_MVFR2 5
1307#define ARM_VFP_MVFR1 6
1308#define ARM_VFP_MVFR0 7
1309#define ARM_VFP_FPEXC 8
1310#define ARM_VFP_FPINST 9
1311#define ARM_VFP_FPINST2 10
1312
1313
1314#define ARM_IWMMXT_wCID 0
1315#define ARM_IWMMXT_wCon 1
1316#define ARM_IWMMXT_wCSSF 2
1317#define ARM_IWMMXT_wCASF 3
1318#define ARM_IWMMXT_wCGR0 8
1319#define ARM_IWMMXT_wCGR1 9
1320#define ARM_IWMMXT_wCGR2 10
1321#define ARM_IWMMXT_wCGR3 11
1322
1323
1324FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1325FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1326FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1327FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1328FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1329FIELD(V7M_CCR, STKALIGN, 9, 1)
1330FIELD(V7M_CCR, DC, 16, 1)
1331FIELD(V7M_CCR, IC, 17, 1)
1332
1333
1334FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1335FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1336FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1337FIELD(V7M_SCR, SEVONPEND, 4, 1)
1338
1339
1340FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1341FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1342FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1343FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1344FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1345FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1346FIELD(V7M_AIRCR, PRIS, 14, 1)
1347FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1348FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1349
1350
1351FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1352FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1353FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1354FIELD(V7M_CFSR, MSTKERR, 4, 1)
1355FIELD(V7M_CFSR, MLSPERR, 5, 1)
1356FIELD(V7M_CFSR, MMARVALID, 7, 1)
1357
1358
1359FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1360FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1361FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1362FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1363FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1364FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1365FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1366
1367
1368FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1369FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1370FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1371FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1372FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1373FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1374
1375
1376FIELD(V7M_CFSR, MMFSR, 0, 8)
1377FIELD(V7M_CFSR, BFSR, 8, 8)
1378FIELD(V7M_CFSR, UFSR, 16, 16)
1379
1380
1381FIELD(V7M_HFSR, VECTTBL, 1, 1)
1382FIELD(V7M_HFSR, FORCED, 30, 1)
1383FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1384
1385
1386FIELD(V7M_DFSR, HALTED, 0, 1)
1387FIELD(V7M_DFSR, BKPT, 1, 1)
1388FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1389FIELD(V7M_DFSR, VCATCH, 3, 1)
1390FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1391
1392
1393FIELD(V7M_SFSR, INVEP, 0, 1)
1394FIELD(V7M_SFSR, INVIS, 1, 1)
1395FIELD(V7M_SFSR, INVER, 2, 1)
1396FIELD(V7M_SFSR, AUVIOL, 3, 1)
1397FIELD(V7M_SFSR, INVTRAN, 4, 1)
1398FIELD(V7M_SFSR, LSPERR, 5, 1)
1399FIELD(V7M_SFSR, SFARVALID, 6, 1)
1400FIELD(V7M_SFSR, LSERR, 7, 1)
1401
1402
1403FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1404FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1405FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1406
1407
1408FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1409FIELD(V7M_CLIDR, LOUIS, 21, 3)
1410FIELD(V7M_CLIDR, LOC, 24, 3)
1411FIELD(V7M_CLIDR, LOUU, 27, 3)
1412FIELD(V7M_CLIDR, ICB, 30, 2)
1413
1414FIELD(V7M_CSSELR, IND, 0, 1)
1415FIELD(V7M_CSSELR, LEVEL, 1, 3)
1416
1417
1418
1419
1420FIELD(V7M_CSSELR, INDEX, 0, 4)
1421
1422QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1423
1424
1425
1426
1427
1428enum arm_features {
1429 ARM_FEATURE_VFP,
1430 ARM_FEATURE_AUXCR,
1431 ARM_FEATURE_XSCALE,
1432 ARM_FEATURE_IWMMXT,
1433 ARM_FEATURE_V6,
1434 ARM_FEATURE_V6K,
1435 ARM_FEATURE_V7,
1436 ARM_FEATURE_THUMB2,
1437 ARM_FEATURE_PMSA,
1438 ARM_FEATURE_VFP3,
1439 ARM_FEATURE_VFP_FP16,
1440 ARM_FEATURE_NEON,
1441 ARM_FEATURE_THUMB_DIV,
1442 ARM_FEATURE_M,
1443 ARM_FEATURE_OMAPCP,
1444 ARM_FEATURE_THUMB2EE,
1445 ARM_FEATURE_V7MP,
1446 ARM_FEATURE_V7VE,
1447 ARM_FEATURE_V4T,
1448 ARM_FEATURE_V5,
1449 ARM_FEATURE_STRONGARM,
1450 ARM_FEATURE_VAPA,
1451 ARM_FEATURE_ARM_DIV,
1452 ARM_FEATURE_VFP4,
1453 ARM_FEATURE_GENERIC_TIMER,
1454 ARM_FEATURE_MVFR,
1455 ARM_FEATURE_DUMMY_C15_REGS,
1456 ARM_FEATURE_CACHE_TEST_CLEAN,
1457 ARM_FEATURE_CACHE_DIRTY_REG,
1458 ARM_FEATURE_CACHE_BLOCK_OPS,
1459 ARM_FEATURE_MPIDR,
1460 ARM_FEATURE_PXN,
1461 ARM_FEATURE_LPAE,
1462 ARM_FEATURE_V8,
1463 ARM_FEATURE_AARCH64,
1464 ARM_FEATURE_V8_AES,
1465 ARM_FEATURE_CBAR,
1466 ARM_FEATURE_CRC,
1467 ARM_FEATURE_CBAR_RO,
1468 ARM_FEATURE_EL2,
1469 ARM_FEATURE_EL3,
1470 ARM_FEATURE_V8_SHA1,
1471 ARM_FEATURE_V8_SHA256,
1472 ARM_FEATURE_V8_PMULL,
1473 ARM_FEATURE_THUMB_DSP,
1474 ARM_FEATURE_PMU,
1475 ARM_FEATURE_VBAR,
1476 ARM_FEATURE_M_SECURITY,
1477 ARM_FEATURE_JAZELLE,
1478 ARM_FEATURE_SVE,
1479 ARM_FEATURE_V8_SHA512,
1480 ARM_FEATURE_V8_SHA3,
1481 ARM_FEATURE_V8_SM3,
1482 ARM_FEATURE_V8_SM4,
1483 ARM_FEATURE_V8_ATOMICS,
1484 ARM_FEATURE_V8_RDM,
1485 ARM_FEATURE_V8_DOTPROD,
1486 ARM_FEATURE_V8_FP16,
1487 ARM_FEATURE_V8_FCMA,
1488 ARM_FEATURE_M_MAIN,
1489};
1490
1491static inline int arm_feature(CPUARMState *env, int feature)
1492{
1493 return (env->features & (1ULL << feature)) != 0;
1494}
1495
1496#if !defined(CONFIG_USER_ONLY)
1497
1498
1499
1500
1501
1502
1503static inline bool arm_is_secure_below_el3(CPUARMState *env)
1504{
1505 if (arm_feature(env, ARM_FEATURE_EL3)) {
1506 return !(env->cp15.scr_el3 & SCR_NS);
1507 } else {
1508
1509
1510
1511 return false;
1512 }
1513}
1514
1515
1516static inline bool arm_is_el3_or_mon(CPUARMState *env)
1517{
1518 if (arm_feature(env, ARM_FEATURE_EL3)) {
1519 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1520
1521 return true;
1522 } else if (!is_a64(env) &&
1523 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1524
1525 return true;
1526 }
1527 }
1528 return false;
1529}
1530
1531
1532static inline bool arm_is_secure(CPUARMState *env)
1533{
1534 if (arm_is_el3_or_mon(env)) {
1535 return true;
1536 }
1537 return arm_is_secure_below_el3(env);
1538}
1539
1540#else
1541static inline bool arm_is_secure_below_el3(CPUARMState *env)
1542{
1543 return false;
1544}
1545
1546static inline bool arm_is_secure(CPUARMState *env)
1547{
1548 return false;
1549}
1550#endif
1551
1552
1553static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1554{
1555
1556
1557
1558 assert(el >= 1 && el <= 3);
1559 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1560
1561
1562
1563
1564
1565 if (el == 3) {
1566 return aa64;
1567 }
1568
1569 if (arm_feature(env, ARM_FEATURE_EL3)) {
1570 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1571 }
1572
1573 if (el == 2) {
1574 return aa64;
1575 }
1576
1577 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1578 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1579 }
1580
1581 return aa64;
1582}
1583
1584
1585
1586
1587
1588
1589
1590
1591static inline bool access_secure_reg(CPUARMState *env)
1592{
1593 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1594 !arm_el_is_aa64(env, 3) &&
1595 !(env->cp15.scr_el3 & SCR_NS));
1596
1597 return ret;
1598}
1599
1600
1601#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1602 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1603
1604#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1605 do { \
1606 if (_secure) { \
1607 (_env)->cp15._regname##_s = (_val); \
1608 } else { \
1609 (_env)->cp15._regname##_ns = (_val); \
1610 } \
1611 } while (0)
1612
1613
1614
1615
1616
1617
1618#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1619 A32_BANKED_REG_GET((_env), _regname, \
1620 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1621
1622#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1623 A32_BANKED_REG_SET((_env), _regname, \
1624 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1625 (_val))
1626
1627void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1628uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1629 uint32_t cur_el, bool secure);
1630
1631
1632#ifndef CONFIG_USER_ONLY
1633bool armv7m_nvic_can_take_pending_exception(void *opaque);
1634#else
1635static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
1636{
1637 return true;
1638}
1639#endif
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
1680 bool *ptargets_secure);
1681
1682
1683
1684
1685
1686
1687
1688
1689void armv7m_nvic_acknowledge_irq(void *opaque);
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711int armv7m_nvic_raw_execution_priority(void *opaque);
1712
1713
1714
1715
1716
1717
1718
1719#ifndef CONFIG_USER_ONLY
1720bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
1721#else
1722static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
1723{
1724 return false;
1725}
1726#endif
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
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1745
1746
1747
1748
1749
1750
1751
1752
1753
1754#define CP_REG_AA64_SHIFT 28
1755#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1756
1757
1758
1759
1760
1761#define CP_REG_NS_SHIFT 29
1762#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1763
1764#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1765 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1766 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1767
1768#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1769 (CP_REG_AA64_MASK | \
1770 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1771 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1772 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1773 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1774 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1775 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1776
1777
1778
1779
1780static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1781{
1782 uint32_t cpregid = kvmid;
1783 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1784 cpregid |= CP_REG_AA64_MASK;
1785 } else {
1786 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1787 cpregid |= (1 << 15);
1788 }
1789
1790
1791
1792
1793 cpregid |= 1 << CP_REG_NS_SHIFT;
1794 }
1795 return cpregid;
1796}
1797
1798
1799
1800
1801static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1802{
1803 uint64_t kvmid;
1804
1805 if (cpregid & CP_REG_AA64_MASK) {
1806 kvmid = cpregid & ~CP_REG_AA64_MASK;
1807 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1808 } else {
1809 kvmid = cpregid & ~(1 << 15);
1810 if (cpregid & (1 << 15)) {
1811 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1812 } else {
1813 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1814 }
1815 }
1816 return kvmid;
1817}
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841#define ARM_CP_SPECIAL 0x0001
1842#define ARM_CP_CONST 0x0002
1843#define ARM_CP_64BIT 0x0004
1844#define ARM_CP_SUPPRESS_TB_END 0x0008
1845#define ARM_CP_OVERRIDE 0x0010
1846#define ARM_CP_ALIAS 0x0020
1847#define ARM_CP_IO 0x0040
1848#define ARM_CP_NO_RAW 0x0080
1849#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
1850#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
1851#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
1852#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
1853#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
1854#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1855#define ARM_CP_FPU 0x1000
1856#define ARM_CP_SVE 0x2000
1857#define ARM_CP_NO_GDB 0x4000
1858
1859#define ARM_CP_SENTINEL 0xffff
1860
1861#define ARM_CP_FLAG_MASK 0x70ff
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872enum {
1873 ARM_CP_STATE_AA32 = 0,
1874 ARM_CP_STATE_AA64 = 1,
1875 ARM_CP_STATE_BOTH = 2,
1876};
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888enum {
1889 ARM_CP_SECSTATE_S = (1 << 0),
1890 ARM_CP_SECSTATE_NS = (1 << 1),
1891};
1892
1893
1894
1895
1896
1897static inline bool cptype_valid(int cptype)
1898{
1899 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1900 || ((cptype & ARM_CP_SPECIAL) &&
1901 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1902}
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921#define PL3_R 0x80
1922#define PL3_W 0x40
1923#define PL2_R (0x20 | PL3_R)
1924#define PL2_W (0x10 | PL3_W)
1925#define PL1_R (0x08 | PL2_R)
1926#define PL1_W (0x04 | PL2_W)
1927#define PL0_R (0x02 | PL1_R)
1928#define PL0_W (0x01 | PL1_W)
1929
1930#define PL3_RW (PL3_R | PL3_W)
1931#define PL2_RW (PL2_R | PL2_W)
1932#define PL1_RW (PL1_R | PL1_W)
1933#define PL0_RW (PL0_R | PL0_W)
1934
1935
1936static inline int arm_highest_el(CPUARMState *env)
1937{
1938 if (arm_feature(env, ARM_FEATURE_EL3)) {
1939 return 3;
1940 }
1941 if (arm_feature(env, ARM_FEATURE_EL2)) {
1942 return 2;
1943 }
1944 return 1;
1945}
1946
1947
1948static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
1949{
1950 return env->v7m.exception != 0;
1951}
1952
1953
1954
1955
1956static inline int arm_current_el(CPUARMState *env)
1957{
1958 if (arm_feature(env, ARM_FEATURE_M)) {
1959 return arm_v7m_is_handler_mode(env) ||
1960 !(env->v7m.control[env->v7m.secure] & 1);
1961 }
1962
1963 if (is_a64(env)) {
1964 return extract32(env->pstate, 2, 2);
1965 }
1966
1967 switch (env->uncached_cpsr & 0x1f) {
1968 case ARM_CPU_MODE_USR:
1969 return 0;
1970 case ARM_CPU_MODE_HYP:
1971 return 2;
1972 case ARM_CPU_MODE_MON:
1973 return 3;
1974 default:
1975 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1976
1977
1978
1979 return 3;
1980 }
1981
1982 return 1;
1983 }
1984}
1985
1986typedef struct ARMCPRegInfo ARMCPRegInfo;
1987
1988typedef enum CPAccessResult {
1989
1990 CP_ACCESS_OK = 0,
1991
1992
1993
1994
1995
1996
1997 CP_ACCESS_TRAP = 1,
1998
1999
2000
2001
2002 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2003
2004 CP_ACCESS_TRAP_EL2 = 3,
2005 CP_ACCESS_TRAP_EL3 = 4,
2006
2007 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2008 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2009
2010
2011
2012 CP_ACCESS_TRAP_FP_EL2 = 7,
2013 CP_ACCESS_TRAP_FP_EL3 = 8,
2014} CPAccessResult;
2015
2016
2017
2018
2019typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2020typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2021 uint64_t value);
2022
2023typedef CPAccessResult CPAccessFn(CPUARMState *env,
2024 const ARMCPRegInfo *opaque,
2025 bool isread);
2026
2027typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2028
2029#define CP_ANY 0xff
2030
2031
2032struct ARMCPRegInfo {
2033
2034 const char *name;
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052 uint8_t cp;
2053 uint8_t crn;
2054 uint8_t crm;
2055 uint8_t opc0;
2056 uint8_t opc1;
2057 uint8_t opc2;
2058
2059 int state;
2060
2061 int type;
2062
2063 int access;
2064
2065 int secure;
2066
2067
2068
2069
2070 void *opaque;
2071
2072
2073
2074 uint64_t resetvalue;
2075
2076
2077
2078
2079
2080
2081 ptrdiff_t fieldoffset;
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094 ptrdiff_t bank_fieldoffsets[2];
2095
2096
2097
2098
2099
2100
2101 CPAccessFn *accessfn;
2102
2103
2104
2105
2106 CPReadFn *readfn;
2107
2108
2109
2110
2111 CPWriteFn *writefn;
2112
2113
2114
2115
2116
2117 CPReadFn *raw_readfn;
2118
2119
2120
2121
2122
2123
2124 CPWriteFn *raw_writefn;
2125
2126
2127
2128
2129 CPResetFn *resetfn;
2130};
2131
2132
2133
2134
2135#define CPREG_FIELD32(env, ri) \
2136 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2137#define CPREG_FIELD64(env, ri) \
2138 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2139
2140#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2141
2142void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2143 const ARMCPRegInfo *regs, void *opaque);
2144void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2145 const ARMCPRegInfo *regs, void *opaque);
2146static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2147{
2148 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2149}
2150static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2151{
2152 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2153}
2154const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2155
2156
2157void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2158 uint64_t value);
2159
2160uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2161
2162
2163
2164
2165void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2166
2167
2168
2169
2170static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2171{
2172 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2173}
2174
2175static inline bool cp_access_ok(int current_el,
2176 const ARMCPRegInfo *ri, int isread)
2177{
2178 return (ri->access >> ((current_el * 2) + isread)) & 1;
2179}
2180
2181
2182uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198bool write_list_to_cpustate(ARMCPU *cpu);
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214bool write_cpustate_to_list(ARMCPU *cpu);
2215
2216#define ARM_CPUID_TI915T 0x54029152
2217#define ARM_CPUID_TI925T 0x54029252
2218
2219#if defined(CONFIG_USER_ONLY)
2220#define TARGET_PAGE_BITS 12
2221#else
2222
2223
2224
2225#define TARGET_PAGE_BITS_VARY
2226#define TARGET_PAGE_BITS_MIN 10
2227#endif
2228
2229#if defined(TARGET_AARCH64)
2230# define TARGET_PHYS_ADDR_SPACE_BITS 48
2231# define TARGET_VIRT_ADDR_SPACE_BITS 64
2232#else
2233# define TARGET_PHYS_ADDR_SPACE_BITS 40
2234# define TARGET_VIRT_ADDR_SPACE_BITS 32
2235#endif
2236
2237static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
2238 unsigned int target_el)
2239{
2240 CPUARMState *env = cs->env_ptr;
2241 unsigned int cur_el = arm_current_el(env);
2242 bool secure = arm_is_secure(env);
2243 bool pstate_unmasked;
2244 int8_t unmasked = 0;
2245
2246
2247
2248
2249
2250 if (cur_el > target_el) {
2251 return false;
2252 }
2253
2254 switch (excp_idx) {
2255 case EXCP_FIQ:
2256 pstate_unmasked = !(env->daif & PSTATE_F);
2257 break;
2258
2259 case EXCP_IRQ:
2260 pstate_unmasked = !(env->daif & PSTATE_I);
2261 break;
2262
2263 case EXCP_VFIQ:
2264 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
2265
2266 return false;
2267 }
2268 return !(env->daif & PSTATE_F);
2269 case EXCP_VIRQ:
2270 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
2271
2272 return false;
2273 }
2274 return !(env->daif & PSTATE_I);
2275 default:
2276 g_assert_not_reached();
2277 }
2278
2279
2280
2281
2282
2283 if ((target_el > cur_el) && (target_el != 1)) {
2284
2285 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2286
2287
2288
2289
2290
2291 if (target_el == 3 || !secure) {
2292 unmasked = 1;
2293 }
2294 } else {
2295
2296
2297
2298
2299 bool hcr, scr;
2300
2301 switch (excp_idx) {
2302 case EXCP_FIQ:
2303
2304
2305
2306
2307
2308
2309 hcr = (env->cp15.hcr_el2 & HCR_FMO);
2310 scr = (env->cp15.scr_el3 & SCR_FIQ);
2311
2312
2313
2314
2315
2316
2317 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
2318 break;
2319 case EXCP_IRQ:
2320
2321
2322
2323
2324
2325
2326 hcr = (env->cp15.hcr_el2 & HCR_IMO);
2327 scr = false;
2328 break;
2329 default:
2330 g_assert_not_reached();
2331 }
2332
2333 if ((scr || hcr) && !secure) {
2334 unmasked = 1;
2335 }
2336 }
2337 }
2338
2339
2340
2341
2342 return unmasked || pstate_unmasked;
2343}
2344
2345#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2346#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2347#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2348
2349#define cpu_signal_handler cpu_arm_signal_handler
2350#define cpu_list arm_cpu_list
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431#define ARM_MMU_IDX_A 0x10
2432#define ARM_MMU_IDX_NOTLB 0x20
2433#define ARM_MMU_IDX_M 0x40
2434
2435
2436#define ARM_MMU_IDX_M_PRIV 0x1
2437#define ARM_MMU_IDX_M_NEGPRI 0x2
2438#define ARM_MMU_IDX_M_S 0x4
2439
2440#define ARM_MMU_IDX_TYPE_MASK (~0x7)
2441#define ARM_MMU_IDX_COREIDX_MASK 0x7
2442
2443typedef enum ARMMMUIdx {
2444 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
2445 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
2446 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
2447 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
2448 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
2449 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
2450 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
2451 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
2452 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
2453 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
2454 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M,
2455 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M,
2456 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M,
2457 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M,
2458 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M,
2459
2460
2461
2462 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
2463 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
2464} ARMMMUIdx;
2465
2466
2467
2468
2469typedef enum ARMMMUIdxBit {
2470 ARMMMUIdxBit_S12NSE0 = 1 << 0,
2471 ARMMMUIdxBit_S12NSE1 = 1 << 1,
2472 ARMMMUIdxBit_S1E2 = 1 << 2,
2473 ARMMMUIdxBit_S1E3 = 1 << 3,
2474 ARMMMUIdxBit_S1SE0 = 1 << 4,
2475 ARMMMUIdxBit_S1SE1 = 1 << 5,
2476 ARMMMUIdxBit_S2NS = 1 << 6,
2477 ARMMMUIdxBit_MUser = 1 << 0,
2478 ARMMMUIdxBit_MPriv = 1 << 1,
2479 ARMMMUIdxBit_MUserNegPri = 1 << 2,
2480 ARMMMUIdxBit_MPrivNegPri = 1 << 3,
2481 ARMMMUIdxBit_MSUser = 1 << 4,
2482 ARMMMUIdxBit_MSPriv = 1 << 5,
2483 ARMMMUIdxBit_MSUserNegPri = 1 << 6,
2484 ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
2485} ARMMMUIdxBit;
2486
2487#define MMU_USER_IDX 0
2488
2489static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
2490{
2491 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
2492}
2493
2494static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
2495{
2496 if (arm_feature(env, ARM_FEATURE_M)) {
2497 return mmu_idx | ARM_MMU_IDX_M;
2498 } else {
2499 return mmu_idx | ARM_MMU_IDX_A;
2500 }
2501}
2502
2503
2504static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
2505{
2506 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
2507 case ARM_MMU_IDX_A:
2508 return mmu_idx & 3;
2509 case ARM_MMU_IDX_M:
2510 return mmu_idx & ARM_MMU_IDX_M_PRIV;
2511 default:
2512 g_assert_not_reached();
2513 }
2514}
2515
2516
2517
2518
2519static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
2520 bool secstate,
2521 bool priv)
2522{
2523 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
2524
2525 if (priv) {
2526 mmu_idx |= ARM_MMU_IDX_M_PRIV;
2527 }
2528
2529 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
2530 mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
2531 }
2532
2533 if (secstate) {
2534 mmu_idx |= ARM_MMU_IDX_M_S;
2535 }
2536
2537 return mmu_idx;
2538}
2539
2540
2541static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
2542 bool secstate)
2543{
2544 bool priv = arm_current_el(env) != 0;
2545
2546 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
2547}
2548
2549
2550static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
2551{
2552 int el = arm_current_el(env);
2553
2554 if (arm_feature(env, ARM_FEATURE_M)) {
2555 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
2556
2557 return arm_to_core_mmu_idx(mmu_idx);
2558 }
2559
2560 if (el < 2 && arm_is_secure_below_el3(env)) {
2561 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
2562 }
2563 return el;
2564}
2565
2566
2567typedef enum ARMASIdx {
2568 ARMASIdx_NS = 0,
2569 ARMASIdx_S = 1,
2570} ARMASIdx;
2571
2572
2573static inline int arm_debug_target_el(CPUARMState *env)
2574{
2575 bool secure = arm_is_secure(env);
2576 bool route_to_el2 = false;
2577
2578 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2579 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2580 env->cp15.mdcr_el2 & (1 << 8);
2581 }
2582
2583 if (route_to_el2) {
2584 return 2;
2585 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2586 !arm_el_is_aa64(env, 3) && secure) {
2587 return 3;
2588 } else {
2589 return 1;
2590 }
2591}
2592
2593static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2594{
2595
2596
2597
2598 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2599}
2600
2601static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2602{
2603 if (arm_is_secure(env)) {
2604
2605 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
2606 || arm_current_el(env) == 3) {
2607 return false;
2608 }
2609 }
2610
2611 if (arm_current_el(env) == arm_debug_target_el(env)) {
2612 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
2613 || (env->daif & PSTATE_D)) {
2614 return false;
2615 }
2616 }
2617 return true;
2618}
2619
2620static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2621{
2622 int el = arm_current_el(env);
2623
2624 if (el == 0 && arm_el_is_aa64(env, 1)) {
2625 return aa64_generate_debug_exceptions(env);
2626 }
2627
2628 if (arm_is_secure(env)) {
2629 int spd;
2630
2631 if (el == 0 && (env->cp15.sder & 1)) {
2632
2633
2634
2635
2636 return true;
2637 }
2638
2639 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2640 switch (spd) {
2641 case 1:
2642
2643 case 0:
2644
2645
2646
2647
2648
2649 return true;
2650 case 2:
2651 return false;
2652 case 3:
2653 return true;
2654 }
2655 }
2656
2657 return el != 2;
2658}
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2675{
2676 if (env->aarch64) {
2677 return aa64_generate_debug_exceptions(env);
2678 } else {
2679 return aa32_generate_debug_exceptions(env);
2680 }
2681}
2682
2683
2684
2685
2686static inline bool arm_singlestep_active(CPUARMState *env)
2687{
2688 return extract32(env->cp15.mdscr_el1, 0, 1)
2689 && arm_el_is_aa64(env, arm_debug_target_el(env))
2690 && arm_generate_debug_exceptions(env);
2691}
2692
2693static inline bool arm_sctlr_b(CPUARMState *env)
2694{
2695 return
2696
2697
2698
2699
2700#ifndef CONFIG_USER_ONLY
2701 !arm_feature(env, ARM_FEATURE_V7) &&
2702#endif
2703 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2704}
2705
2706
2707static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2708{
2709 int cur_el;
2710
2711
2712 if (!is_a64(env)) {
2713 return
2714#ifdef CONFIG_USER_ONLY
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726 arm_sctlr_b(env) ||
2727#endif
2728 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2729 }
2730
2731 cur_el = arm_current_el(env);
2732
2733 if (cur_el == 0) {
2734 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2735 }
2736
2737 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2738}
2739
2740#include "exec/cpu-all.h"
2741
2742
2743
2744
2745
2746
2747#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2748#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2749#define ARM_TBFLAG_MMUIDX_SHIFT 28
2750#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2751#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2752#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2753#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2754#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2755
2756#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2757#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2758
2759
2760#define ARM_TBFLAG_THUMB_SHIFT 0
2761#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2762#define ARM_TBFLAG_VECLEN_SHIFT 1
2763#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2764#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2765#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2766#define ARM_TBFLAG_VFPEN_SHIFT 7
2767#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2768#define ARM_TBFLAG_CONDEXEC_SHIFT 8
2769#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2770#define ARM_TBFLAG_SCTLR_B_SHIFT 16
2771#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2772
2773
2774
2775#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2776#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2777
2778
2779
2780
2781#define ARM_TBFLAG_NS_SHIFT 19
2782#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2783#define ARM_TBFLAG_BE_DATA_SHIFT 20
2784#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2785
2786#define ARM_TBFLAG_HANDLER_SHIFT 21
2787#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
2788
2789
2790#define ARM_TBFLAG_TBI0_SHIFT 0
2791#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2792#define ARM_TBFLAG_TBI1_SHIFT 1
2793#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2794#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2
2795#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT)
2796#define ARM_TBFLAG_ZCR_LEN_SHIFT 4
2797#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT)
2798
2799
2800#define ARM_TBFLAG_AARCH64_STATE(F) \
2801 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2802#define ARM_TBFLAG_MMUIDX(F) \
2803 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2804#define ARM_TBFLAG_SS_ACTIVE(F) \
2805 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2806#define ARM_TBFLAG_PSTATE_SS(F) \
2807 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2808#define ARM_TBFLAG_FPEXC_EL(F) \
2809 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2810#define ARM_TBFLAG_THUMB(F) \
2811 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2812#define ARM_TBFLAG_VECLEN(F) \
2813 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2814#define ARM_TBFLAG_VECSTRIDE(F) \
2815 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2816#define ARM_TBFLAG_VFPEN(F) \
2817 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2818#define ARM_TBFLAG_CONDEXEC(F) \
2819 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2820#define ARM_TBFLAG_SCTLR_B(F) \
2821 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2822#define ARM_TBFLAG_XSCALE_CPAR(F) \
2823 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2824#define ARM_TBFLAG_NS(F) \
2825 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2826#define ARM_TBFLAG_BE_DATA(F) \
2827 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2828#define ARM_TBFLAG_HANDLER(F) \
2829 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
2830#define ARM_TBFLAG_TBI0(F) \
2831 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2832#define ARM_TBFLAG_TBI1(F) \
2833 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2834#define ARM_TBFLAG_SVEEXC_EL(F) \
2835 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT)
2836#define ARM_TBFLAG_ZCR_LEN(F) \
2837 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT)
2838
2839static inline bool bswap_code(bool sctlr_b)
2840{
2841#ifdef CONFIG_USER_ONLY
2842
2843
2844
2845
2846 return
2847#ifdef TARGET_WORDS_BIGENDIAN
2848 1 ^
2849#endif
2850 sctlr_b;
2851#else
2852
2853
2854
2855 return 0;
2856#endif
2857}
2858
2859#ifdef CONFIG_USER_ONLY
2860static inline bool arm_cpu_bswap_data(CPUARMState *env)
2861{
2862 return
2863#ifdef TARGET_WORDS_BIGENDIAN
2864 1 ^
2865#endif
2866 arm_cpu_data_is_big_endian(env);
2867}
2868#endif
2869
2870#ifndef CONFIG_USER_ONLY
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
2892#else
2893
2894static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
2895{
2896 return 0;
2897}
2898
2899static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
2900{
2901 return 0;
2902}
2903#endif
2904
2905void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2906 target_ulong *cs_base, uint32_t *flags);
2907
2908enum {
2909 QEMU_PSCI_CONDUIT_DISABLED = 0,
2910 QEMU_PSCI_CONDUIT_SMC = 1,
2911 QEMU_PSCI_CONDUIT_HVC = 2,
2912};
2913
2914#ifndef CONFIG_USER_ONLY
2915
2916static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2917{
2918 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2919}
2920
2921
2922
2923
2924
2925static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2926{
2927 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2928}
2929#endif
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
2942 void *opaque);
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
2954 *opaque);
2955
2956
2957
2958
2959
2960static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
2961{
2962 return &env->vfp.zregs[regno >> 1].d[regno & 1];
2963}
2964
2965
2966
2967
2968
2969static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
2970{
2971 return &env->vfp.zregs[regno].d[0];
2972}
2973
2974
2975
2976
2977
2978static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
2979{
2980 return &env->vfp.zregs[regno].d[0];
2981}
2982
2983
2984extern const uint64_t pred_esz_masks[4];
2985
2986#endif
2987