1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu-common.h"
25#if !defined(CONFIG_USER_ONLY)
26#include "hw/loader.h"
27#endif
28#include "hw/arm/arm.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/kvm.h"
31#include "kvm_arm.h"
32
33static inline void set_feature(CPUARMState *env, int feature)
34{
35 env->features |= 1ULL << feature;
36}
37
38static inline void unset_feature(CPUARMState *env, int feature)
39{
40 env->features &= ~(1ULL << feature);
41}
42
43#ifndef CONFIG_USER_ONLY
44static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
45{
46 ARMCPU *cpu = arm_env_get_cpu(env);
47
48
49 return (cpu->core_count - 1) << 24;
50}
51#endif
52
53static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
54#ifndef CONFIG_USER_ONLY
55 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
56 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
57 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
58 .writefn = arm_cp_write_ignore },
59 { .name = "L2CTLR",
60 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
61 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
62 .writefn = arm_cp_write_ignore },
63#endif
64 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
65 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
66 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
67 { .name = "L2ECTLR",
68 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
69 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
71 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
72 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
74 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
75 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76 { .name = "CPUACTLR",
77 .cp = 15, .opc1 = 0, .crm = 15,
78 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
79 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
80 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
81 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
82 { .name = "CPUECTLR",
83 .cp = 15, .opc1 = 1, .crm = 15,
84 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
85 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
86 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
87 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
88 { .name = "CPUMERRSR",
89 .cp = 15, .opc1 = 2, .crm = 15,
90 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
91 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
92 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
93 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
94 { .name = "L2MERRSR",
95 .cp = 15, .opc1 = 3, .crm = 15,
96 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
97 REGINFO_SENTINEL
98};
99
100static void aarch64_a57_initfn(Object *obj)
101{
102 ARMCPU *cpu = ARM_CPU(obj);
103
104 cpu->dtb_compatible = "arm,cortex-a57";
105 set_feature(&cpu->env, ARM_FEATURE_V8);
106 set_feature(&cpu->env, ARM_FEATURE_VFP4);
107 set_feature(&cpu->env, ARM_FEATURE_NEON);
108 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
109 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
110 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
111 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
112 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
113 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
114 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
115 set_feature(&cpu->env, ARM_FEATURE_CRC);
116 set_feature(&cpu->env, ARM_FEATURE_EL2);
117 set_feature(&cpu->env, ARM_FEATURE_EL3);
118 set_feature(&cpu->env, ARM_FEATURE_PMU);
119 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
120 cpu->midr = 0x411fd070;
121 cpu->revidr = 0x00000000;
122 cpu->reset_fpsid = 0x41034070;
123 cpu->mvfr0 = 0x10110222;
124 cpu->mvfr1 = 0x12111111;
125 cpu->mvfr2 = 0x00000043;
126 cpu->ctr = 0x8444c004;
127 cpu->reset_sctlr = 0x00c50838;
128 cpu->id_pfr0 = 0x00000131;
129 cpu->id_pfr1 = 0x00011011;
130 cpu->id_dfr0 = 0x03010066;
131 cpu->id_afr0 = 0x00000000;
132 cpu->id_mmfr0 = 0x10101105;
133 cpu->id_mmfr1 = 0x40000000;
134 cpu->id_mmfr2 = 0x01260000;
135 cpu->id_mmfr3 = 0x02102211;
136 cpu->id_isar0 = 0x02101110;
137 cpu->id_isar1 = 0x13112111;
138 cpu->id_isar2 = 0x21232042;
139 cpu->id_isar3 = 0x01112131;
140 cpu->id_isar4 = 0x00011142;
141 cpu->id_isar5 = 0x00011121;
142 cpu->id_isar6 = 0;
143 cpu->id_aa64pfr0 = 0x00002222;
144 cpu->id_aa64dfr0 = 0x10305106;
145 cpu->pmceid0 = 0x00000000;
146 cpu->pmceid1 = 0x00000000;
147 cpu->id_aa64isar0 = 0x00011120;
148 cpu->id_aa64mmfr0 = 0x00001124;
149 cpu->dbgdidr = 0x3516d000;
150 cpu->clidr = 0x0a200023;
151 cpu->ccsidr[0] = 0x701fe00a;
152 cpu->ccsidr[1] = 0x201fe012;
153 cpu->ccsidr[2] = 0x70ffe07a;
154 cpu->dcz_blocksize = 4;
155 cpu->gic_num_lrs = 4;
156 cpu->gic_vpribits = 5;
157 cpu->gic_vprebits = 5;
158 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
159}
160
161static void aarch64_a53_initfn(Object *obj)
162{
163 ARMCPU *cpu = ARM_CPU(obj);
164
165 cpu->dtb_compatible = "arm,cortex-a53";
166 set_feature(&cpu->env, ARM_FEATURE_V8);
167 set_feature(&cpu->env, ARM_FEATURE_VFP4);
168 set_feature(&cpu->env, ARM_FEATURE_NEON);
169 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
170 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
171 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
172 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
173 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
174 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
175 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
176 set_feature(&cpu->env, ARM_FEATURE_CRC);
177 set_feature(&cpu->env, ARM_FEATURE_EL2);
178 set_feature(&cpu->env, ARM_FEATURE_EL3);
179 set_feature(&cpu->env, ARM_FEATURE_PMU);
180 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
181 cpu->midr = 0x410fd034;
182 cpu->revidr = 0x00000000;
183 cpu->reset_fpsid = 0x41034070;
184 cpu->mvfr0 = 0x10110222;
185 cpu->mvfr1 = 0x12111111;
186 cpu->mvfr2 = 0x00000043;
187 cpu->ctr = 0x84448004;
188 cpu->reset_sctlr = 0x00c50838;
189 cpu->id_pfr0 = 0x00000131;
190 cpu->id_pfr1 = 0x00011011;
191 cpu->id_dfr0 = 0x03010066;
192 cpu->id_afr0 = 0x00000000;
193 cpu->id_mmfr0 = 0x10101105;
194 cpu->id_mmfr1 = 0x40000000;
195 cpu->id_mmfr2 = 0x01260000;
196 cpu->id_mmfr3 = 0x02102211;
197 cpu->id_isar0 = 0x02101110;
198 cpu->id_isar1 = 0x13112111;
199 cpu->id_isar2 = 0x21232042;
200 cpu->id_isar3 = 0x01112131;
201 cpu->id_isar4 = 0x00011142;
202 cpu->id_isar5 = 0x00011121;
203 cpu->id_isar6 = 0;
204 cpu->id_aa64pfr0 = 0x00002222;
205 cpu->id_aa64dfr0 = 0x10305106;
206 cpu->id_aa64isar0 = 0x00011120;
207 cpu->id_aa64mmfr0 = 0x00001122;
208 cpu->dbgdidr = 0x3516d000;
209 cpu->clidr = 0x0a200023;
210 cpu->ccsidr[0] = 0x700fe01a;
211 cpu->ccsidr[1] = 0x201fe00a;
212 cpu->ccsidr[2] = 0x707fe07a;
213 cpu->dcz_blocksize = 4;
214 cpu->gic_num_lrs = 4;
215 cpu->gic_vpribits = 5;
216 cpu->gic_vprebits = 5;
217 define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
218}
219
220
221
222
223
224
225static void aarch64_max_initfn(Object *obj)
226{
227 ARMCPU *cpu = ARM_CPU(obj);
228
229 if (kvm_enabled()) {
230 kvm_arm_set_cpu_features_from_host(cpu);
231 } else {
232 aarch64_a57_initfn(obj);
233#ifdef CONFIG_USER_ONLY
234
235
236
237
238
239
240 set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
241 set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
242 set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
243 set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
244 set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS);
245 set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
246 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
247 set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
248 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
249 set_feature(&cpu->env, ARM_FEATURE_SVE);
250
251
252
253 cpu->ctr = 0x80038003;
254 cpu->dcz_blocksize = 7;
255#endif
256 }
257}
258
259typedef struct ARMCPUInfo {
260 const char *name;
261 void (*initfn)(Object *obj);
262 void (*class_init)(ObjectClass *oc, void *data);
263} ARMCPUInfo;
264
265static const ARMCPUInfo aarch64_cpus[] = {
266 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
267 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
268 { .name = "max", .initfn = aarch64_max_initfn },
269 { .name = NULL }
270};
271
272static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
273{
274 ARMCPU *cpu = ARM_CPU(obj);
275
276 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
277}
278
279static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
280{
281 ARMCPU *cpu = ARM_CPU(obj);
282
283
284
285
286
287 if (!kvm_enabled()) {
288 error_setg(errp, "'aarch64' feature cannot be disabled "
289 "unless KVM is enabled");
290 return;
291 }
292
293 if (value == false) {
294 unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
295 } else {
296 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
297 }
298}
299
300static void aarch64_cpu_initfn(Object *obj)
301{
302 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
303 aarch64_cpu_set_aarch64, NULL);
304 object_property_set_description(obj, "aarch64",
305 "Set on/off to enable/disable aarch64 "
306 "execution state ",
307 NULL);
308}
309
310static void aarch64_cpu_finalizefn(Object *obj)
311{
312}
313
314static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
315{
316 ARMCPU *cpu = ARM_CPU(cs);
317
318
319
320
321 if (is_a64(&cpu->env)) {
322 cpu->env.pc = value;
323 } else {
324 cpu->env.regs[15] = value;
325 }
326}
327
328static gchar *aarch64_gdb_arch_name(CPUState *cs)
329{
330 return g_strdup("aarch64");
331}
332
333static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
334{
335 CPUClass *cc = CPU_CLASS(oc);
336
337 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
338 cc->set_pc = aarch64_cpu_set_pc;
339 cc->gdb_read_register = aarch64_cpu_gdb_read_register;
340 cc->gdb_write_register = aarch64_cpu_gdb_write_register;
341 cc->gdb_num_core_regs = 34;
342 cc->gdb_core_xml_file = "aarch64-core.xml";
343 cc->gdb_arch_name = aarch64_gdb_arch_name;
344}
345
346static void aarch64_cpu_register(const ARMCPUInfo *info)
347{
348 TypeInfo type_info = {
349 .parent = TYPE_AARCH64_CPU,
350 .instance_size = sizeof(ARMCPU),
351 .instance_init = info->initfn,
352 .class_size = sizeof(ARMCPUClass),
353 .class_init = info->class_init,
354 };
355
356 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
357 type_register(&type_info);
358 g_free((void *)type_info.name);
359}
360
361static const TypeInfo aarch64_cpu_type_info = {
362 .name = TYPE_AARCH64_CPU,
363 .parent = TYPE_ARM_CPU,
364 .instance_size = sizeof(ARMCPU),
365 .instance_init = aarch64_cpu_initfn,
366 .instance_finalize = aarch64_cpu_finalizefn,
367 .abstract = true,
368 .class_size = sizeof(AArch64CPUClass),
369 .class_init = aarch64_cpu_class_init,
370};
371
372static void aarch64_cpu_register_types(void)
373{
374 const ARMCPUInfo *info = aarch64_cpus;
375
376 type_register_static(&aarch64_cpu_type_info);
377
378 while (info->name) {
379 aarch64_cpu_register(info);
380 info++;
381 }
382}
383
384type_init(aarch64_cpu_register_types)
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
403{
404 int i, j;
405 uint64_t pmask;
406
407 assert(vq >= 1 && vq <= ARM_MAX_VQ);
408
409
410 for (i = 0; i < 32; i++) {
411 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
412 }
413
414
415 pmask = 0;
416 if (vq & 3) {
417 pmask = ~(-1ULL << (16 * (vq & 3)));
418 }
419 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
420 for (i = 0; i < 17; ++i) {
421 env->vfp.pregs[i].p[j] &= pmask;
422 }
423 pmask = 0;
424 }
425}
426