1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
22
23#include "qemu-common.h"
24#include "qemu/int128.h"
25
26
27
28#if defined (TARGET_PPC64)
29
30#define TARGET_LONG_BITS 64
31#define TARGET_PAGE_BITS 12
32
33#define TCG_GUEST_DEFAULT_MO 0
34
35
36
37
38#define TARGET_PHYS_ADDR_SPACE_BITS 62
39
40
41
42
43#ifdef TARGET_ABI32
44# define TARGET_VIRT_ADDR_SPACE_BITS 32
45#else
46# define TARGET_VIRT_ADDR_SPACE_BITS 64
47#endif
48
49#define TARGET_PAGE_BITS_64K 16
50#define TARGET_PAGE_BITS_16M 24
51
52#else
53
54#define TARGET_LONG_BITS 32
55
56#if defined(TARGET_PPCEMB)
57
58
59#if defined(CONFIG_USER_ONLY)
60
61
62
63#define TARGET_PAGE_BITS 12
64#else
65
66#define TARGET_PAGE_BITS 10
67#endif
68#else
69
70#define TARGET_PAGE_BITS 12
71#endif
72
73#define TARGET_PHYS_ADDR_SPACE_BITS 36
74#define TARGET_VIRT_ADDR_SPACE_BITS 32
75
76#endif
77
78#define CPUArchState struct CPUPPCState
79
80#include "exec/cpu-defs.h"
81#include "cpu-qom.h"
82
83#if defined (TARGET_PPC64)
84#define PPC_ELF_MACHINE EM_PPC64
85#else
86#define PPC_ELF_MACHINE EM_PPC
87#endif
88
89#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
90#define PPC_BIT32(bit) (0x80000000UL >> (bit))
91#define PPC_BIT8(bit) (0x80UL >> (bit))
92#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
93#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
94 PPC_BIT32(bs))
95#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
96
97#if HOST_LONG_BITS == 32
98# define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
99#elif HOST_LONG_BITS == 64
100# define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
101#else
102# error Unknown sizeof long
103#endif
104
105#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
106#define SETFIELD(m, v, val) \
107 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
108
109
110
111enum {
112 POWERPC_EXCP_NONE = -1,
113
114 POWERPC_EXCP_CRITICAL = 0,
115 POWERPC_EXCP_MCHECK = 1,
116 POWERPC_EXCP_DSI = 2,
117 POWERPC_EXCP_ISI = 3,
118 POWERPC_EXCP_EXTERNAL = 4,
119 POWERPC_EXCP_ALIGN = 5,
120 POWERPC_EXCP_PROGRAM = 6,
121 POWERPC_EXCP_FPU = 7,
122 POWERPC_EXCP_SYSCALL = 8,
123 POWERPC_EXCP_APU = 9,
124 POWERPC_EXCP_DECR = 10,
125 POWERPC_EXCP_FIT = 11,
126 POWERPC_EXCP_WDT = 12,
127 POWERPC_EXCP_DTLB = 13,
128 POWERPC_EXCP_ITLB = 14,
129 POWERPC_EXCP_DEBUG = 15,
130
131 POWERPC_EXCP_SPEU = 32,
132 POWERPC_EXCP_EFPDI = 33,
133 POWERPC_EXCP_EFPRI = 34,
134 POWERPC_EXCP_EPERFM = 35,
135 POWERPC_EXCP_DOORI = 36,
136 POWERPC_EXCP_DOORCI = 37,
137 POWERPC_EXCP_GDOORI = 38,
138 POWERPC_EXCP_GDOORCI = 39,
139 POWERPC_EXCP_HYPPRIV = 41,
140
141
142 POWERPC_EXCP_RESET = 64,
143 POWERPC_EXCP_DSEG = 65,
144 POWERPC_EXCP_ISEG = 66,
145 POWERPC_EXCP_HDECR = 67,
146 POWERPC_EXCP_TRACE = 68,
147 POWERPC_EXCP_HDSI = 69,
148 POWERPC_EXCP_HISI = 70,
149 POWERPC_EXCP_HDSEG = 71,
150 POWERPC_EXCP_HISEG = 72,
151 POWERPC_EXCP_VPU = 73,
152
153 POWERPC_EXCP_PIT = 74,
154
155 POWERPC_EXCP_IO = 75,
156 POWERPC_EXCP_RUNM = 76,
157
158 POWERPC_EXCP_EMUL = 77,
159
160 POWERPC_EXCP_IFTLB = 78,
161 POWERPC_EXCP_DLTLB = 79,
162 POWERPC_EXCP_DSTLB = 80,
163
164 POWERPC_EXCP_FPA = 81,
165 POWERPC_EXCP_DABR = 82,
166 POWERPC_EXCP_IABR = 83,
167 POWERPC_EXCP_SMI = 84,
168 POWERPC_EXCP_PERFM = 85,
169
170 POWERPC_EXCP_THERM = 86,
171
172 POWERPC_EXCP_VPUA = 87,
173
174 POWERPC_EXCP_SOFTP = 88,
175 POWERPC_EXCP_MAINT = 89,
176
177 POWERPC_EXCP_MEXTBR = 90,
178 POWERPC_EXCP_NMEXTBR = 91,
179 POWERPC_EXCP_ITLBE = 92,
180 POWERPC_EXCP_DTLBE = 93,
181
182 POWERPC_EXCP_VSXU = 94,
183 POWERPC_EXCP_FU = 95,
184
185 POWERPC_EXCP_HV_EMU = 96,
186 POWERPC_EXCP_HV_MAINT = 97,
187 POWERPC_EXCP_HV_FU = 98,
188
189 POWERPC_EXCP_SDOOR = 99,
190 POWERPC_EXCP_SDOOR_HV = 100,
191
192 POWERPC_EXCP_NB = 101,
193
194 POWERPC_EXCP_STOP = 0x200,
195 POWERPC_EXCP_BRANCH = 0x201,
196
197 POWERPC_EXCP_SYNC = 0x202,
198 POWERPC_EXCP_SYSCALL_USER = 0x203,
199};
200
201
202enum {
203
204 POWERPC_EXCP_ALIGN_FP = 0x01,
205 POWERPC_EXCP_ALIGN_LST = 0x02,
206 POWERPC_EXCP_ALIGN_LE = 0x03,
207 POWERPC_EXCP_ALIGN_PROT = 0x04,
208 POWERPC_EXCP_ALIGN_BAT = 0x05,
209 POWERPC_EXCP_ALIGN_CACHE = 0x06,
210
211
212 POWERPC_EXCP_FP = 0x10,
213 POWERPC_EXCP_FP_OX = 0x01,
214 POWERPC_EXCP_FP_UX = 0x02,
215 POWERPC_EXCP_FP_ZX = 0x03,
216 POWERPC_EXCP_FP_XX = 0x04,
217 POWERPC_EXCP_FP_VXSNAN = 0x05,
218 POWERPC_EXCP_FP_VXISI = 0x06,
219 POWERPC_EXCP_FP_VXIDI = 0x07,
220 POWERPC_EXCP_FP_VXZDZ = 0x08,
221 POWERPC_EXCP_FP_VXIMZ = 0x09,
222 POWERPC_EXCP_FP_VXVC = 0x0A,
223 POWERPC_EXCP_FP_VXSOFT = 0x0B,
224 POWERPC_EXCP_FP_VXSQRT = 0x0C,
225 POWERPC_EXCP_FP_VXCVI = 0x0D,
226
227 POWERPC_EXCP_INVAL = 0x20,
228 POWERPC_EXCP_INVAL_INVAL = 0x01,
229 POWERPC_EXCP_INVAL_LSWX = 0x02,
230 POWERPC_EXCP_INVAL_SPR = 0x03,
231 POWERPC_EXCP_INVAL_FP = 0x04,
232
233 POWERPC_EXCP_PRIV = 0x30,
234 POWERPC_EXCP_PRIV_OPC = 0x01,
235 POWERPC_EXCP_PRIV_REG = 0x02,
236
237 POWERPC_EXCP_TRAP = 0x40,
238};
239
240#define PPC_INPUT(env) (env->bus_model)
241
242
243typedef struct opc_handler_t opc_handler_t;
244
245
246
247typedef struct DisasContext DisasContext;
248typedef struct ppc_spr_t ppc_spr_t;
249typedef union ppc_avr_t ppc_avr_t;
250typedef union ppc_tlb_t ppc_tlb_t;
251typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
252
253
254struct ppc_spr_t {
255 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
256 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
257#if !defined(CONFIG_USER_ONLY)
258 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
259 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
260 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
261 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
262#endif
263 const char *name;
264 target_ulong default_value;
265#ifdef CONFIG_KVM
266
267
268
269 uint64_t one_reg_id;
270#endif
271};
272
273
274union ppc_avr_t {
275 float32 f[4];
276 uint8_t u8[16];
277 uint16_t u16[8];
278 uint32_t u32[4];
279 int8_t s8[16];
280 int16_t s16[8];
281 int32_t s32[4];
282 uint64_t u64[2];
283 int64_t s64[2];
284#ifdef CONFIG_INT128
285 __uint128_t u128;
286#endif
287 Int128 s128;
288};
289
290#if !defined(CONFIG_USER_ONLY)
291
292typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
293struct ppc6xx_tlb_t {
294 target_ulong pte0;
295 target_ulong pte1;
296 target_ulong EPN;
297};
298
299typedef struct ppcemb_tlb_t ppcemb_tlb_t;
300struct ppcemb_tlb_t {
301 uint64_t RPN;
302 target_ulong EPN;
303 target_ulong PID;
304 target_ulong size;
305 uint32_t prot;
306 uint32_t attr;
307};
308
309typedef struct ppcmas_tlb_t {
310 uint32_t mas8;
311 uint32_t mas1;
312 uint64_t mas2;
313 uint64_t mas7_3;
314} ppcmas_tlb_t;
315
316union ppc_tlb_t {
317 ppc6xx_tlb_t *tlb6;
318 ppcemb_tlb_t *tlbe;
319 ppcmas_tlb_t *tlbm;
320};
321
322
323#define TLB_NONE 0
324#define TLB_6XX 1
325#define TLB_EMB 2
326#define TLB_MAS 3
327#endif
328
329typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
330
331typedef struct ppc_slb_t ppc_slb_t;
332struct ppc_slb_t {
333 uint64_t esid;
334 uint64_t vsid;
335 const PPCHash64SegmentPageSizes *sps;
336};
337
338#define MAX_SLB_ENTRIES 64
339#define SEGMENT_SHIFT_256M 28
340#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
341
342#define SEGMENT_SHIFT_1T 40
343#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
344
345
346
347
348#define MSR_SF 63
349#define MSR_TAG 62
350#define MSR_ISF 61
351#define MSR_SHV 60
352#define MSR_TS0 34
353#define MSR_TS1 33
354#define MSR_TM 32
355#define MSR_CM 31
356#define MSR_ICM 30
357#define MSR_THV 29
358#define MSR_GS 28
359#define MSR_UCLE 26
360#define MSR_VR 25
361#define MSR_SPE 25
362#define MSR_AP 23
363#define MSR_VSX 23
364#define MSR_SA 22
365#define MSR_KEY 19
366#define MSR_POW 18
367#define MSR_TGPR 17
368#define MSR_CE 17
369#define MSR_ILE 16
370#define MSR_EE 15
371#define MSR_PR 14
372#define MSR_FP 13
373#define MSR_ME 12
374#define MSR_FE0 11
375#define MSR_SE 10
376#define MSR_DWE 10
377#define MSR_UBLE 10
378#define MSR_BE 9
379#define MSR_DE 9
380#define MSR_FE1 8
381#define MSR_AL 7
382#define MSR_EP 6
383#define MSR_IR 5
384#define MSR_DR 4
385#define MSR_IS 5
386#define MSR_DS 4
387#define MSR_PE 3
388#define MSR_PX 2
389#define MSR_PMM 2
390#define MSR_RI 1
391#define MSR_LE 0
392
393
394#define LPCR_VPM0 PPC_BIT(0)
395#define LPCR_VPM1 PPC_BIT(1)
396#define LPCR_ISL PPC_BIT(2)
397#define LPCR_KBV PPC_BIT(3)
398#define LPCR_DPFD_SHIFT (63 - 11)
399#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
400#define LPCR_VRMASD_SHIFT (63 - 16)
401#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
402
403#define LPCR_PECE_U_SHIFT (63 - 19)
404#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
405#define LPCR_HVEE PPC_BIT(17)
406#define LPCR_RMLS_SHIFT (63 - 37)
407#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
408#define LPCR_ILE PPC_BIT(38)
409#define LPCR_AIL_SHIFT (63 - 40)
410#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
411#define LPCR_UPRT PPC_BIT(41)
412#define LPCR_EVIRT PPC_BIT(42)
413#define LPCR_ONL PPC_BIT(45)
414#define LPCR_LD PPC_BIT(46)
415#define LPCR_P7_PECE0 PPC_BIT(49)
416#define LPCR_P7_PECE1 PPC_BIT(50)
417#define LPCR_P7_PECE2 PPC_BIT(51)
418#define LPCR_P8_PECE0 PPC_BIT(47)
419#define LPCR_P8_PECE1 PPC_BIT(48)
420#define LPCR_P8_PECE2 PPC_BIT(49)
421#define LPCR_P8_PECE3 PPC_BIT(50)
422#define LPCR_P8_PECE4 PPC_BIT(51)
423
424#define LPCR_PECE_L_SHIFT (63 - 51)
425#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
426#define LPCR_PDEE PPC_BIT(47)
427#define LPCR_HDEE PPC_BIT(48)
428#define LPCR_EEE PPC_BIT(49)
429#define LPCR_DEE PPC_BIT(50)
430#define LPCR_OEE PPC_BIT(51)
431#define LPCR_MER PPC_BIT(52)
432#define LPCR_GTSE PPC_BIT(53)
433#define LPCR_TC PPC_BIT(54)
434#define LPCR_HEIC PPC_BIT(59)
435#define LPCR_LPES0 PPC_BIT(60)
436#define LPCR_LPES1 PPC_BIT(61)
437#define LPCR_RMI PPC_BIT(62)
438#define LPCR_HVICE PPC_BIT(62)
439#define LPCR_HDICE PPC_BIT(63)
440
441#define msr_sf ((env->msr >> MSR_SF) & 1)
442#define msr_isf ((env->msr >> MSR_ISF) & 1)
443#define msr_shv ((env->msr >> MSR_SHV) & 1)
444#define msr_cm ((env->msr >> MSR_CM) & 1)
445#define msr_icm ((env->msr >> MSR_ICM) & 1)
446#define msr_thv ((env->msr >> MSR_THV) & 1)
447#define msr_gs ((env->msr >> MSR_GS) & 1)
448#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
449#define msr_vr ((env->msr >> MSR_VR) & 1)
450#define msr_spe ((env->msr >> MSR_SPE) & 1)
451#define msr_ap ((env->msr >> MSR_AP) & 1)
452#define msr_vsx ((env->msr >> MSR_VSX) & 1)
453#define msr_sa ((env->msr >> MSR_SA) & 1)
454#define msr_key ((env->msr >> MSR_KEY) & 1)
455#define msr_pow ((env->msr >> MSR_POW) & 1)
456#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
457#define msr_ce ((env->msr >> MSR_CE) & 1)
458#define msr_ile ((env->msr >> MSR_ILE) & 1)
459#define msr_ee ((env->msr >> MSR_EE) & 1)
460#define msr_pr ((env->msr >> MSR_PR) & 1)
461#define msr_fp ((env->msr >> MSR_FP) & 1)
462#define msr_me ((env->msr >> MSR_ME) & 1)
463#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
464#define msr_se ((env->msr >> MSR_SE) & 1)
465#define msr_dwe ((env->msr >> MSR_DWE) & 1)
466#define msr_uble ((env->msr >> MSR_UBLE) & 1)
467#define msr_be ((env->msr >> MSR_BE) & 1)
468#define msr_de ((env->msr >> MSR_DE) & 1)
469#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
470#define msr_al ((env->msr >> MSR_AL) & 1)
471#define msr_ep ((env->msr >> MSR_EP) & 1)
472#define msr_ir ((env->msr >> MSR_IR) & 1)
473#define msr_dr ((env->msr >> MSR_DR) & 1)
474#define msr_is ((env->msr >> MSR_IS) & 1)
475#define msr_ds ((env->msr >> MSR_DS) & 1)
476#define msr_pe ((env->msr >> MSR_PE) & 1)
477#define msr_px ((env->msr >> MSR_PX) & 1)
478#define msr_pmm ((env->msr >> MSR_PMM) & 1)
479#define msr_ri ((env->msr >> MSR_RI) & 1)
480#define msr_le ((env->msr >> MSR_LE) & 1)
481#define msr_ts ((env->msr >> MSR_TS1) & 3)
482#define msr_tm ((env->msr >> MSR_TM) & 1)
483
484
485#if defined(TARGET_PPC64)
486#define MSR_HVB (1ULL << MSR_SHV)
487#define msr_hv msr_shv
488#else
489#if defined(PPC_EMULATE_32BITS_HYPV)
490#define MSR_HVB (1ULL << MSR_THV)
491#define msr_hv msr_thv
492#else
493#define MSR_HVB (0ULL)
494#define msr_hv (0)
495#endif
496#endif
497
498
499#define DSISR_NOPTE 0x40000000
500
501#define DSISR_PROTFAULT 0x08000000
502#define DSISR_ISSTORE 0x02000000
503
504#define DSISR_AMR 0x00200000
505
506#define DSISR_R_BADCONFIG 0x00080000
507
508
509
510#define SRR1_NOPTE DSISR_NOPTE
511
512#define SRR1_NOEXEC_GUARD 0x10000000
513#define SRR1_PROTFAULT DSISR_PROTFAULT
514#define SRR1_IAMR DSISR_AMR
515
516
517#define FSCR_EBB (63 - 56)
518#define FSCR_TAR (63 - 55)
519
520#define FSCR_IC_MASK (0xFFULL)
521#define FSCR_IC_POS (63 - 7)
522#define FSCR_IC_DSCR_SPR3 2
523#define FSCR_IC_PMU 3
524#define FSCR_IC_BHRB 4
525#define FSCR_IC_TM 5
526#define FSCR_IC_EBB 7
527#define FSCR_IC_TAR 8
528
529
530#define ESR_PIL PPC_BIT(36)
531#define ESR_PPR PPC_BIT(37)
532#define ESR_PTR PPC_BIT(38)
533#define ESR_FP PPC_BIT(39)
534#define ESR_ST PPC_BIT(40)
535#define ESR_AP PPC_BIT(44)
536#define ESR_PUO PPC_BIT(45)
537#define ESR_BO PPC_BIT(46)
538#define ESR_PIE PPC_BIT(47)
539#define ESR_DATA PPC_BIT(53)
540#define ESR_TLBI PPC_BIT(54)
541#define ESR_PT PPC_BIT(55)
542#define ESR_SPV PPC_BIT(56)
543#define ESR_EPID PPC_BIT(57)
544#define ESR_VLEMI PPC_BIT(58)
545#define ESR_MIF PPC_BIT(62)
546
547
548#define TEXASR_FAILURE_PERSISTENT (63 - 7)
549#define TEXASR_DISALLOWED (63 - 8)
550#define TEXASR_NESTING_OVERFLOW (63 - 9)
551#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
552#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
553#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
554#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
555#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
556#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
557#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
558#define TEXASR_ABORT (63 - 31)
559#define TEXASR_SUSPENDED (63 - 32)
560#define TEXASR_PRIVILEGE_HV (63 - 34)
561#define TEXASR_PRIVILEGE_PR (63 - 35)
562#define TEXASR_FAILURE_SUMMARY (63 - 36)
563#define TEXASR_TFIAR_EXACT (63 - 37)
564#define TEXASR_ROT (63 - 38)
565#define TEXASR_TRANSACTION_LEVEL (63 - 52)
566
567enum {
568 POWERPC_FLAG_NONE = 0x00000000,
569
570 POWERPC_FLAG_SPE = 0x00000001,
571 POWERPC_FLAG_VRE = 0x00000002,
572
573 POWERPC_FLAG_TGPR = 0x00000004,
574 POWERPC_FLAG_CE = 0x00000008,
575
576 POWERPC_FLAG_SE = 0x00000010,
577 POWERPC_FLAG_DWE = 0x00000020,
578 POWERPC_FLAG_UBLE = 0x00000040,
579
580 POWERPC_FLAG_BE = 0x00000080,
581 POWERPC_FLAG_DE = 0x00000100,
582
583 POWERPC_FLAG_PX = 0x00000200,
584 POWERPC_FLAG_PMM = 0x00000400,
585
586
587 POWERPC_FLAG_RTC_CLK = 0x00010000,
588 POWERPC_FLAG_BUS_CLK = 0x00020000,
589
590 POWERPC_FLAG_CFAR = 0x00040000,
591
592 POWERPC_FLAG_VSX = 0x00080000,
593
594 POWERPC_FLAG_TM = 0x00100000,
595};
596
597
598
599#define FPSCR_FX 31
600#define FPSCR_FEX 30
601#define FPSCR_VX 29
602#define FPSCR_OX 28
603#define FPSCR_UX 27
604#define FPSCR_ZX 26
605#define FPSCR_XX 25
606#define FPSCR_VXSNAN 24
607#define FPSCR_VXISI 23
608#define FPSCR_VXIDI 22
609#define FPSCR_VXZDZ 21
610#define FPSCR_VXIMZ 20
611#define FPSCR_VXVC 19
612#define FPSCR_FR 18
613#define FPSCR_FI 17
614#define FPSCR_C 16
615#define FPSCR_FL 15
616#define FPSCR_FG 14
617#define FPSCR_FE 13
618#define FPSCR_FU 12
619#define FPSCR_FPCC 12
620#define FPSCR_FPRF 12
621#define FPSCR_VXSOFT 10
622#define FPSCR_VXSQRT 9
623#define FPSCR_VXCVI 8
624#define FPSCR_VE 7
625#define FPSCR_OE 6
626#define FPSCR_UE 5
627#define FPSCR_ZE 4
628#define FPSCR_XE 3
629#define FPSCR_NI 2
630#define FPSCR_RN1 1
631#define FPSCR_RN 0
632#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
633#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
634#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
635#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
636#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
637#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
638#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
639#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
640#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
641#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
642#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
643#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
644#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
645#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
646#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
647#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
648#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
649#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
650#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
651#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
652#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
653#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
654#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
655
656#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
657 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
658 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
659 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
660 (1 << FPSCR_VXCVI)))
661
662#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
663
664#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
665 0x1F)
666
667#define FP_FX (1ull << FPSCR_FX)
668#define FP_FEX (1ull << FPSCR_FEX)
669#define FP_VX (1ull << FPSCR_VX)
670#define FP_OX (1ull << FPSCR_OX)
671#define FP_UX (1ull << FPSCR_UX)
672#define FP_ZX (1ull << FPSCR_ZX)
673#define FP_XX (1ull << FPSCR_XX)
674#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
675#define FP_VXISI (1ull << FPSCR_VXISI)
676#define FP_VXIDI (1ull << FPSCR_VXIDI)
677#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
678#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
679#define FP_VXVC (1ull << FPSCR_VXVC)
680#define FP_FR (1ull << FSPCR_FR)
681#define FP_FI (1ull << FPSCR_FI)
682#define FP_C (1ull << FPSCR_C)
683#define FP_FL (1ull << FPSCR_FL)
684#define FP_FG (1ull << FPSCR_FG)
685#define FP_FE (1ull << FPSCR_FE)
686#define FP_FU (1ull << FPSCR_FU)
687#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
688#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
689#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
690#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
691#define FP_VXCVI (1ull << FPSCR_VXCVI)
692#define FP_VE (1ull << FPSCR_VE)
693#define FP_OE (1ull << FPSCR_OE)
694#define FP_UE (1ull << FPSCR_UE)
695#define FP_ZE (1ull << FPSCR_ZE)
696#define FP_XE (1ull << FPSCR_XE)
697#define FP_NI (1ull << FPSCR_NI)
698#define FP_RN1 (1ull << FPSCR_RN1)
699#define FP_RN (1ull << FPSCR_RN)
700
701
702#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
703 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
704 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
705 FP_VXSQRT | FP_VXCVI)
706
707
708
709#define VSCR_NJ 16
710#define VSCR_SAT 0
711#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
712#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
713
714
715
716
717#define MAS0_NV_SHIFT 0
718#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
719
720#define MAS0_WQ_SHIFT 12
721#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
722
723#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
724
725#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
726
727#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
728
729#define MAS0_HES_SHIFT 14
730#define MAS0_HES (1 << MAS0_HES_SHIFT)
731
732#define MAS0_ESEL_SHIFT 16
733#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
734
735#define MAS0_TLBSEL_SHIFT 28
736#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
737#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
738#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
739#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
740#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
741
742#define MAS0_ATSEL_SHIFT 31
743#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
744#define MAS0_ATSEL_TLB 0
745#define MAS0_ATSEL_LRAT MAS0_ATSEL
746
747#define MAS1_TSIZE_SHIFT 7
748#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
749
750#define MAS1_TS_SHIFT 12
751#define MAS1_TS (1 << MAS1_TS_SHIFT)
752
753#define MAS1_IND_SHIFT 13
754#define MAS1_IND (1 << MAS1_IND_SHIFT)
755
756#define MAS1_TID_SHIFT 16
757#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
758
759#define MAS1_IPROT_SHIFT 30
760#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
761
762#define MAS1_VALID_SHIFT 31
763#define MAS1_VALID 0x80000000
764
765#define MAS2_EPN_SHIFT 12
766#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
767
768#define MAS2_ACM_SHIFT 6
769#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
770
771#define MAS2_VLE_SHIFT 5
772#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
773
774#define MAS2_W_SHIFT 4
775#define MAS2_W (1 << MAS2_W_SHIFT)
776
777#define MAS2_I_SHIFT 3
778#define MAS2_I (1 << MAS2_I_SHIFT)
779
780#define MAS2_M_SHIFT 2
781#define MAS2_M (1 << MAS2_M_SHIFT)
782
783#define MAS2_G_SHIFT 1
784#define MAS2_G (1 << MAS2_G_SHIFT)
785
786#define MAS2_E_SHIFT 0
787#define MAS2_E (1 << MAS2_E_SHIFT)
788
789#define MAS3_RPN_SHIFT 12
790#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
791
792#define MAS3_U0 0x00000200
793#define MAS3_U1 0x00000100
794#define MAS3_U2 0x00000080
795#define MAS3_U3 0x00000040
796#define MAS3_UX 0x00000020
797#define MAS3_SX 0x00000010
798#define MAS3_UW 0x00000008
799#define MAS3_SW 0x00000004
800#define MAS3_UR 0x00000002
801#define MAS3_SR 0x00000001
802#define MAS3_SPSIZE_SHIFT 1
803#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
804
805#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
806#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
807#define MAS4_TIDSELD_MASK 0x00030000
808#define MAS4_TIDSELD_PID0 0x00000000
809#define MAS4_TIDSELD_PID1 0x00010000
810#define MAS4_TIDSELD_PID2 0x00020000
811#define MAS4_TIDSELD_PIDZ 0x00030000
812#define MAS4_INDD 0x00008000
813#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
814#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
815#define MAS4_ACMD 0x00000040
816#define MAS4_VLED 0x00000020
817#define MAS4_WD 0x00000010
818#define MAS4_ID 0x00000008
819#define MAS4_MD 0x00000004
820#define MAS4_GD 0x00000002
821#define MAS4_ED 0x00000001
822#define MAS4_WIMGED_MASK 0x0000001f
823#define MAS4_WIMGED_SHIFT 0
824
825#define MAS5_SGS 0x80000000
826#define MAS5_SLPID_MASK 0x00000fff
827
828#define MAS6_SPID0 0x3fff0000
829#define MAS6_SPID1 0x00007ffe
830#define MAS6_ISIZE(x) MAS1_TSIZE(x)
831#define MAS6_SAS 0x00000001
832#define MAS6_SPID MAS6_SPID0
833#define MAS6_SIND 0x00000002
834#define MAS6_SIND_SHIFT 1
835#define MAS6_SPID_MASK 0x3fff0000
836#define MAS6_SPID_SHIFT 16
837#define MAS6_ISIZE_MASK 0x00000f80
838#define MAS6_ISIZE_SHIFT 7
839
840#define MAS7_RPN 0xffffffff
841
842#define MAS8_TGS 0x80000000
843#define MAS8_VF 0x40000000
844#define MAS8_TLBPID 0x00000fff
845
846
847#define MMUCFG_MAVN 0x00000003
848#define MMUCFG_MAVN_V1 0x00000000
849#define MMUCFG_MAVN_V2 0x00000001
850#define MMUCFG_NTLBS 0x0000000c
851#define MMUCFG_PIDSIZE 0x000007c0
852#define MMUCFG_TWC 0x00008000
853#define MMUCFG_LRAT 0x00010000
854#define MMUCFG_RASIZE 0x00fe0000
855#define MMUCFG_LPIDSIZE 0x0f000000
856
857
858#define MMUCSR0_TLB1FI 0x00000002
859#define MMUCSR0_TLB0FI 0x00000004
860#define MMUCSR0_TLB2FI 0x00000040
861#define MMUCSR0_TLB3FI 0x00000020
862#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
863 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
864#define MMUCSR0_TLB0PS 0x00000780
865#define MMUCSR0_TLB1PS 0x00007800
866#define MMUCSR0_TLB2PS 0x00078000
867#define MMUCSR0_TLB3PS 0x00780000
868
869
870#define TLBnCFG_N_ENTRY 0x00000fff
871#define TLBnCFG_HES 0x00002000
872#define TLBnCFG_AVAIL 0x00004000
873#define TLBnCFG_IPROT 0x00008000
874#define TLBnCFG_GTWE 0x00010000
875#define TLBnCFG_IND 0x00020000
876#define TLBnCFG_PT 0x00040000
877#define TLBnCFG_MINSIZE 0x00f00000
878#define TLBnCFG_MINSIZE_SHIFT 20
879#define TLBnCFG_MAXSIZE 0x000f0000
880#define TLBnCFG_MAXSIZE_SHIFT 16
881#define TLBnCFG_ASSOC 0xff000000
882#define TLBnCFG_ASSOC_SHIFT 24
883
884
885#define TLBnPS_4K 0x00000004
886#define TLBnPS_8K 0x00000008
887#define TLBnPS_16K 0x00000010
888#define TLBnPS_32K 0x00000020
889#define TLBnPS_64K 0x00000040
890#define TLBnPS_128K 0x00000080
891#define TLBnPS_256K 0x00000100
892#define TLBnPS_512K 0x00000200
893#define TLBnPS_1M 0x00000400
894#define TLBnPS_2M 0x00000800
895#define TLBnPS_4M 0x00001000
896#define TLBnPS_8M 0x00002000
897#define TLBnPS_16M 0x00004000
898#define TLBnPS_32M 0x00008000
899#define TLBnPS_64M 0x00010000
900#define TLBnPS_128M 0x00020000
901#define TLBnPS_256M 0x00040000
902#define TLBnPS_512M 0x00080000
903#define TLBnPS_1G 0x00100000
904#define TLBnPS_2G 0x00200000
905#define TLBnPS_4G 0x00400000
906#define TLBnPS_8G 0x00800000
907#define TLBnPS_16G 0x01000000
908#define TLBnPS_32G 0x02000000
909#define TLBnPS_64G 0x04000000
910#define TLBnPS_128G 0x08000000
911#define TLBnPS_256G 0x10000000
912
913
914#define TLBILX_T_ALL 0
915#define TLBILX_T_TID 1
916#define TLBILX_T_FULLMATCH 3
917#define TLBILX_T_CLASS0 4
918#define TLBILX_T_CLASS1 5
919#define TLBILX_T_CLASS2 6
920#define TLBILX_T_CLASS3 7
921
922
923
924#define BOOKE206_FLUSH_TLB0 (1 << 0)
925#define BOOKE206_FLUSH_TLB1 (1 << 1)
926#define BOOKE206_FLUSH_TLB2 (1 << 2)
927#define BOOKE206_FLUSH_TLB3 (1 << 3)
928
929
930#define BOOKE206_MAX_TLBN 4
931
932
933
934
935#define DBELL_TYPE_SHIFT 27
936#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
937#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
938#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
939#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
940#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
941#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
942
943#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
944
945#define DBELL_BRDCAST PPC_BIT(37)
946#define DBELL_LPIDTAG_SHIFT 14
947#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
948#define DBELL_PIRTAG_MASK 0x3fff
949
950#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
951
952#define PPC_PAGE_SIZES_MAX_SZ 8
953
954struct ppc_radix_page_info {
955 uint32_t count;
956 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
957};
958
959
960
961#define NB_MMU_MODES 8
962
963#define PPC_CPU_OPCODES_LEN 0x40
964#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
965
966struct CPUPPCState {
967
968
969
970
971 target_ulong gpr[32];
972
973 target_ulong gprh[32];
974
975 target_ulong lr;
976
977 target_ulong ctr;
978
979 uint32_t crf[8];
980#if defined(TARGET_PPC64)
981
982 target_ulong cfar;
983#endif
984
985 target_ulong xer;
986 target_ulong so;
987 target_ulong ov;
988 target_ulong ca;
989 target_ulong ov32;
990 target_ulong ca32;
991
992 target_ulong reserve_addr;
993
994 target_ulong reserve_val;
995 target_ulong reserve_val2;
996
997
998
999 target_ulong msr;
1000
1001 target_ulong tgpr[4];
1002
1003
1004 float_status fp_status;
1005
1006 float64 fpr[32];
1007
1008 target_ulong fpscr;
1009
1010
1011 target_ulong nip;
1012
1013
1014 uint64_t retxh;
1015
1016 int access_type;
1017
1018
1019 CPU_COMMON
1020
1021
1022#if !defined(CONFIG_USER_ONLY)
1023#if defined(TARGET_PPC64)
1024
1025 ppc_slb_t slb[MAX_SLB_ENTRIES];
1026
1027#endif
1028
1029 target_ulong sr[32];
1030
1031 uint32_t nb_BATs;
1032 target_ulong DBAT[2][8];
1033 target_ulong IBAT[2][8];
1034
1035 int32_t nb_tlb;
1036 int tlb_per_way;
1037 int nb_ways;
1038 int last_way;
1039 int id_tlbs;
1040 int nb_pids;
1041 int tlb_type;
1042 ppc_tlb_t tlb;
1043
1044 target_ulong pb[4];
1045 bool tlb_dirty;
1046 bool kvm_sw_tlb;
1047 uint32_t tlb_need_flush;
1048#define TLB_NEED_LOCAL_FLUSH 0x1
1049#define TLB_NEED_GLOBAL_FLUSH 0x2
1050#endif
1051
1052
1053
1054 target_ulong spr[1024];
1055 ppc_spr_t spr_cb[1024];
1056
1057 ppc_avr_t avr[32];
1058 uint32_t vscr;
1059
1060 uint64_t vsr[32];
1061
1062 uint64_t spe_acc;
1063 uint32_t spe_fscr;
1064
1065
1066 float_status vec_status;
1067
1068
1069
1070 ppc_tb_t *tb_env;
1071
1072 ppc_dcr_t *dcr_env;
1073
1074 int dcache_line_size;
1075 int icache_line_size;
1076
1077
1078
1079 target_ulong msr_mask;
1080 powerpc_mmu_t mmu_model;
1081 powerpc_excp_t excp_model;
1082 powerpc_input_t bus_model;
1083 int bfd_mach;
1084 uint32_t flags;
1085 uint64_t insns_flags;
1086 uint64_t insns_flags2;
1087#if defined(TARGET_PPC64)
1088 ppc_slb_t vrma_slb;
1089 target_ulong rmls;
1090#endif
1091
1092 int error_code;
1093 uint32_t pending_interrupts;
1094#if !defined(CONFIG_USER_ONLY)
1095
1096
1097
1098 uint32_t irq_input_state;
1099 void **irq_inputs;
1100
1101 target_ulong excp_vectors[POWERPC_EXCP_NB];
1102 target_ulong excp_prefix;
1103 target_ulong ivor_mask;
1104 target_ulong ivpr_mask;
1105 target_ulong hreset_vector;
1106 hwaddr mpic_iack;
1107
1108 bool mpic_proxy;
1109
1110
1111
1112 bool has_hv_mode;
1113
1114
1115
1116
1117 bool in_pm_state;
1118#endif
1119
1120
1121
1122 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1123
1124
1125 target_ulong hflags;
1126 target_ulong hflags_nmsr;
1127 int immu_idx;
1128 int dmmu_idx;
1129
1130
1131 int (*check_pow)(CPUPPCState *env);
1132
1133#if !defined(CONFIG_USER_ONLY)
1134 void *load_info;
1135#endif
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145 uint8_t fit_period[4];
1146 uint8_t wdt_period[4];
1147
1148
1149 target_ulong tm_gpr[32];
1150 ppc_avr_t tm_vsr[64];
1151 uint64_t tm_cr;
1152 uint64_t tm_lr;
1153 uint64_t tm_ctr;
1154 uint64_t tm_fpscr;
1155 uint64_t tm_amr;
1156 uint64_t tm_ppr;
1157 uint64_t tm_vrsave;
1158 uint32_t tm_vscr;
1159 uint64_t tm_dscr;
1160 uint64_t tm_tar;
1161};
1162
1163#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1164do { \
1165 env->fit_period[0] = (a_); \
1166 env->fit_period[1] = (b_); \
1167 env->fit_period[2] = (c_); \
1168 env->fit_period[3] = (d_); \
1169 } while (0)
1170
1171#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1172do { \
1173 env->wdt_period[0] = (a_); \
1174 env->wdt_period[1] = (b_); \
1175 env->wdt_period[2] = (c_); \
1176 env->wdt_period[3] = (d_); \
1177 } while (0)
1178
1179typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1180typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190struct PowerPCCPU {
1191
1192 CPUState parent_obj;
1193
1194
1195 CPUPPCState env;
1196 int vcpu_id;
1197 uint32_t compat_pvr;
1198 PPCVirtualHypervisor *vhyp;
1199 Object *intc;
1200 void *machine_data;
1201 int32_t node_id;
1202 PPCHash64Options *hash64_opts;
1203
1204
1205 bool pre_2_8_migration;
1206 target_ulong mig_msr_mask;
1207 uint64_t mig_insns_flags;
1208 uint64_t mig_insns_flags2;
1209 uint32_t mig_nb_BATs;
1210 bool pre_2_10_migration;
1211 bool pre_3_0_migration;
1212 int32_t mig_slb_nr;
1213};
1214
1215static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1216{
1217 return container_of(env, PowerPCCPU, env);
1218}
1219
1220#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1221
1222#define ENV_OFFSET offsetof(PowerPCCPU, env)
1223
1224PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1225PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1226PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1227
1228struct PPCVirtualHypervisor {
1229 Object parent;
1230};
1231
1232struct PPCVirtualHypervisorClass {
1233 InterfaceClass parent;
1234 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1235 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1236 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1237 hwaddr ptex, int n);
1238 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1239 const ppc_hash_pte64_t *hptes,
1240 hwaddr ptex, int n);
1241 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1242 uint64_t pte0, uint64_t pte1);
1243 uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1244 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1245};
1246
1247#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1248#define PPC_VIRTUAL_HYPERVISOR(obj) \
1249 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1250#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1251 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1252 TYPE_PPC_VIRTUAL_HYPERVISOR)
1253#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1254 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1255 TYPE_PPC_VIRTUAL_HYPERVISOR)
1256
1257void ppc_cpu_do_interrupt(CPUState *cpu);
1258bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1259void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1260 int flags);
1261void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1262 fprintf_function cpu_fprintf, int flags);
1263hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1264int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1265int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1266int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1267int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1268int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1269 int cpuid, void *opaque);
1270int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1271 int cpuid, void *opaque);
1272#ifndef CONFIG_USER_ONLY
1273void ppc_cpu_do_system_reset(CPUState *cs);
1274extern const struct VMStateDescription vmstate_ppc_cpu;
1275#endif
1276
1277
1278void ppc_translate_init(void);
1279
1280
1281
1282int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1283 void *puc);
1284#if defined(CONFIG_USER_ONLY)
1285int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
1286 int mmu_idx);
1287#endif
1288
1289#if !defined(CONFIG_USER_ONLY)
1290void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1291void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1292#endif
1293void ppc_store_msr (CPUPPCState *env, target_ulong value);
1294
1295void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1296
1297
1298#ifndef NO_CPU_IO_DEFS
1299uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1300uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1301void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1302void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1303uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1304uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1305void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1306void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1307bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1308uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1309void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1310uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1311void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1312uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1313uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1314uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1315#if !defined(CONFIG_USER_ONLY)
1316void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1317void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1318target_ulong load_40x_pit (CPUPPCState *env);
1319void store_40x_pit (CPUPPCState *env, target_ulong val);
1320void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1321void store_40x_sler (CPUPPCState *env, uint32_t val);
1322void store_booke_tcr (CPUPPCState *env, target_ulong val);
1323void store_booke_tsr (CPUPPCState *env, target_ulong val);
1324void ppc_tlb_invalidate_all (CPUPPCState *env);
1325void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1326void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1327#endif
1328#endif
1329
1330void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1331
1332static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1333{
1334 uint64_t gprv;
1335
1336 gprv = env->gpr[gprn];
1337 if (env->flags & POWERPC_FLAG_SPE) {
1338
1339
1340
1341 gprv &= 0xFFFFFFFFULL;
1342 gprv |= (uint64_t)env->gprh[gprn] << 32;
1343 }
1344
1345 return gprv;
1346}
1347
1348
1349int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1350int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1351
1352#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1353#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1354#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1355
1356#define cpu_signal_handler cpu_ppc_signal_handler
1357#define cpu_list ppc_cpu_list
1358
1359
1360#define MMU_USER_IDX 0
1361static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1362{
1363 return ifetch ? env->immu_idx : env->dmmu_idx;
1364}
1365
1366
1367#if defined(TARGET_PPC64)
1368bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1369 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1370bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1371 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1372
1373void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1374
1375#if !defined(CONFIG_USER_ONLY)
1376void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1377#endif
1378int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1379void ppc_compat_add_property(Object *obj, const char *name,
1380 uint32_t *compat_pvr, const char *basedesc,
1381 Error **errp);
1382#endif
1383
1384#include "exec/cpu-all.h"
1385
1386
1387
1388#define CRF_LT_BIT 3
1389#define CRF_GT_BIT 2
1390#define CRF_EQ_BIT 1
1391#define CRF_SO_BIT 0
1392#define CRF_LT (1 << CRF_LT_BIT)
1393#define CRF_GT (1 << CRF_GT_BIT)
1394#define CRF_EQ (1 << CRF_EQ_BIT)
1395#define CRF_SO (1 << CRF_SO_BIT)
1396
1397#define CRF_CH (1 << CRF_LT_BIT)
1398#define CRF_CL (1 << CRF_GT_BIT)
1399#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1400#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1401
1402
1403#define XER_SO 31
1404#define XER_OV 30
1405#define XER_CA 29
1406#define XER_OV32 19
1407#define XER_CA32 18
1408#define XER_CMP 8
1409#define XER_BC 0
1410#define xer_so (env->so)
1411#define xer_ov (env->ov)
1412#define xer_ca (env->ca)
1413#define xer_ov32 (env->ov)
1414#define xer_ca32 (env->ca)
1415#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1416#define xer_bc ((env->xer >> XER_BC) & 0x7F)
1417
1418
1419#define SPR_MQ (0x000)
1420#define SPR_XER (0x001)
1421#define SPR_601_VRTCU (0x004)
1422#define SPR_601_VRTCL (0x005)
1423#define SPR_601_UDECR (0x006)
1424#define SPR_LR (0x008)
1425#define SPR_CTR (0x009)
1426#define SPR_UAMR (0x00D)
1427#define SPR_DSCR (0x011)
1428#define SPR_DSISR (0x012)
1429#define SPR_DAR (0x013)
1430#define SPR_601_RTCU (0x014)
1431#define SPR_601_RTCL (0x015)
1432#define SPR_DECR (0x016)
1433#define SPR_SDR1 (0x019)
1434#define SPR_SRR0 (0x01A)
1435#define SPR_SRR1 (0x01B)
1436#define SPR_CFAR (0x01C)
1437#define SPR_AMR (0x01D)
1438#define SPR_ACOP (0x01F)
1439#define SPR_BOOKE_PID (0x030)
1440#define SPR_BOOKS_PID (0x030)
1441#define SPR_BOOKE_DECAR (0x036)
1442#define SPR_BOOKE_CSRR0 (0x03A)
1443#define SPR_BOOKE_CSRR1 (0x03B)
1444#define SPR_BOOKE_DEAR (0x03D)
1445#define SPR_IAMR (0x03D)
1446#define SPR_BOOKE_ESR (0x03E)
1447#define SPR_BOOKE_IVPR (0x03F)
1448#define SPR_MPC_EIE (0x050)
1449#define SPR_MPC_EID (0x051)
1450#define SPR_MPC_NRI (0x052)
1451#define SPR_TFHAR (0x080)
1452#define SPR_TFIAR (0x081)
1453#define SPR_TEXASR (0x082)
1454#define SPR_TEXASRU (0x083)
1455#define SPR_UCTRL (0x088)
1456#define SPR_TIDR (0x090)
1457#define SPR_MPC_CMPA (0x090)
1458#define SPR_MPC_CMPB (0x091)
1459#define SPR_MPC_CMPC (0x092)
1460#define SPR_MPC_CMPD (0x093)
1461#define SPR_MPC_ECR (0x094)
1462#define SPR_MPC_DER (0x095)
1463#define SPR_MPC_COUNTA (0x096)
1464#define SPR_MPC_COUNTB (0x097)
1465#define SPR_CTRL (0x098)
1466#define SPR_MPC_CMPE (0x098)
1467#define SPR_MPC_CMPF (0x099)
1468#define SPR_FSCR (0x099)
1469#define SPR_MPC_CMPG (0x09A)
1470#define SPR_MPC_CMPH (0x09B)
1471#define SPR_MPC_LCTRL1 (0x09C)
1472#define SPR_MPC_LCTRL2 (0x09D)
1473#define SPR_UAMOR (0x09D)
1474#define SPR_MPC_ICTRL (0x09E)
1475#define SPR_MPC_BAR (0x09F)
1476#define SPR_PSPB (0x09F)
1477#define SPR_DAWR (0x0B4)
1478#define SPR_RPR (0x0BA)
1479#define SPR_CIABR (0x0BB)
1480#define SPR_DAWRX (0x0BC)
1481#define SPR_HFSCR (0x0BE)
1482#define SPR_VRSAVE (0x100)
1483#define SPR_USPRG0 (0x100)
1484#define SPR_USPRG1 (0x101)
1485#define SPR_USPRG2 (0x102)
1486#define SPR_USPRG3 (0x103)
1487#define SPR_USPRG4 (0x104)
1488#define SPR_USPRG5 (0x105)
1489#define SPR_USPRG6 (0x106)
1490#define SPR_USPRG7 (0x107)
1491#define SPR_VTBL (0x10C)
1492#define SPR_VTBU (0x10D)
1493#define SPR_SPRG0 (0x110)
1494#define SPR_SPRG1 (0x111)
1495#define SPR_SPRG2 (0x112)
1496#define SPR_SPRG3 (0x113)
1497#define SPR_SPRG4 (0x114)
1498#define SPR_SCOMC (0x114)
1499#define SPR_SPRG5 (0x115)
1500#define SPR_SCOMD (0x115)
1501#define SPR_SPRG6 (0x116)
1502#define SPR_SPRG7 (0x117)
1503#define SPR_ASR (0x118)
1504#define SPR_EAR (0x11A)
1505#define SPR_TBL (0x11C)
1506#define SPR_TBU (0x11D)
1507#define SPR_TBU40 (0x11E)
1508#define SPR_SVR (0x11E)
1509#define SPR_BOOKE_PIR (0x11E)
1510#define SPR_PVR (0x11F)
1511#define SPR_HSPRG0 (0x130)
1512#define SPR_BOOKE_DBSR (0x130)
1513#define SPR_HSPRG1 (0x131)
1514#define SPR_HDSISR (0x132)
1515#define SPR_HDAR (0x133)
1516#define SPR_BOOKE_EPCR (0x133)
1517#define SPR_SPURR (0x134)
1518#define SPR_BOOKE_DBCR0 (0x134)
1519#define SPR_IBCR (0x135)
1520#define SPR_PURR (0x135)
1521#define SPR_BOOKE_DBCR1 (0x135)
1522#define SPR_DBCR (0x136)
1523#define SPR_HDEC (0x136)
1524#define SPR_BOOKE_DBCR2 (0x136)
1525#define SPR_HIOR (0x137)
1526#define SPR_MBAR (0x137)
1527#define SPR_RMOR (0x138)
1528#define SPR_BOOKE_IAC1 (0x138)
1529#define SPR_HRMOR (0x139)
1530#define SPR_BOOKE_IAC2 (0x139)
1531#define SPR_HSRR0 (0x13A)
1532#define SPR_BOOKE_IAC3 (0x13A)
1533#define SPR_HSRR1 (0x13B)
1534#define SPR_BOOKE_IAC4 (0x13B)
1535#define SPR_BOOKE_DAC1 (0x13C)
1536#define SPR_MMCRH (0x13C)
1537#define SPR_DABR2 (0x13D)
1538#define SPR_BOOKE_DAC2 (0x13D)
1539#define SPR_TFMR (0x13D)
1540#define SPR_BOOKE_DVC1 (0x13E)
1541#define SPR_LPCR (0x13E)
1542#define SPR_BOOKE_DVC2 (0x13F)
1543#define SPR_LPIDR (0x13F)
1544#define SPR_BOOKE_TSR (0x150)
1545#define SPR_HMER (0x150)
1546#define SPR_HMEER (0x151)
1547#define SPR_PCR (0x152)
1548#define SPR_BOOKE_LPIDR (0x152)
1549#define SPR_BOOKE_TCR (0x154)
1550#define SPR_BOOKE_TLB0PS (0x158)
1551#define SPR_BOOKE_TLB1PS (0x159)
1552#define SPR_BOOKE_TLB2PS (0x15A)
1553#define SPR_BOOKE_TLB3PS (0x15B)
1554#define SPR_AMOR (0x15D)
1555#define SPR_BOOKE_MAS7_MAS3 (0x174)
1556#define SPR_BOOKE_IVOR0 (0x190)
1557#define SPR_BOOKE_IVOR1 (0x191)
1558#define SPR_BOOKE_IVOR2 (0x192)
1559#define SPR_BOOKE_IVOR3 (0x193)
1560#define SPR_BOOKE_IVOR4 (0x194)
1561#define SPR_BOOKE_IVOR5 (0x195)
1562#define SPR_BOOKE_IVOR6 (0x196)
1563#define SPR_BOOKE_IVOR7 (0x197)
1564#define SPR_BOOKE_IVOR8 (0x198)
1565#define SPR_BOOKE_IVOR9 (0x199)
1566#define SPR_BOOKE_IVOR10 (0x19A)
1567#define SPR_BOOKE_IVOR11 (0x19B)
1568#define SPR_BOOKE_IVOR12 (0x19C)
1569#define SPR_BOOKE_IVOR13 (0x19D)
1570#define SPR_BOOKE_IVOR14 (0x19E)
1571#define SPR_BOOKE_IVOR15 (0x19F)
1572#define SPR_BOOKE_IVOR38 (0x1B0)
1573#define SPR_BOOKE_IVOR39 (0x1B1)
1574#define SPR_BOOKE_IVOR40 (0x1B2)
1575#define SPR_BOOKE_IVOR41 (0x1B3)
1576#define SPR_BOOKE_IVOR42 (0x1B4)
1577#define SPR_BOOKE_GIVOR2 (0x1B8)
1578#define SPR_BOOKE_GIVOR3 (0x1B9)
1579#define SPR_BOOKE_GIVOR4 (0x1BA)
1580#define SPR_BOOKE_GIVOR8 (0x1BB)
1581#define SPR_BOOKE_GIVOR13 (0x1BC)
1582#define SPR_BOOKE_GIVOR14 (0x1BD)
1583#define SPR_TIR (0x1BE)
1584#define SPR_PTCR (0x1D0)
1585#define SPR_BOOKE_SPEFSCR (0x200)
1586#define SPR_Exxx_BBEAR (0x201)
1587#define SPR_Exxx_BBTAR (0x202)
1588#define SPR_Exxx_L1CFG0 (0x203)
1589#define SPR_Exxx_L1CFG1 (0x204)
1590#define SPR_Exxx_NPIDR (0x205)
1591#define SPR_ATBL (0x20E)
1592#define SPR_ATBU (0x20F)
1593#define SPR_IBAT0U (0x210)
1594#define SPR_BOOKE_IVOR32 (0x210)
1595#define SPR_RCPU_MI_GRA (0x210)
1596#define SPR_IBAT0L (0x211)
1597#define SPR_BOOKE_IVOR33 (0x211)
1598#define SPR_IBAT1U (0x212)
1599#define SPR_BOOKE_IVOR34 (0x212)
1600#define SPR_IBAT1L (0x213)
1601#define SPR_BOOKE_IVOR35 (0x213)
1602#define SPR_IBAT2U (0x214)
1603#define SPR_BOOKE_IVOR36 (0x214)
1604#define SPR_IBAT2L (0x215)
1605#define SPR_BOOKE_IVOR37 (0x215)
1606#define SPR_IBAT3U (0x216)
1607#define SPR_IBAT3L (0x217)
1608#define SPR_DBAT0U (0x218)
1609#define SPR_RCPU_L2U_GRA (0x218)
1610#define SPR_DBAT0L (0x219)
1611#define SPR_DBAT1U (0x21A)
1612#define SPR_DBAT1L (0x21B)
1613#define SPR_DBAT2U (0x21C)
1614#define SPR_DBAT2L (0x21D)
1615#define SPR_DBAT3U (0x21E)
1616#define SPR_DBAT3L (0x21F)
1617#define SPR_IBAT4U (0x230)
1618#define SPR_RPCU_BBCMCR (0x230)
1619#define SPR_MPC_IC_CST (0x230)
1620#define SPR_Exxx_CTXCR (0x230)
1621#define SPR_IBAT4L (0x231)
1622#define SPR_MPC_IC_ADR (0x231)
1623#define SPR_Exxx_DBCR3 (0x231)
1624#define SPR_IBAT5U (0x232)
1625#define SPR_MPC_IC_DAT (0x232)
1626#define SPR_Exxx_DBCNT (0x232)
1627#define SPR_IBAT5L (0x233)
1628#define SPR_IBAT6U (0x234)
1629#define SPR_IBAT6L (0x235)
1630#define SPR_IBAT7U (0x236)
1631#define SPR_IBAT7L (0x237)
1632#define SPR_DBAT4U (0x238)
1633#define SPR_RCPU_L2U_MCR (0x238)
1634#define SPR_MPC_DC_CST (0x238)
1635#define SPR_Exxx_ALTCTXCR (0x238)
1636#define SPR_DBAT4L (0x239)
1637#define SPR_MPC_DC_ADR (0x239)
1638#define SPR_DBAT5U (0x23A)
1639#define SPR_BOOKE_MCSRR0 (0x23A)
1640#define SPR_MPC_DC_DAT (0x23A)
1641#define SPR_DBAT5L (0x23B)
1642#define SPR_BOOKE_MCSRR1 (0x23B)
1643#define SPR_DBAT6U (0x23C)
1644#define SPR_BOOKE_MCSR (0x23C)
1645#define SPR_DBAT6L (0x23D)
1646#define SPR_Exxx_MCAR (0x23D)
1647#define SPR_DBAT7U (0x23E)
1648#define SPR_BOOKE_DSRR0 (0x23E)
1649#define SPR_DBAT7L (0x23F)
1650#define SPR_BOOKE_DSRR1 (0x23F)
1651#define SPR_BOOKE_SPRG8 (0x25C)
1652#define SPR_BOOKE_SPRG9 (0x25D)
1653#define SPR_BOOKE_MAS0 (0x270)
1654#define SPR_BOOKE_MAS1 (0x271)
1655#define SPR_BOOKE_MAS2 (0x272)
1656#define SPR_BOOKE_MAS3 (0x273)
1657#define SPR_BOOKE_MAS4 (0x274)
1658#define SPR_BOOKE_MAS5 (0x275)
1659#define SPR_BOOKE_MAS6 (0x276)
1660#define SPR_BOOKE_PID1 (0x279)
1661#define SPR_BOOKE_PID2 (0x27A)
1662#define SPR_MPC_DPDR (0x280)
1663#define SPR_MPC_IMMR (0x288)
1664#define SPR_BOOKE_TLB0CFG (0x2B0)
1665#define SPR_BOOKE_TLB1CFG (0x2B1)
1666#define SPR_BOOKE_TLB2CFG (0x2B2)
1667#define SPR_BOOKE_TLB3CFG (0x2B3)
1668#define SPR_BOOKE_EPR (0x2BE)
1669#define SPR_PERF0 (0x300)
1670#define SPR_RCPU_MI_RBA0 (0x300)
1671#define SPR_MPC_MI_CTR (0x300)
1672#define SPR_POWER_USIER (0x300)
1673#define SPR_PERF1 (0x301)
1674#define SPR_RCPU_MI_RBA1 (0x301)
1675#define SPR_POWER_UMMCR2 (0x301)
1676#define SPR_PERF2 (0x302)
1677#define SPR_RCPU_MI_RBA2 (0x302)
1678#define SPR_MPC_MI_AP (0x302)
1679#define SPR_POWER_UMMCRA (0x302)
1680#define SPR_PERF3 (0x303)
1681#define SPR_RCPU_MI_RBA3 (0x303)
1682#define SPR_MPC_MI_EPN (0x303)
1683#define SPR_POWER_UPMC1 (0x303)
1684#define SPR_PERF4 (0x304)
1685#define SPR_POWER_UPMC2 (0x304)
1686#define SPR_PERF5 (0x305)
1687#define SPR_MPC_MI_TWC (0x305)
1688#define SPR_POWER_UPMC3 (0x305)
1689#define SPR_PERF6 (0x306)
1690#define SPR_MPC_MI_RPN (0x306)
1691#define SPR_POWER_UPMC4 (0x306)
1692#define SPR_PERF7 (0x307)
1693#define SPR_POWER_UPMC5 (0x307)
1694#define SPR_PERF8 (0x308)
1695#define SPR_RCPU_L2U_RBA0 (0x308)
1696#define SPR_MPC_MD_CTR (0x308)
1697#define SPR_POWER_UPMC6 (0x308)
1698#define SPR_PERF9 (0x309)
1699#define SPR_RCPU_L2U_RBA1 (0x309)
1700#define SPR_MPC_MD_CASID (0x309)
1701#define SPR_970_UPMC7 (0X309)
1702#define SPR_PERFA (0x30A)
1703#define SPR_RCPU_L2U_RBA2 (0x30A)
1704#define SPR_MPC_MD_AP (0x30A)
1705#define SPR_970_UPMC8 (0X30A)
1706#define SPR_PERFB (0x30B)
1707#define SPR_RCPU_L2U_RBA3 (0x30B)
1708#define SPR_MPC_MD_EPN (0x30B)
1709#define SPR_POWER_UMMCR0 (0X30B)
1710#define SPR_PERFC (0x30C)
1711#define SPR_MPC_MD_TWB (0x30C)
1712#define SPR_POWER_USIAR (0X30C)
1713#define SPR_PERFD (0x30D)
1714#define SPR_MPC_MD_TWC (0x30D)
1715#define SPR_POWER_USDAR (0X30D)
1716#define SPR_PERFE (0x30E)
1717#define SPR_MPC_MD_RPN (0x30E)
1718#define SPR_POWER_UMMCR1 (0X30E)
1719#define SPR_PERFF (0x30F)
1720#define SPR_MPC_MD_TW (0x30F)
1721#define SPR_UPERF0 (0x310)
1722#define SPR_POWER_SIER (0x310)
1723#define SPR_UPERF1 (0x311)
1724#define SPR_POWER_MMCR2 (0x311)
1725#define SPR_UPERF2 (0x312)
1726#define SPR_POWER_MMCRA (0X312)
1727#define SPR_UPERF3 (0x313)
1728#define SPR_POWER_PMC1 (0X313)
1729#define SPR_UPERF4 (0x314)
1730#define SPR_POWER_PMC2 (0X314)
1731#define SPR_UPERF5 (0x315)
1732#define SPR_POWER_PMC3 (0X315)
1733#define SPR_UPERF6 (0x316)
1734#define SPR_POWER_PMC4 (0X316)
1735#define SPR_UPERF7 (0x317)
1736#define SPR_POWER_PMC5 (0X317)
1737#define SPR_UPERF8 (0x318)
1738#define SPR_POWER_PMC6 (0X318)
1739#define SPR_UPERF9 (0x319)
1740#define SPR_970_PMC7 (0X319)
1741#define SPR_UPERFA (0x31A)
1742#define SPR_970_PMC8 (0X31A)
1743#define SPR_UPERFB (0x31B)
1744#define SPR_POWER_MMCR0 (0X31B)
1745#define SPR_UPERFC (0x31C)
1746#define SPR_POWER_SIAR (0X31C)
1747#define SPR_UPERFD (0x31D)
1748#define SPR_POWER_SDAR (0X31D)
1749#define SPR_UPERFE (0x31E)
1750#define SPR_POWER_MMCR1 (0X31E)
1751#define SPR_UPERFF (0x31F)
1752#define SPR_RCPU_MI_RA0 (0x320)
1753#define SPR_MPC_MI_DBCAM (0x320)
1754#define SPR_BESCRS (0x320)
1755#define SPR_RCPU_MI_RA1 (0x321)
1756#define SPR_MPC_MI_DBRAM0 (0x321)
1757#define SPR_BESCRSU (0x321)
1758#define SPR_RCPU_MI_RA2 (0x322)
1759#define SPR_MPC_MI_DBRAM1 (0x322)
1760#define SPR_BESCRR (0x322)
1761#define SPR_RCPU_MI_RA3 (0x323)
1762#define SPR_BESCRRU (0x323)
1763#define SPR_EBBHR (0x324)
1764#define SPR_EBBRR (0x325)
1765#define SPR_BESCR (0x326)
1766#define SPR_RCPU_L2U_RA0 (0x328)
1767#define SPR_MPC_MD_DBCAM (0x328)
1768#define SPR_RCPU_L2U_RA1 (0x329)
1769#define SPR_MPC_MD_DBRAM0 (0x329)
1770#define SPR_RCPU_L2U_RA2 (0x32A)
1771#define SPR_MPC_MD_DBRAM1 (0x32A)
1772#define SPR_RCPU_L2U_RA3 (0x32B)
1773#define SPR_TAR (0x32F)
1774#define SPR_IC (0x350)
1775#define SPR_VTB (0x351)
1776#define SPR_MMCRC (0x353)
1777#define SPR_PSSCR (0x357)
1778#define SPR_440_INV0 (0x370)
1779#define SPR_440_INV1 (0x371)
1780#define SPR_440_INV2 (0x372)
1781#define SPR_440_INV3 (0x373)
1782#define SPR_440_ITV0 (0x374)
1783#define SPR_440_ITV1 (0x375)
1784#define SPR_440_ITV2 (0x376)
1785#define SPR_440_ITV3 (0x377)
1786#define SPR_440_CCR1 (0x378)
1787#define SPR_TACR (0x378)
1788#define SPR_TCSCR (0x379)
1789#define SPR_CSIGR (0x37a)
1790#define SPR_DCRIPR (0x37B)
1791#define SPR_POWER_SPMC1 (0x37C)
1792#define SPR_POWER_SPMC2 (0x37D)
1793#define SPR_POWER_MMCRS (0x37E)
1794#define SPR_WORT (0x37F)
1795#define SPR_PPR (0x380)
1796#define SPR_750_GQR0 (0x390)
1797#define SPR_440_DNV0 (0x390)
1798#define SPR_750_GQR1 (0x391)
1799#define SPR_440_DNV1 (0x391)
1800#define SPR_750_GQR2 (0x392)
1801#define SPR_440_DNV2 (0x392)
1802#define SPR_750_GQR3 (0x393)
1803#define SPR_440_DNV3 (0x393)
1804#define SPR_750_GQR4 (0x394)
1805#define SPR_440_DTV0 (0x394)
1806#define SPR_750_GQR5 (0x395)
1807#define SPR_440_DTV1 (0x395)
1808#define SPR_750_GQR6 (0x396)
1809#define SPR_440_DTV2 (0x396)
1810#define SPR_750_GQR7 (0x397)
1811#define SPR_440_DTV3 (0x397)
1812#define SPR_750_THRM4 (0x398)
1813#define SPR_750CL_HID2 (0x398)
1814#define SPR_440_DVLIM (0x398)
1815#define SPR_750_WPAR (0x399)
1816#define SPR_440_IVLIM (0x399)
1817#define SPR_TSCR (0x399)
1818#define SPR_750_DMAU (0x39A)
1819#define SPR_750_DMAL (0x39B)
1820#define SPR_440_RSTCFG (0x39B)
1821#define SPR_BOOKE_DCDBTRL (0x39C)
1822#define SPR_BOOKE_DCDBTRH (0x39D)
1823#define SPR_BOOKE_ICDBTRL (0x39E)
1824#define SPR_BOOKE_ICDBTRH (0x39F)
1825#define SPR_74XX_UMMCR2 (0x3A0)
1826#define SPR_7XX_UPMC5 (0x3A1)
1827#define SPR_7XX_UPMC6 (0x3A2)
1828#define SPR_UBAMR (0x3A7)
1829#define SPR_7XX_UMMCR0 (0x3A8)
1830#define SPR_7XX_UPMC1 (0x3A9)
1831#define SPR_7XX_UPMC2 (0x3AA)
1832#define SPR_7XX_USIAR (0x3AB)
1833#define SPR_7XX_UMMCR1 (0x3AC)
1834#define SPR_7XX_UPMC3 (0x3AD)
1835#define SPR_7XX_UPMC4 (0x3AE)
1836#define SPR_USDA (0x3AF)
1837#define SPR_40x_ZPR (0x3B0)
1838#define SPR_BOOKE_MAS7 (0x3B0)
1839#define SPR_74XX_MMCR2 (0x3B0)
1840#define SPR_7XX_PMC5 (0x3B1)
1841#define SPR_40x_PID (0x3B1)
1842#define SPR_7XX_PMC6 (0x3B2)
1843#define SPR_440_MMUCR (0x3B2)
1844#define SPR_4xx_CCR0 (0x3B3)
1845#define SPR_BOOKE_EPLC (0x3B3)
1846#define SPR_405_IAC3 (0x3B4)
1847#define SPR_BOOKE_EPSC (0x3B4)
1848#define SPR_405_IAC4 (0x3B5)
1849#define SPR_405_DVC1 (0x3B6)
1850#define SPR_405_DVC2 (0x3B7)
1851#define SPR_BAMR (0x3B7)
1852#define SPR_7XX_MMCR0 (0x3B8)
1853#define SPR_7XX_PMC1 (0x3B9)
1854#define SPR_40x_SGR (0x3B9)
1855#define SPR_7XX_PMC2 (0x3BA)
1856#define SPR_40x_DCWR (0x3BA)
1857#define SPR_7XX_SIAR (0x3BB)
1858#define SPR_405_SLER (0x3BB)
1859#define SPR_7XX_MMCR1 (0x3BC)
1860#define SPR_405_SU0R (0x3BC)
1861#define SPR_401_SKR (0x3BC)
1862#define SPR_7XX_PMC3 (0x3BD)
1863#define SPR_405_DBCR1 (0x3BD)
1864#define SPR_7XX_PMC4 (0x3BE)
1865#define SPR_SDA (0x3BF)
1866#define SPR_403_VTBL (0x3CC)
1867#define SPR_403_VTBU (0x3CD)
1868#define SPR_DMISS (0x3D0)
1869#define SPR_DCMP (0x3D1)
1870#define SPR_HASH1 (0x3D2)
1871#define SPR_HASH2 (0x3D3)
1872#define SPR_BOOKE_ICDBDR (0x3D3)
1873#define SPR_TLBMISS (0x3D4)
1874#define SPR_IMISS (0x3D4)
1875#define SPR_40x_ESR (0x3D4)
1876#define SPR_PTEHI (0x3D5)
1877#define SPR_ICMP (0x3D5)
1878#define SPR_40x_DEAR (0x3D5)
1879#define SPR_PTELO (0x3D6)
1880#define SPR_RPA (0x3D6)
1881#define SPR_40x_EVPR (0x3D6)
1882#define SPR_L3PM (0x3D7)
1883#define SPR_403_CDBCR (0x3D7)
1884#define SPR_L3ITCR0 (0x3D8)
1885#define SPR_TCR (0x3D8)
1886#define SPR_40x_TSR (0x3D8)
1887#define SPR_IBR (0x3DA)
1888#define SPR_40x_TCR (0x3DA)
1889#define SPR_ESASRR (0x3DB)
1890#define SPR_40x_PIT (0x3DB)
1891#define SPR_403_TBL (0x3DC)
1892#define SPR_403_TBU (0x3DD)
1893#define SPR_SEBR (0x3DE)
1894#define SPR_40x_SRR2 (0x3DE)
1895#define SPR_SER (0x3DF)
1896#define SPR_40x_SRR3 (0x3DF)
1897#define SPR_L3OHCR (0x3E8)
1898#define SPR_L3ITCR1 (0x3E9)
1899#define SPR_L3ITCR2 (0x3EA)
1900#define SPR_L3ITCR3 (0x3EB)
1901#define SPR_HID0 (0x3F0)
1902#define SPR_40x_DBSR (0x3F0)
1903#define SPR_HID1 (0x3F1)
1904#define SPR_IABR (0x3F2)
1905#define SPR_40x_DBCR0 (0x3F2)
1906#define SPR_601_HID2 (0x3F2)
1907#define SPR_Exxx_L1CSR0 (0x3F2)
1908#define SPR_ICTRL (0x3F3)
1909#define SPR_HID2 (0x3F3)
1910#define SPR_750CL_HID4 (0x3F3)
1911#define SPR_Exxx_L1CSR1 (0x3F3)
1912#define SPR_440_DBDR (0x3F3)
1913#define SPR_LDSTDB (0x3F4)
1914#define SPR_750_TDCL (0x3F4)
1915#define SPR_40x_IAC1 (0x3F4)
1916#define SPR_MMUCSR0 (0x3F4)
1917#define SPR_970_HID4 (0x3F4)
1918#define SPR_DABR (0x3F5)
1919#define DABR_MASK (~(target_ulong)0x7)
1920#define SPR_Exxx_BUCSR (0x3F5)
1921#define SPR_40x_IAC2 (0x3F5)
1922#define SPR_601_HID5 (0x3F5)
1923#define SPR_40x_DAC1 (0x3F6)
1924#define SPR_MSSCR0 (0x3F6)
1925#define SPR_970_HID5 (0x3F6)
1926#define SPR_MSSSR0 (0x3F7)
1927#define SPR_MSSCR1 (0x3F7)
1928#define SPR_DABRX (0x3F7)
1929#define SPR_40x_DAC2 (0x3F7)
1930#define SPR_MMUCFG (0x3F7)
1931#define SPR_LDSTCR (0x3F8)
1932#define SPR_L2PMCR (0x3F8)
1933#define SPR_750FX_HID2 (0x3F8)
1934#define SPR_Exxx_L1FINV0 (0x3F8)
1935#define SPR_L2CR (0x3F9)
1936#define SPR_L3CR (0x3FA)
1937#define SPR_750_TDCH (0x3FA)
1938#define SPR_IABR2 (0x3FA)
1939#define SPR_40x_DCCR (0x3FA)
1940#define SPR_ICTC (0x3FB)
1941#define SPR_40x_ICCR (0x3FB)
1942#define SPR_THRM1 (0x3FC)
1943#define SPR_403_PBL1 (0x3FC)
1944#define SPR_SP (0x3FD)
1945#define SPR_THRM2 (0x3FD)
1946#define SPR_403_PBU1 (0x3FD)
1947#define SPR_604_HID13 (0x3FD)
1948#define SPR_LT (0x3FE)
1949#define SPR_THRM3 (0x3FE)
1950#define SPR_RCPU_FPECR (0x3FE)
1951#define SPR_403_PBL2 (0x3FE)
1952#define SPR_PIR (0x3FF)
1953#define SPR_403_PBU2 (0x3FF)
1954#define SPR_601_HID15 (0x3FF)
1955#define SPR_604_HID15 (0x3FF)
1956#define SPR_E500_SVR (0x3FF)
1957
1958
1959#define EPCR_DMIUH (1 << 22)
1960
1961#define EPCR_DGTMI (1 << 23)
1962
1963#define EPCR_GICM (1 << 24)
1964
1965#define EPCR_ICM (1 << 25)
1966
1967#define EPCR_DUVD (1 << 26)
1968
1969#define EPCR_ISIGS (1 << 27)
1970
1971#define EPCR_DSIGS (1 << 28)
1972
1973#define EPCR_ITLBGS (1 << 29)
1974
1975#define EPCR_DTLBGS (1 << 30)
1976
1977#define EPCR_EXTGS (1 << 31)
1978
1979#define L1CSR0_CPE 0x00010000
1980#define L1CSR0_CUL 0x00000400
1981#define L1CSR0_DCLFR 0x00000100
1982#define L1CSR0_DCFI 0x00000002
1983#define L1CSR0_DCE 0x00000001
1984
1985#define L1CSR1_CPE 0x00010000
1986#define L1CSR1_ICUL 0x00000400
1987#define L1CSR1_ICLFR 0x00000100
1988#define L1CSR1_ICFI 0x00000002
1989#define L1CSR1_ICE 0x00000001
1990
1991
1992#define HID0_DEEPNAP (1 << 24)
1993#define HID0_DOZE (1 << 23)
1994#define HID0_NAP (1 << 22)
1995#define HID0_HILE PPC_BIT(19)
1996#define HID0_POWER9_HILE PPC_BIT(4)
1997
1998
1999
2000enum {
2001 PPC_NONE = 0x0000000000000000ULL,
2002
2003 PPC_INSNS_BASE = 0x0000000000000001ULL,
2004
2005#define PPC_INTEGER PPC_INSNS_BASE
2006
2007#define PPC_FLOW PPC_INSNS_BASE
2008
2009#define PPC_MEM PPC_INSNS_BASE
2010
2011#define PPC_RES PPC_INSNS_BASE
2012
2013#define PPC_MISC PPC_INSNS_BASE
2014
2015
2016 PPC_POWER = 0x0000000000000002ULL,
2017
2018 PPC_POWER2 = 0x0000000000000004ULL,
2019
2020 PPC_POWER_RTC = 0x0000000000000008ULL,
2021
2022 PPC_POWER_BR = 0x0000000000000010ULL,
2023
2024 PPC_64B = 0x0000000000000020ULL,
2025
2026 PPC_64BX = 0x0000000000000040ULL,
2027
2028 PPC_64H = 0x0000000000000080ULL,
2029
2030 PPC_WAIT = 0x0000000000000100ULL,
2031
2032 PPC_MFTB = 0x0000000000000200ULL,
2033
2034
2035
2036 PPC_602_SPEC = 0x0000000000000400ULL,
2037
2038 PPC_ISEL = 0x0000000000000800ULL,
2039
2040 PPC_POPCNTB = 0x0000000000001000ULL,
2041
2042 PPC_STRING = 0x0000000000002000ULL,
2043
2044 PPC_CILDST = 0x0000000000004000ULL,
2045
2046
2047
2048 PPC_FLOAT = 0x0000000000010000ULL,
2049
2050 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2051 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2052 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2053 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2054 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2055 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2056 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2057
2058
2059
2060 PPC_ALTIVEC = 0x0000000001000000ULL,
2061
2062 PPC_SPE = 0x0000000002000000ULL,
2063
2064 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2065
2066 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2067
2068
2069 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2070 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2071 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2072
2073 PPC_MEM_SYNC = 0x0000000080000000ULL,
2074
2075 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2076
2077
2078 PPC_CACHE = 0x0000000200000000ULL,
2079
2080 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2081
2082 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2083
2084 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2085
2086 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2087
2088
2089
2090 PPC_EXTERN = 0x0000010000000000ULL,
2091
2092 PPC_SEGMENT = 0x0000020000000000ULL,
2093
2094 PPC_6xx_TLB = 0x0000040000000000ULL,
2095
2096 PPC_74xx_TLB = 0x0000080000000000ULL,
2097
2098 PPC_40x_TLB = 0x0000100000000000ULL,
2099
2100 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2101
2102 PPC_SLBI = 0x0000400000000000ULL,
2103
2104
2105 PPC_WRTEE = 0x0001000000000000ULL,
2106
2107 PPC_40x_EXCP = 0x0002000000000000ULL,
2108
2109 PPC_405_MAC = 0x0004000000000000ULL,
2110
2111 PPC_440_SPEC = 0x0008000000000000ULL,
2112
2113 PPC_BOOKE = 0x0010000000000000ULL,
2114
2115 PPC_MFAPIDI = 0x0020000000000000ULL,
2116
2117 PPC_TLBIVA = 0x0040000000000000ULL,
2118
2119 PPC_TLBIVAX = 0x0080000000000000ULL,
2120
2121 PPC_4xx_COMMON = 0x0100000000000000ULL,
2122
2123 PPC_40x_ICBT = 0x0200000000000000ULL,
2124
2125 PPC_RFMCI = 0x0400000000000000ULL,
2126
2127 PPC_RFDI = 0x0800000000000000ULL,
2128
2129 PPC_DCR = 0x1000000000000000ULL,
2130
2131 PPC_DCRX = 0x2000000000000000ULL,
2132
2133 PPC_DCRUX = 0x4000000000000000ULL,
2134
2135 PPC_POPCNTWD = 0x8000000000000000ULL,
2136
2137#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2138 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2139 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2140 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2141 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2142 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2143 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2144 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2145 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2146 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2147 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2148 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2149 | PPC_CACHE | PPC_CACHE_ICBI \
2150 | PPC_CACHE_DCBZ \
2151 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2152 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2153 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2154 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2155 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2156 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2157 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2158 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2159 | PPC_POPCNTWD | PPC_CILDST)
2160
2161
2162
2163
2164 PPC2_BOOKE206 = 0x0000000000000001ULL,
2165
2166 PPC2_VSX = 0x0000000000000002ULL,
2167
2168 PPC2_DFP = 0x0000000000000004ULL,
2169
2170 PPC2_PRCNTL = 0x0000000000000008ULL,
2171
2172 PPC2_DBRX = 0x0000000000000010ULL,
2173
2174 PPC2_ISA205 = 0x0000000000000020ULL,
2175
2176 PPC2_VSX207 = 0x0000000000000040ULL,
2177
2178 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2179
2180 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2181
2182 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2183
2184 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2185
2186 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2187
2188 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2189
2190 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2191
2192 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2193
2194 PPC2_ISA207S = 0x0000000000008000ULL,
2195
2196 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2197
2198 PPC2_TM = 0x0000000000020000ULL,
2199
2200 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2201
2202 PPC2_ISA300 = 0x0000000000080000ULL,
2203
2204#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2205 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2206 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2207 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2208 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2209 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2210 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2211 PPC2_ISA300)
2212};
2213
2214
2215
2216
2217
2218enum {
2219
2220 ACCESS_USER = 0x00,
2221 ACCESS_SUPER = 0x01,
2222
2223 ACCESS_CODE = 0x10,
2224 ACCESS_INT = 0x20,
2225 ACCESS_FLOAT = 0x30,
2226 ACCESS_RES = 0x40,
2227 ACCESS_EXT = 0x50,
2228 ACCESS_CACHE = 0x60,
2229};
2230
2231
2232
2233
2234
2235enum {
2236
2237 PPC6xx_INPUT_HRESET = 0,
2238 PPC6xx_INPUT_SRESET = 1,
2239 PPC6xx_INPUT_CKSTP_IN = 2,
2240 PPC6xx_INPUT_MCP = 3,
2241 PPC6xx_INPUT_SMI = 4,
2242 PPC6xx_INPUT_INT = 5,
2243 PPC6xx_INPUT_TBEN = 6,
2244 PPC6xx_INPUT_WAKEUP = 7,
2245 PPC6xx_INPUT_NB,
2246};
2247
2248enum {
2249
2250 PPCBookE_INPUT_HRESET = 0,
2251 PPCBookE_INPUT_SRESET = 1,
2252 PPCBookE_INPUT_CKSTP_IN = 2,
2253 PPCBookE_INPUT_MCP = 3,
2254 PPCBookE_INPUT_SMI = 4,
2255 PPCBookE_INPUT_INT = 5,
2256 PPCBookE_INPUT_CINT = 6,
2257 PPCBookE_INPUT_NB,
2258};
2259
2260enum {
2261
2262 PPCE500_INPUT_RESET_CORE = 0,
2263 PPCE500_INPUT_MCK = 1,
2264 PPCE500_INPUT_CINT = 3,
2265 PPCE500_INPUT_INT = 4,
2266 PPCE500_INPUT_DEBUG = 6,
2267 PPCE500_INPUT_NB,
2268};
2269
2270enum {
2271
2272 PPC40x_INPUT_RESET_CORE = 0,
2273 PPC40x_INPUT_RESET_CHIP = 1,
2274 PPC40x_INPUT_RESET_SYS = 2,
2275 PPC40x_INPUT_CINT = 3,
2276 PPC40x_INPUT_INT = 4,
2277 PPC40x_INPUT_HALT = 5,
2278 PPC40x_INPUT_DEBUG = 6,
2279 PPC40x_INPUT_NB,
2280};
2281
2282enum {
2283
2284 PPCRCPU_INPUT_PORESET = 0,
2285 PPCRCPU_INPUT_HRESET = 1,
2286 PPCRCPU_INPUT_SRESET = 2,
2287 PPCRCPU_INPUT_IRQ0 = 3,
2288 PPCRCPU_INPUT_IRQ1 = 4,
2289 PPCRCPU_INPUT_IRQ2 = 5,
2290 PPCRCPU_INPUT_IRQ3 = 6,
2291 PPCRCPU_INPUT_IRQ4 = 7,
2292 PPCRCPU_INPUT_IRQ5 = 8,
2293 PPCRCPU_INPUT_IRQ6 = 9,
2294 PPCRCPU_INPUT_IRQ7 = 10,
2295 PPCRCPU_INPUT_NB,
2296};
2297
2298#if defined(TARGET_PPC64)
2299enum {
2300
2301 PPC970_INPUT_HRESET = 0,
2302 PPC970_INPUT_SRESET = 1,
2303 PPC970_INPUT_CKSTP = 2,
2304 PPC970_INPUT_TBEN = 3,
2305 PPC970_INPUT_MCP = 4,
2306 PPC970_INPUT_INT = 5,
2307 PPC970_INPUT_THINT = 6,
2308 PPC970_INPUT_NB,
2309};
2310
2311enum {
2312
2313 POWER7_INPUT_INT = 0,
2314
2315
2316
2317 POWER7_INPUT_NB,
2318};
2319#endif
2320
2321
2322enum {
2323
2324 PPC_INTERRUPT_RESET = 0,
2325 PPC_INTERRUPT_WAKEUP,
2326 PPC_INTERRUPT_MCK,
2327 PPC_INTERRUPT_EXT,
2328 PPC_INTERRUPT_SMI,
2329 PPC_INTERRUPT_CEXT,
2330 PPC_INTERRUPT_DEBUG,
2331 PPC_INTERRUPT_THERM,
2332
2333 PPC_INTERRUPT_DECR,
2334 PPC_INTERRUPT_HDECR,
2335 PPC_INTERRUPT_PIT,
2336 PPC_INTERRUPT_FIT,
2337 PPC_INTERRUPT_WDT,
2338 PPC_INTERRUPT_CDOORBELL,
2339 PPC_INTERRUPT_DOORBELL,
2340 PPC_INTERRUPT_PERFM,
2341 PPC_INTERRUPT_HMI,
2342 PPC_INTERRUPT_HDOORBELL,
2343};
2344
2345
2346enum {
2347 PCR_COMPAT_2_05 = PPC_BIT(62),
2348 PCR_COMPAT_2_06 = PPC_BIT(61),
2349 PCR_COMPAT_2_07 = PPC_BIT(60),
2350 PCR_COMPAT_3_00 = PPC_BIT(59),
2351 PCR_VEC_DIS = PPC_BIT(0),
2352 PCR_VSX_DIS = PPC_BIT(1),
2353 PCR_TM_DIS = PPC_BIT(2),
2354};
2355
2356
2357enum {
2358 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2359 HMER_PROC_RECV_DONE = PPC_BIT(2),
2360 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2361 HMER_TFAC_ERROR = PPC_BIT(4),
2362 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2363 HMER_XSCOM_FAIL = PPC_BIT(8),
2364 HMER_XSCOM_DONE = PPC_BIT(9),
2365 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2366 HMER_WARN_RISE = PPC_BIT(14),
2367 HMER_WARN_FALL = PPC_BIT(15),
2368 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2369 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2370 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2371 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2372};
2373
2374
2375enum {
2376 AIL_NONE = 0,
2377 AIL_RESERVED = 1,
2378 AIL_0001_8000 = 2,
2379 AIL_C000_0000_0000_4000 = 3,
2380};
2381
2382
2383
2384#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2385target_ulong cpu_read_xer(CPUPPCState *env);
2386void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2387
2388static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2389 target_ulong *cs_base, uint32_t *flags)
2390{
2391 *pc = env->nip;
2392 *cs_base = 0;
2393 *flags = env->hflags;
2394}
2395
2396void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2397void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2398 uintptr_t raddr);
2399void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2400 uint32_t error_code);
2401void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2402 uint32_t error_code, uintptr_t raddr);
2403
2404#if !defined(CONFIG_USER_ONLY)
2405static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2406{
2407 uintptr_t tlbml = (uintptr_t)tlbm;
2408 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2409
2410 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2411}
2412
2413static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2414{
2415 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2416 int r = tlbncfg & TLBnCFG_N_ENTRY;
2417 return r;
2418}
2419
2420static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2421{
2422 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2423 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2424 return r;
2425}
2426
2427static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2428{
2429 int id = booke206_tlbm_id(env, tlbm);
2430 int end = 0;
2431 int i;
2432
2433 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2434 end += booke206_tlb_size(env, i);
2435 if (id < end) {
2436 return i;
2437 }
2438 }
2439
2440 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2441 return 0;
2442}
2443
2444static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2445{
2446 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2447 int tlbid = booke206_tlbm_id(env, tlb);
2448 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2449}
2450
2451static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2452 target_ulong ea, int way)
2453{
2454 int r;
2455 uint32_t ways = booke206_tlb_ways(env, tlbn);
2456 int ways_bits = ctz32(ways);
2457 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2458 int i;
2459
2460 way &= ways - 1;
2461 ea >>= MAS2_EPN_SHIFT;
2462 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2463 r = (ea << ways_bits) | way;
2464
2465 if (r >= booke206_tlb_size(env, tlbn)) {
2466 return NULL;
2467 }
2468
2469
2470 for (i = 0; i < tlbn; i++) {
2471 r += booke206_tlb_size(env, i);
2472 }
2473
2474 return &env->tlb.tlbm[r];
2475}
2476
2477
2478static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2479{
2480 uint32_t ret = 0;
2481
2482 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2483
2484 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2485 } else {
2486 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2487 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2488 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2489 int i;
2490 for (i = min; i <= max; i++) {
2491 ret |= (1 << (i << 1));
2492 }
2493 }
2494
2495 return ret;
2496}
2497
2498static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2499 ppcmas_tlb_t *tlb)
2500{
2501 uint8_t i;
2502 int32_t tsize = -1;
2503
2504 for (i = 0; i < 32; i++) {
2505 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2506 if (tsize == -1) {
2507 tsize = i;
2508 } else {
2509 return;
2510 }
2511 }
2512 }
2513
2514
2515 assert(tsize != -1);
2516 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2517 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2518}
2519
2520#endif
2521
2522static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2523{
2524 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2525 return msr & (1ULL << MSR_CM);
2526 }
2527
2528 return msr & (1ULL << MSR_SF);
2529}
2530
2531
2532
2533
2534
2535static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2536{
2537 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2538 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2539}
2540
2541void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2542
2543void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2544#endif
2545