qemu/target/ppc/helper_regs.h
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   1/*
   2 *  PowerPC emulation special registers manipulation helpers for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HELPER_REGS_H
  21#define HELPER_REGS_H
  22
  23#include "qemu/main-loop.h"
  24#include "exec/exec-all.h"
  25
  26/* Swap temporary saved registers with GPRs */
  27static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
  28{
  29    target_ulong tmp;
  30
  31    tmp = env->gpr[0];
  32    env->gpr[0] = env->tgpr[0];
  33    env->tgpr[0] = tmp;
  34    tmp = env->gpr[1];
  35    env->gpr[1] = env->tgpr[1];
  36    env->tgpr[1] = tmp;
  37    tmp = env->gpr[2];
  38    env->gpr[2] = env->tgpr[2];
  39    env->tgpr[2] = tmp;
  40    tmp = env->gpr[3];
  41    env->gpr[3] = env->tgpr[3];
  42    env->tgpr[3] = tmp;
  43}
  44
  45static inline void hreg_compute_mem_idx(CPUPPCState *env)
  46{
  47    /* This is our encoding for server processors. The architecture
  48     * specifies that there is no such thing as userspace with
  49     * translation off, however it appears that MacOS does it and
  50     * some 32-bit CPUs support it. Weird...
  51     *
  52     *   0 = Guest User space virtual mode
  53     *   1 = Guest Kernel space virtual mode
  54     *   2 = Guest User space real mode
  55     *   3 = Guest Kernel space real mode
  56     *   4 = HV User space virtual mode
  57     *   5 = HV Kernel space virtual mode
  58     *   6 = HV User space real mode
  59     *   7 = HV Kernel space real mode
  60     *
  61     * For BookE, we need 8 MMU modes as follow:
  62     *
  63     *  0 = AS 0 HV User space
  64     *  1 = AS 0 HV Kernel space
  65     *  2 = AS 1 HV User space
  66     *  3 = AS 1 HV Kernel space
  67     *  4 = AS 0 Guest User space
  68     *  5 = AS 0 Guest Kernel space
  69     *  6 = AS 1 Guest User space
  70     *  7 = AS 1 Guest Kernel space
  71     */
  72    if (env->mmu_model & POWERPC_MMU_BOOKE) {
  73        env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  74        env->immu_idx += msr_is ? 2 : 0;
  75        env->dmmu_idx += msr_ds ? 2 : 0;
  76        env->immu_idx += msr_gs ? 4 : 0;
  77        env->dmmu_idx += msr_gs ? 4 : 0;
  78    } else {
  79        env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
  80        env->immu_idx += msr_ir ? 0 : 2;
  81        env->dmmu_idx += msr_dr ? 0 : 2;
  82        env->immu_idx += msr_hv ? 4 : 0;
  83        env->dmmu_idx += msr_hv ? 4 : 0;
  84    }
  85}
  86
  87static inline void hreg_compute_hflags(CPUPPCState *env)
  88{
  89    target_ulong hflags_mask;
  90
  91    /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
  92    hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
  93        (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
  94        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
  95    hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
  96    hreg_compute_mem_idx(env);
  97    env->hflags = env->msr & hflags_mask;
  98    /* Merge with hflags coming from other registers */
  99    env->hflags |= env->hflags_nmsr;
 100}
 101
 102static inline void cpu_interrupt_exittb(CPUState *cs)
 103{
 104    if (!qemu_mutex_iothread_locked()) {
 105        qemu_mutex_lock_iothread();
 106        cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 107        qemu_mutex_unlock_iothread();
 108    } else {
 109        cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
 110    }
 111}
 112
 113static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
 114                                 int alter_hv)
 115{
 116    int excp;
 117#if !defined(CONFIG_USER_ONLY)
 118    CPUState *cs = CPU(ppc_env_get_cpu(env));
 119#endif
 120
 121    excp = 0;
 122    value &= env->msr_mask;
 123#if !defined(CONFIG_USER_ONLY)
 124    /* Neither mtmsr nor guest state can alter HV */
 125    if (!alter_hv || !(env->msr & MSR_HVB)) {
 126        value &= ~MSR_HVB;
 127        value |= env->msr & MSR_HVB;
 128    }
 129    if (((value >> MSR_IR) & 1) != msr_ir ||
 130        ((value >> MSR_DR) & 1) != msr_dr) {
 131        cpu_interrupt_exittb(cs);
 132    }
 133    if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
 134        ((value >> MSR_GS) & 1) != msr_gs) {
 135        cpu_interrupt_exittb(cs);
 136    }
 137    if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
 138                 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
 139        /* Swap temporary saved registers with GPRs */
 140        hreg_swap_gpr_tgpr(env);
 141    }
 142    if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
 143        /* Change the exception prefix on PowerPC 601 */
 144        env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
 145    }
 146    /* If PR=1 then EE, IR and DR must be 1
 147     *
 148     * Note: We only enforce this on 64-bit server processors.
 149     * It appears that:
 150     * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
 151     *   exploits it.
 152     * - 64-bit embedded implementations do not need any operation to be
 153     *   performed when PR is set.
 154     */
 155    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
 156        value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
 157    }
 158#endif
 159    env->msr = value;
 160    hreg_compute_hflags(env);
 161#if !defined(CONFIG_USER_ONLY)
 162    if (unlikely(msr_pow == 1)) {
 163        if (!env->pending_interrupts && (*env->check_pow)(env)) {
 164            cs->halted = 1;
 165            excp = EXCP_HALTED;
 166        }
 167    }
 168#endif
 169
 170    return excp;
 171}
 172
 173#if !defined(CONFIG_USER_ONLY)
 174static inline void check_tlb_flush(CPUPPCState *env, bool global)
 175{
 176    CPUState *cs = CPU(ppc_env_get_cpu(env));
 177    if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
 178        tlb_flush(cs);
 179        env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 180    }
 181
 182    /* Propagate TLB invalidations to other CPUs when the guest uses broadcast
 183     * TLB invalidation instructions.
 184     */
 185    if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
 186        CPUState *other_cs;
 187        CPU_FOREACH(other_cs) {
 188            if (other_cs != cs) {
 189                PowerPCCPU *cpu = POWERPC_CPU(other_cs);
 190                CPUPPCState *other_env = &cpu->env;
 191
 192                other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
 193                tlb_flush(other_cs);
 194            }
 195        }
 196        env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
 197    }
 198}
 199#else
 200static inline void check_tlb_flush(CPUPPCState *env, bool global) { }
 201#endif
 202
 203#endif /* HELPER_REGS_H */
 204
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