1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include "qemu/osdep.h"
20#include "cpu.h"
21#include "exec/exec-all.h"
22#include "qemu/host-utils.h"
23#include "exec/helper-proto.h"
24#include "helper_regs.h"
25#include "exec/cpu_ldst.h"
26#include "tcg.h"
27#include "internal.h"
28
29
30
31static inline bool needs_byteswap(const CPUPPCState *env)
32{
33#if defined(TARGET_WORDS_BIGENDIAN)
34 return msr_le;
35#else
36 return !msr_le;
37#endif
38}
39
40
41
42
43static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
44 target_long arg)
45{
46#if defined(TARGET_PPC64)
47 if (!msr_is_64bit(env, env->msr)) {
48 return (uint32_t)(addr + arg);
49 } else
50#endif
51 {
52 return addr + arg;
53 }
54}
55
56void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
57{
58 for (; reg < 32; reg++) {
59 if (needs_byteswap(env)) {
60 env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
61 } else {
62 env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
63 }
64 addr = addr_add(env, addr, 4);
65 }
66}
67
68void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
69{
70 for (; reg < 32; reg++) {
71 if (needs_byteswap(env)) {
72 cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
73 GETPC());
74 } else {
75 cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
76 }
77 addr = addr_add(env, addr, 4);
78 }
79}
80
81static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
82 uint32_t reg, uintptr_t raddr)
83{
84 int sh;
85
86 for (; nb > 3; nb -= 4) {
87 env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
88 reg = (reg + 1) % 32;
89 addr = addr_add(env, addr, 4);
90 }
91 if (unlikely(nb > 0)) {
92 env->gpr[reg] = 0;
93 for (sh = 24; nb > 0; nb--, sh -= 8) {
94 env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh;
95 addr = addr_add(env, addr, 1);
96 }
97 }
98}
99
100void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
101{
102 do_lsw(env, addr, nb, reg, GETPC());
103}
104
105
106
107
108
109
110void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
111 uint32_t ra, uint32_t rb)
112{
113 if (likely(xer_bc != 0)) {
114 int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
115 if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
116 lsw_reg_in_range(reg, num_used_regs, rb))) {
117 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
118 POWERPC_EXCP_INVAL |
119 POWERPC_EXCP_INVAL_LSWX, GETPC());
120 } else {
121 do_lsw(env, addr, xer_bc, reg, GETPC());
122 }
123 }
124}
125
126void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
127 uint32_t reg)
128{
129 int sh;
130
131 for (; nb > 3; nb -= 4) {
132 cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
133 reg = (reg + 1) % 32;
134 addr = addr_add(env, addr, 4);
135 }
136 if (unlikely(nb > 0)) {
137 for (sh = 24; nb > 0; nb--, sh -= 8) {
138 cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC());
139 addr = addr_add(env, addr, 1);
140 }
141 }
142}
143
144void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
145{
146 target_ulong mask, dcbz_size = env->dcache_line_size;
147 uint32_t i;
148 void *haddr;
149
150#if defined(TARGET_PPC64)
151
152 if (env->excp_model == POWERPC_EXCP_970 &&
153 !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
154 dcbz_size = 32;
155 }
156#endif
157
158
159 mask = ~(dcbz_size - 1);
160 addr &= mask;
161
162
163 if ((env->reserve_addr & mask) == (addr & mask)) {
164 env->reserve_addr = (target_ulong)-1ULL;
165 }
166
167
168 haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx);
169 if (haddr) {
170 memset(haddr, 0, dcbz_size);
171 } else {
172
173 for (i = 0; i < dcbz_size; i += 8) {
174 cpu_stq_data_ra(env, addr + i, 0, GETPC());
175 }
176 }
177}
178
179void helper_icbi(CPUPPCState *env, target_ulong addr)
180{
181 addr &= ~(env->dcache_line_size - 1);
182
183
184
185
186
187 cpu_ldl_data_ra(env, addr, GETPC());
188}
189
190
191target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
192 uint32_t ra, uint32_t rb)
193{
194 int i, c, d;
195
196 d = 24;
197 for (i = 0; i < xer_bc; i++) {
198 c = cpu_ldub_data_ra(env, addr, GETPC());
199 addr = addr_add(env, addr, 1);
200
201 if (likely(reg != rb && (ra == 0 || reg != ra))) {
202 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
203 }
204 if (unlikely(c == xer_cmp)) {
205 break;
206 }
207 if (likely(d != 0)) {
208 d -= 8;
209 } else {
210 d = 24;
211 reg++;
212 reg = reg & 0x1F;
213 }
214 }
215 return i;
216}
217
218#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
219uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
220 uint32_t opidx)
221{
222 Int128 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
223 env->retxh = int128_gethi(ret);
224 return int128_getlo(ret);
225}
226
227uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
228 uint32_t opidx)
229{
230 Int128 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
231 env->retxh = int128_gethi(ret);
232 return int128_getlo(ret);
233}
234
235void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
236 uint64_t lo, uint64_t hi, uint32_t opidx)
237{
238 Int128 val = int128_make128(lo, hi);
239 helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
240}
241
242void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
243 uint64_t lo, uint64_t hi, uint32_t opidx)
244{
245 Int128 val = int128_make128(lo, hi);
246 helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
247}
248
249uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
250 uint64_t new_lo, uint64_t new_hi,
251 uint32_t opidx)
252{
253 bool success = false;
254
255 if (likely(addr == env->reserve_addr)) {
256 Int128 oldv, cmpv, newv;
257
258 cmpv = int128_make128(env->reserve_val2, env->reserve_val);
259 newv = int128_make128(new_lo, new_hi);
260 oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
261 opidx, GETPC());
262 success = int128_eq(oldv, cmpv);
263 }
264 env->reserve_addr = -1;
265 return env->so + success * CRF_EQ_BIT;
266}
267
268uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
269 uint64_t new_lo, uint64_t new_hi,
270 uint32_t opidx)
271{
272 bool success = false;
273
274 if (likely(addr == env->reserve_addr)) {
275 Int128 oldv, cmpv, newv;
276
277 cmpv = int128_make128(env->reserve_val2, env->reserve_val);
278 newv = int128_make128(new_lo, new_hi);
279 oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
280 opidx, GETPC());
281 success = int128_eq(oldv, cmpv);
282 }
283 env->reserve_addr = -1;
284 return env->so + success * CRF_EQ_BIT;
285}
286#endif
287
288
289
290#if defined(HOST_WORDS_BIGENDIAN)
291#define HI_IDX 0
292#define LO_IDX 1
293#else
294#define HI_IDX 1
295#define LO_IDX 0
296#endif
297
298
299
300
301
302
303#define LVE(name, access, swap, element) \
304 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
305 target_ulong addr) \
306 { \
307 size_t n_elems = ARRAY_SIZE(r->element); \
308 int adjust = HI_IDX*(n_elems - 1); \
309 int sh = sizeof(r->element[0]) >> 1; \
310 int index = (addr & 0xf) >> sh; \
311 if (msr_le) { \
312 index = n_elems - index - 1; \
313 } \
314 \
315 if (needs_byteswap(env)) { \
316 r->element[LO_IDX ? index : (adjust - index)] = \
317 swap(access(env, addr, GETPC())); \
318 } else { \
319 r->element[LO_IDX ? index : (adjust - index)] = \
320 access(env, addr, GETPC()); \
321 } \
322 }
323#define I(x) (x)
324LVE(lvebx, cpu_ldub_data_ra, I, u8)
325LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
326LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
327#undef I
328#undef LVE
329
330#define STVE(name, access, swap, element) \
331 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
332 target_ulong addr) \
333 { \
334 size_t n_elems = ARRAY_SIZE(r->element); \
335 int adjust = HI_IDX * (n_elems - 1); \
336 int sh = sizeof(r->element[0]) >> 1; \
337 int index = (addr & 0xf) >> sh; \
338 if (msr_le) { \
339 index = n_elems - index - 1; \
340 } \
341 \
342 if (needs_byteswap(env)) { \
343 access(env, addr, swap(r->element[LO_IDX ? index : \
344 (adjust - index)]), \
345 GETPC()); \
346 } else { \
347 access(env, addr, r->element[LO_IDX ? index : \
348 (adjust - index)], GETPC()); \
349 } \
350 }
351#define I(x) (x)
352STVE(stvebx, cpu_stb_data_ra, I, u8)
353STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
354STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
355#undef I
356#undef LVE
357
358#ifdef TARGET_PPC64
359#define GET_NB(rb) ((rb >> 56) & 0xFF)
360
361#define VSX_LXVL(name, lj) \
362void helper_##name(CPUPPCState *env, target_ulong addr, \
363 target_ulong xt_num, target_ulong rb) \
364{ \
365 int i; \
366 ppc_vsr_t xt; \
367 uint64_t nb = GET_NB(rb); \
368 \
369 xt.s128 = int128_zero(); \
370 if (nb) { \
371 nb = (nb >= 16) ? 16 : nb; \
372 if (msr_le && !lj) { \
373 for (i = 16; i > 16 - nb; i--) { \
374 xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
375 addr = addr_add(env, addr, 1); \
376 } \
377 } else { \
378 for (i = 0; i < nb; i++) { \
379 xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
380 addr = addr_add(env, addr, 1); \
381 } \
382 } \
383 } \
384 putVSR(xt_num, &xt, env); \
385}
386
387VSX_LXVL(lxvl, 0)
388VSX_LXVL(lxvll, 1)
389#undef VSX_LXVL
390
391#define VSX_STXVL(name, lj) \
392void helper_##name(CPUPPCState *env, target_ulong addr, \
393 target_ulong xt_num, target_ulong rb) \
394{ \
395 int i; \
396 ppc_vsr_t xt; \
397 target_ulong nb = GET_NB(rb); \
398 \
399 if (!nb) { \
400 return; \
401 } \
402 getVSR(xt_num, &xt, env); \
403 nb = (nb >= 16) ? 16 : nb; \
404 if (msr_le && !lj) { \
405 for (i = 16; i > 16 - nb; i--) { \
406 cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \
407 addr = addr_add(env, addr, 1); \
408 } \
409 } else { \
410 for (i = 0; i < nb; i++) { \
411 cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \
412 addr = addr_add(env, addr, 1); \
413 } \
414 } \
415}
416
417VSX_STXVL(stxvl, 0)
418VSX_STXVL(stxvll, 1)
419#undef VSX_STXVL
420#undef GET_NB
421#endif
422
423#undef HI_IDX
424#undef LO_IDX
425
426void helper_tbegin(CPUPPCState *env)
427{
428
429
430
431
432
433
434
435
436 env->spr[SPR_TEXASR] =
437 (1ULL << TEXASR_FAILURE_PERSISTENT) |
438 (1ULL << TEXASR_NESTING_OVERFLOW) |
439 (msr_hv << TEXASR_PRIVILEGE_HV) |
440 (msr_pr << TEXASR_PRIVILEGE_PR) |
441 (1ULL << TEXASR_FAILURE_SUMMARY) |
442 (1ULL << TEXASR_TFIAR_EXACT);
443 env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
444 env->spr[SPR_TFHAR] = env->nip + 4;
445 env->crf[0] = 0xB;
446}
447