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19#include "qemu/osdep.h"
20#include "cpu.h"
21#include "exec/helper-proto.h"
22#include "exec/exec-all.h"
23#include "exec/cpu_ldst.h"
24#include "fpu/softfloat.h"
25
26#ifndef CONFIG_USER_ONLY
27
28void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
29 MMUAccessType access_type,
30 int mmu_idx, uintptr_t retaddr)
31{
32 switch (access_type) {
33 case MMU_INST_FETCH:
34 case MMU_DATA_LOAD:
35 cs->exception_index = 0x0e0;
36 break;
37 case MMU_DATA_STORE:
38 cs->exception_index = 0x100;
39 break;
40 }
41 cpu_loop_exit_restore(cs, retaddr);
42}
43
44void tlb_fill(CPUState *cs, target_ulong addr, int size,
45 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
46{
47 int ret;
48
49 ret = superh_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
50 if (ret) {
51
52 cpu_loop_exit_restore(cs, retaddr);
53 }
54}
55
56#endif
57
58void helper_ldtlb(CPUSH4State *env)
59{
60#ifdef CONFIG_USER_ONLY
61 SuperHCPU *cpu = sh_env_get_cpu(env);
62
63
64 cpu_abort(CPU(cpu), "Unhandled ldtlb");
65#else
66 cpu_load_tlb(env);
67#endif
68}
69
70static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
71 uintptr_t retaddr)
72{
73 CPUState *cs = CPU(sh_env_get_cpu(env));
74
75 cs->exception_index = index;
76 cpu_loop_exit_restore(cs, retaddr);
77}
78
79void helper_raise_illegal_instruction(CPUSH4State *env)
80{
81 raise_exception(env, 0x180, 0);
82}
83
84void helper_raise_slot_illegal_instruction(CPUSH4State *env)
85{
86 raise_exception(env, 0x1a0, 0);
87}
88
89void helper_raise_fpu_disable(CPUSH4State *env)
90{
91 raise_exception(env, 0x800, 0);
92}
93
94void helper_raise_slot_fpu_disable(CPUSH4State *env)
95{
96 raise_exception(env, 0x820, 0);
97}
98
99void helper_debug(CPUSH4State *env)
100{
101 raise_exception(env, EXCP_DEBUG, 0);
102}
103
104void helper_sleep(CPUSH4State *env)
105{
106 CPUState *cs = CPU(sh_env_get_cpu(env));
107
108 cs->halted = 1;
109 env->in_sleep = 1;
110 raise_exception(env, EXCP_HLT, 0);
111}
112
113void helper_trapa(CPUSH4State *env, uint32_t tra)
114{
115 env->tra = tra << 2;
116 raise_exception(env, 0x160, 0);
117}
118
119void helper_exclusive(CPUSH4State *env)
120{
121
122 cpu_loop_exit_atomic(ENV_GET_CPU(env), 0);
123}
124
125void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
126{
127 if (cpu_sh4_is_cached (env, address))
128 {
129 memory_content *r = g_new(memory_content, 1);
130
131 r->address = address;
132 r->value = value;
133 r->next = NULL;
134
135 *(env->movcal_backup_tail) = r;
136 env->movcal_backup_tail = &(r->next);
137 }
138}
139
140void helper_discard_movcal_backup(CPUSH4State *env)
141{
142 memory_content *current = env->movcal_backup;
143
144 while(current)
145 {
146 memory_content *next = current->next;
147 g_free(current);
148 env->movcal_backup = current = next;
149 if (current == NULL)
150 env->movcal_backup_tail = &(env->movcal_backup);
151 }
152}
153
154void helper_ocbi(CPUSH4State *env, uint32_t address)
155{
156 memory_content **current = &(env->movcal_backup);
157 while (*current)
158 {
159 uint32_t a = (*current)->address;
160 if ((a & ~0x1F) == (address & ~0x1F))
161 {
162 memory_content *next = (*current)->next;
163 cpu_stl_data(env, a, (*current)->value);
164
165 if (next == NULL)
166 {
167 env->movcal_backup_tail = current;
168 }
169
170 g_free(*current);
171 *current = next;
172 break;
173 }
174 }
175}
176
177void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
178{
179 int64_t res;
180
181 res = ((uint64_t) env->mach << 32) | env->macl;
182 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
183 env->mach = (res >> 32) & 0xffffffff;
184 env->macl = res & 0xffffffff;
185 if (env->sr & (1u << SR_S)) {
186 if (res < 0)
187 env->mach |= 0xffff0000;
188 else
189 env->mach &= 0x00007fff;
190 }
191}
192
193void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
194{
195 int64_t res;
196
197 res = ((uint64_t) env->mach << 32) | env->macl;
198 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
199 env->mach = (res >> 32) & 0xffffffff;
200 env->macl = res & 0xffffffff;
201 if (env->sr & (1u << SR_S)) {
202 if (res < -0x80000000) {
203 env->mach = 1;
204 env->macl = 0x80000000;
205 } else if (res > 0x000000007fffffff) {
206 env->mach = 1;
207 env->macl = 0x7fffffff;
208 }
209 }
210}
211
212void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
213{
214 env->fpscr = val & FPSCR_MASK;
215 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
216 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
217 } else {
218 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
219 }
220 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
221}
222
223static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
224{
225 int xcpt, cause, enable;
226
227 xcpt = get_float_exception_flags(&env->fp_status);
228
229
230 env->fpscr &= ~FPSCR_CAUSE_MASK;
231
232 if (unlikely(xcpt)) {
233 if (xcpt & float_flag_invalid) {
234 env->fpscr |= FPSCR_CAUSE_V;
235 }
236 if (xcpt & float_flag_divbyzero) {
237 env->fpscr |= FPSCR_CAUSE_Z;
238 }
239 if (xcpt & float_flag_overflow) {
240 env->fpscr |= FPSCR_CAUSE_O;
241 }
242 if (xcpt & float_flag_underflow) {
243 env->fpscr |= FPSCR_CAUSE_U;
244 }
245 if (xcpt & float_flag_inexact) {
246 env->fpscr |= FPSCR_CAUSE_I;
247 }
248
249
250 env->fpscr |= (env->fpscr & FPSCR_CAUSE_MASK)
251 >> (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
252
253
254 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
255 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
256 if (cause & enable) {
257 raise_exception(env, 0x120, retaddr);
258 }
259 }
260}
261
262float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
263{
264 set_float_exception_flags(0, &env->fp_status);
265 t0 = float32_add(t0, t1, &env->fp_status);
266 update_fpscr(env, GETPC());
267 return t0;
268}
269
270float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
271{
272 set_float_exception_flags(0, &env->fp_status);
273 t0 = float64_add(t0, t1, &env->fp_status);
274 update_fpscr(env, GETPC());
275 return t0;
276}
277
278uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
279{
280 int relation;
281
282 set_float_exception_flags(0, &env->fp_status);
283 relation = float32_compare(t0, t1, &env->fp_status);
284 update_fpscr(env, GETPC());
285 return relation == float_relation_equal;
286}
287
288uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
289{
290 int relation;
291
292 set_float_exception_flags(0, &env->fp_status);
293 relation = float64_compare(t0, t1, &env->fp_status);
294 update_fpscr(env, GETPC());
295 return relation == float_relation_equal;
296}
297
298uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
299{
300 int relation;
301
302 set_float_exception_flags(0, &env->fp_status);
303 relation = float32_compare(t0, t1, &env->fp_status);
304 update_fpscr(env, GETPC());
305 return relation == float_relation_greater;
306}
307
308uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
309{
310 int relation;
311
312 set_float_exception_flags(0, &env->fp_status);
313 relation = float64_compare(t0, t1, &env->fp_status);
314 update_fpscr(env, GETPC());
315 return relation == float_relation_greater;
316}
317
318float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
319{
320 float64 ret;
321 set_float_exception_flags(0, &env->fp_status);
322 ret = float32_to_float64(t0, &env->fp_status);
323 update_fpscr(env, GETPC());
324 return ret;
325}
326
327float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
328{
329 float32 ret;
330 set_float_exception_flags(0, &env->fp_status);
331 ret = float64_to_float32(t0, &env->fp_status);
332 update_fpscr(env, GETPC());
333 return ret;
334}
335
336float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
337{
338 set_float_exception_flags(0, &env->fp_status);
339 t0 = float32_div(t0, t1, &env->fp_status);
340 update_fpscr(env, GETPC());
341 return t0;
342}
343
344float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
345{
346 set_float_exception_flags(0, &env->fp_status);
347 t0 = float64_div(t0, t1, &env->fp_status);
348 update_fpscr(env, GETPC());
349 return t0;
350}
351
352float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
353{
354 float32 ret;
355 set_float_exception_flags(0, &env->fp_status);
356 ret = int32_to_float32(t0, &env->fp_status);
357 update_fpscr(env, GETPC());
358 return ret;
359}
360
361float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
362{
363 float64 ret;
364 set_float_exception_flags(0, &env->fp_status);
365 ret = int32_to_float64(t0, &env->fp_status);
366 update_fpscr(env, GETPC());
367 return ret;
368}
369
370float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
371{
372 set_float_exception_flags(0, &env->fp_status);
373 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
374 update_fpscr(env, GETPC());
375 return t0;
376}
377
378float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
379{
380 set_float_exception_flags(0, &env->fp_status);
381 t0 = float32_mul(t0, t1, &env->fp_status);
382 update_fpscr(env, GETPC());
383 return t0;
384}
385
386float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
387{
388 set_float_exception_flags(0, &env->fp_status);
389 t0 = float64_mul(t0, t1, &env->fp_status);
390 update_fpscr(env, GETPC());
391 return t0;
392}
393
394float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
395{
396 set_float_exception_flags(0, &env->fp_status);
397 t0 = float32_sqrt(t0, &env->fp_status);
398 update_fpscr(env, GETPC());
399 return t0;
400}
401
402float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
403{
404 set_float_exception_flags(0, &env->fp_status);
405 t0 = float64_sqrt(t0, &env->fp_status);
406 update_fpscr(env, GETPC());
407 return t0;
408}
409
410float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
411{
412 set_float_exception_flags(0, &env->fp_status);
413
414 t0 = float32_sqrt(t0, &env->fp_status);
415 t0 = float32_div(float32_one, t0, &env->fp_status);
416
417
418
419 if (get_float_exception_flags(&env->fp_status) == 0) {
420 set_float_exception_flags(float_flag_inexact, &env->fp_status);
421 }
422 update_fpscr(env, GETPC());
423 return t0;
424}
425
426float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
427{
428 set_float_exception_flags(0, &env->fp_status);
429 t0 = float32_sub(t0, t1, &env->fp_status);
430 update_fpscr(env, GETPC());
431 return t0;
432}
433
434float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
435{
436 set_float_exception_flags(0, &env->fp_status);
437 t0 = float64_sub(t0, t1, &env->fp_status);
438 update_fpscr(env, GETPC());
439 return t0;
440}
441
442uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
443{
444 uint32_t ret;
445 set_float_exception_flags(0, &env->fp_status);
446 ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
447 update_fpscr(env, GETPC());
448 return ret;
449}
450
451uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
452{
453 uint32_t ret;
454 set_float_exception_flags(0, &env->fp_status);
455 ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
456 update_fpscr(env, GETPC());
457 return ret;
458}
459
460void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
461{
462 int bank, i;
463 float32 r, p;
464
465 bank = (env->sr & FPSCR_FR) ? 16 : 0;
466 r = float32_zero;
467 set_float_exception_flags(0, &env->fp_status);
468
469 for (i = 0 ; i < 4 ; i++) {
470 p = float32_mul(env->fregs[bank + m + i],
471 env->fregs[bank + n + i],
472 &env->fp_status);
473 r = float32_add(r, p, &env->fp_status);
474 }
475 update_fpscr(env, GETPC());
476
477 env->fregs[bank + n + 3] = r;
478}
479
480void helper_ftrv(CPUSH4State *env, uint32_t n)
481{
482 int bank_matrix, bank_vector;
483 int i, j;
484 float32 r[4];
485 float32 p;
486
487 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
488 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
489 set_float_exception_flags(0, &env->fp_status);
490 for (i = 0 ; i < 4 ; i++) {
491 r[i] = float32_zero;
492 for (j = 0 ; j < 4 ; j++) {
493 p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
494 env->fregs[bank_vector + j],
495 &env->fp_status);
496 r[i] = float32_add(r[i], p, &env->fp_status);
497 }
498 }
499 update_fpscr(env, GETPC());
500
501 for (i = 0 ; i < 4 ; i++) {
502 env->fregs[bank_vector + i] = r[i];
503 }
504}
505