LXR qemu/target/tilegx/cpu.c

   1/*
   2 * QEMU TILE-Gx CPU
   3 *
   4 *  Copyright (c) 2015 Chen Gang
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "qemu-common.h"
  25#include "hw/qdev-properties.h"
  26#include "linux-user/syscall_defs.h"
  27
  28static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  29                                  fprintf_function cpu_fprintf, int flags)
  30{
  31    static const char * const reg_names[TILEGX_R_COUNT] = {
  32         "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  33         "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  34        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  35        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  36        "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  37        "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  38        "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  39    };
  40
  41    TileGXCPU *cpu = TILEGX_CPU(cs);
  42    CPUTLGState *env = &cpu->env;
  43    int i;
  44
  45    for (i = 0; i < TILEGX_R_COUNT; i++) {
  46        cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  47                    reg_names[i], env->regs[i],
  48                    (i % 4) == 3 ? "\n" : " ");
  49    }
  50    cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  51                env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  52}
  53
  54static ObjectClass *tilegx_cpu_class_by_name(const char *cpu_model)
  55{
  56    return object_class_by_name(TYPE_TILEGX_CPU);
  57}
  58
  59static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  60{
  61    TileGXCPU *cpu = TILEGX_CPU(cs);
  62
  63    cpu->env.pc = value;
  64}
  65
  66static bool tilegx_cpu_has_work(CPUState *cs)
  67{
  68    return true;
  69}
  70
  71static void tilegx_cpu_reset(CPUState *s)
  72{
  73    TileGXCPU *cpu = TILEGX_CPU(s);
  74    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  75    CPUTLGState *env = &cpu->env;
  76
  77    tcc->parent_reset(s);
  78
  79    memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
  80}
  81
  82static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  83{
  84    CPUState *cs = CPU(dev);
  85    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  86    Error *local_err = NULL;
  87
  88    cpu_exec_realizefn(cs, &local_err);
  89    if (local_err != NULL) {
  90        error_propagate(errp, local_err);
  91        return;
  92    }
  93
  94    cpu_reset(cs);
  95    qemu_init_vcpu(cs);
  96
  97    tcc->parent_realize(dev, errp);
  98}
  99
 100static void tilegx_cpu_initfn(Object *obj)
 101{
 102    CPUState *cs = CPU(obj);
 103    TileGXCPU *cpu = TILEGX_CPU(obj);
 104    CPUTLGState *env = &cpu->env;
 105
 106    cs->env_ptr = env;
 107}
 108
 109static void tilegx_cpu_do_interrupt(CPUState *cs)
 110{
 111    cs->exception_index = -1;
 112}
 113
 114static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
 115                                       int rw, int mmu_idx)
 116{
 117    TileGXCPU *cpu = TILEGX_CPU(cs);
 118
 119    /* The sigcode field will be filled in by do_signal in main.c.  */
 120    cs->exception_index = TILEGX_EXCP_SIGNAL;
 121    cpu->env.excaddr = address;
 122    cpu->env.signo = TARGET_SIGSEGV;
 123    cpu->env.sigcode = 0;
 124
 125    return 1;
 126}
 127
 128static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 129{
 130    if (interrupt_request & CPU_INTERRUPT_HARD) {
 131        tilegx_cpu_do_interrupt(cs);
 132        return true;
 133    }
 134    return false;
 135}
 136
 137static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 138{
 139    DeviceClass *dc = DEVICE_CLASS(oc);
 140    CPUClass *cc = CPU_CLASS(oc);
 141    TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 142
 143    device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
 144                                    &tcc->parent_realize);
 145
 146    tcc->parent_reset = cc->reset;
 147    cc->reset = tilegx_cpu_reset;
 148
 149    cc->class_by_name = tilegx_cpu_class_by_name;
 150    cc->has_work = tilegx_cpu_has_work;
 151    cc->do_interrupt = tilegx_cpu_do_interrupt;
 152    cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 153    cc->dump_state = tilegx_cpu_dump_state;
 154    cc->set_pc = tilegx_cpu_set_pc;
 155    cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 156    cc->gdb_num_core_regs = 0;
 157    cc->tcg_initialize = tilegx_tcg_init;
 158}
 159
 160static const TypeInfo tilegx_cpu_type_info = {
 161    .name = TYPE_TILEGX_CPU,
 162    .parent = TYPE_CPU,
 163    .instance_size = sizeof(TileGXCPU),
 164    .instance_init = tilegx_cpu_initfn,
 165    .class_size = sizeof(TileGXCPUClass),
 166    .class_init = tilegx_cpu_class_init,
 167};
 168
 169static void tilegx_cpu_register_types(void)
 170{
 171    type_register_static(&tilegx_cpu_type_info);
 172}
 173
 174type_init(tilegx_cpu_register_types)
 175