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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "cpu.h"
34#include "qemu-common.h"
35#include "migration/vmstate.h"
36
37
38static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
39{
40 XtensaCPU *cpu = XTENSA_CPU(cs);
41
42 cpu->env.pc = value;
43}
44
45static bool xtensa_cpu_has_work(CPUState *cs)
46{
47#ifndef CONFIG_USER_ONLY
48 XtensaCPU *cpu = XTENSA_CPU(cs);
49
50 return !cpu->env.runstall && cpu->env.pending_irq_level;
51#else
52 return true;
53#endif
54}
55
56
57static void xtensa_cpu_reset(CPUState *s)
58{
59 XtensaCPU *cpu = XTENSA_CPU(s);
60 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
61 CPUXtensaState *env = &cpu->env;
62
63 xcc->parent_reset(s);
64
65 env->exception_taken = 0;
66 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
67 env->sregs[LITBASE] &= ~1;
68#ifndef CONFIG_USER_ONLY
69 env->sregs[PS] = xtensa_option_enabled(env->config,
70 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
71 env->pending_irq_level = 0;
72#else
73 env->sregs[PS] =
74 (xtensa_option_enabled(env->config,
75 XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
76 PS_UM | (3 << PS_RING_SHIFT);
77#endif
78 env->sregs[VECBASE] = env->config->vecbase;
79 env->sregs[IBREAKENABLE] = 0;
80 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
81 env->sregs[CACHEATTR] = 0x22222222;
82 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
83 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
84 env->sregs[CONFIGID0] = env->config->configid[0];
85 env->sregs[CONFIGID1] = env->config->configid[1];
86
87#ifndef CONFIG_USER_ONLY
88 reset_mmu(env);
89 s->halted = env->runstall;
90#endif
91}
92
93static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
94{
95 ObjectClass *oc;
96 char *typename;
97
98 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
99 oc = object_class_by_name(typename);
100 g_free(typename);
101 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
102 object_class_is_abstract(oc)) {
103 return NULL;
104 }
105 return oc;
106}
107
108static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
109{
110 XtensaCPU *cpu = XTENSA_CPU(cs);
111
112 info->private_data = cpu->env.config->isa;
113 info->print_insn = print_insn_xtensa;
114}
115
116static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
117{
118 CPUState *cs = CPU(dev);
119 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
120 Error *local_err = NULL;
121
122#ifndef CONFIG_USER_ONLY
123 xtensa_irq_init(&XTENSA_CPU(dev)->env);
124#endif
125
126 cpu_exec_realizefn(cs, &local_err);
127 if (local_err != NULL) {
128 error_propagate(errp, local_err);
129 return;
130 }
131
132 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
133
134 qemu_init_vcpu(cs);
135
136 xcc->parent_realize(dev, errp);
137}
138
139static void xtensa_cpu_initfn(Object *obj)
140{
141 CPUState *cs = CPU(obj);
142 XtensaCPU *cpu = XTENSA_CPU(obj);
143 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
144 CPUXtensaState *env = &cpu->env;
145
146 cs->env_ptr = env;
147 env->config = xcc->config;
148
149#ifndef CONFIG_USER_ONLY
150 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
151 env->system_er = g_malloc(sizeof(*env->system_er));
152 memory_region_init_io(env->system_er, obj, NULL, env, "er",
153 UINT64_C(0x100000000));
154 address_space_init(env->address_space_er, env->system_er, "ER");
155#endif
156}
157
158static const VMStateDescription vmstate_xtensa_cpu = {
159 .name = "cpu",
160 .unmigratable = 1,
161};
162
163static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
164{
165 DeviceClass *dc = DEVICE_CLASS(oc);
166 CPUClass *cc = CPU_CLASS(oc);
167 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
168
169 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
170 &xcc->parent_realize);
171
172 xcc->parent_reset = cc->reset;
173 cc->reset = xtensa_cpu_reset;
174
175 cc->class_by_name = xtensa_cpu_class_by_name;
176 cc->has_work = xtensa_cpu_has_work;
177 cc->do_interrupt = xtensa_cpu_do_interrupt;
178 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
179 cc->dump_state = xtensa_cpu_dump_state;
180 cc->set_pc = xtensa_cpu_set_pc;
181 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
182 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
183 cc->gdb_stop_before_watchpoint = true;
184#ifdef CONFIG_USER_ONLY
185 cc->handle_mmu_fault = xtensa_cpu_handle_mmu_fault;
186#else
187 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
188 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
189 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
190#endif
191 cc->debug_excp_handler = xtensa_breakpoint_handler;
192 cc->disas_set_info = xtensa_cpu_disas_set_info;
193 cc->tcg_initialize = xtensa_translate_init;
194 dc->vmsd = &vmstate_xtensa_cpu;
195}
196
197static const TypeInfo xtensa_cpu_type_info = {
198 .name = TYPE_XTENSA_CPU,
199 .parent = TYPE_CPU,
200 .instance_size = sizeof(XtensaCPU),
201 .instance_init = xtensa_cpu_initfn,
202 .abstract = true,
203 .class_size = sizeof(XtensaCPUClass),
204 .class_init = xtensa_cpu_class_init,
205};
206
207static void xtensa_cpu_register_types(void)
208{
209 type_register_static(&xtensa_cpu_type_info);
210}
211
212type_init(xtensa_cpu_register_types)
213