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25#include "qemu/osdep.h"
26#include <getopt.h>
27
28#include "libqtest.h"
29#include "libqos/libqos-pc.h"
30#include "libqos/ahci.h"
31#include "libqos/pci-pc.h"
32
33#include "qemu-common.h"
34#include "qapi/qmp/qdict.h"
35#include "qemu/host-utils.h"
36
37#include "hw/pci/pci_ids.h"
38#include "hw/pci/pci_regs.h"
39
40
41#define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
42#define TEST_IMAGE_SIZE_MB_SMALL 64
43
44
45static char tmp_path[] = "/tmp/qtest.XXXXXX";
46static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
47static char mig_socket[] = "/tmp/qtest-migration.XXXXXX";
48static bool ahci_pedantic;
49static const char *imgfmt;
50static unsigned test_image_size_mb;
51
52
53static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
54static void ahci_test_pci_spec(AHCIQState *ahci);
55static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
56 uint8_t offset);
57static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
58static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
59static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
60
61
62
63static uint64_t mb_to_sectors(uint64_t image_size_mb)
64{
65 return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE;
66}
67
68static void string_bswap16(uint16_t *s, size_t bytes)
69{
70 g_assert_cmphex((bytes & 1), ==, 0);
71 bytes /= 2;
72
73 while (bytes--) {
74 *s = bswap16(*s);
75 s++;
76 }
77}
78
79
80
81
82static void verify_state(AHCIQState *ahci, uint64_t hba_old)
83{
84 int i, j;
85 uint32_t ahci_fingerprint;
86 uint64_t hba_base;
87 AHCICommandHeader cmd;
88
89 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
90 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
91
92
93 if (!ahci->enabled) {
94 return;
95 }
96
97 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
98 g_assert_cmphex(hba_base, ==, hba_old);
99
100 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap);
101 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2);
102
103 for (i = 0; i < 32; i++) {
104 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==,
105 ahci->port[i].fb);
106 g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==,
107 ahci->port[i].clb);
108 for (j = 0; j < 32; j++) {
109 ahci_get_command_header(ahci, i, j, &cmd);
110 g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]);
111 g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]);
112 }
113 }
114}
115
116static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
117{
118 QOSState *tmp = to->parent;
119 QPCIDevice *dev = to->dev;
120 char *uri_local = NULL;
121 uint64_t hba_old;
122
123 if (uri == NULL) {
124 uri_local = g_strdup_printf("%s%s", "unix:", mig_socket);
125 uri = uri_local;
126 }
127
128 hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5);
129
130
131 migrate(from->parent, to->parent, uri);
132
133
134
135
136 memcpy(to, from, sizeof(AHCIQState));
137 to->parent = tmp;
138 to->dev = dev;
139
140 tmp = from->parent;
141 dev = from->dev;
142 memset(from, 0x00, sizeof(AHCIQState));
143 from->parent = tmp;
144 from->dev = dev;
145
146 verify_state(to, hba_old);
147 g_free(uri_local);
148}
149
150
151
152
153
154
155static AHCIQState *ahci_vboot(const char *cli, va_list ap)
156{
157 AHCIQState *s;
158
159 s = g_new0(AHCIQState, 1);
160 s->parent = qtest_pc_vboot(cli, ap);
161 global_qtest = s->parent->qts;
162 alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
163
164
165 s->dev = get_ahci_device(s->parent->qts, &s->fingerprint);
166
167 return s;
168}
169
170
171
172
173static AHCIQState *ahci_boot(const char *cli, ...)
174{
175 AHCIQState *s;
176 va_list ap;
177
178 if (cli) {
179 va_start(ap, cli);
180 s = ahci_vboot(cli, ap);
181 va_end(ap);
182 } else {
183 cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
184 ",format=%s"
185 " -M q35 "
186 "-device ide-hd,drive=drive0 "
187 "-global ide-hd.ver=%s";
188 s = ahci_boot(cli, tmp_path, "testdisk", imgfmt, "version");
189 }
190
191 return s;
192}
193
194
195
196
197static void ahci_shutdown(AHCIQState *ahci)
198{
199 QOSState *qs = ahci->parent;
200
201 set_context(qs);
202 ahci_clean_mem(ahci);
203 free_ahci_device(ahci->dev);
204 g_free(ahci);
205 qtest_shutdown(qs);
206}
207
208
209
210
211
212static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
213{
214 AHCIQState *ahci;
215 va_list ap;
216 uint16_t buff[256];
217 uint8_t port;
218 uint8_t hello;
219
220 if (cli) {
221 va_start(ap, cli);
222 ahci = ahci_vboot(cli, ap);
223 va_end(ap);
224 } else {
225 ahci = ahci_boot(NULL);
226 }
227
228 ahci_pci_enable(ahci);
229 ahci_hba_enable(ahci);
230
231 port = ahci_port_select(ahci);
232 ahci_port_clear(ahci, port);
233 if (is_atapi(ahci, port)) {
234 hello = CMD_PACKET_ID;
235 } else {
236 hello = CMD_IDENTIFY;
237 }
238 ahci_io(ahci, port, hello, &buff, sizeof(buff), 0);
239
240 return ahci;
241}
242
243
244
245
246
247
248static void ahci_test_pci_spec(AHCIQState *ahci)
249{
250 uint8_t datab;
251 uint16_t data;
252 uint32_t datal;
253
254
255 data = qpci_config_readw(ahci->dev, PCI_COMMAND);
256 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
257 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
258 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);
259 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE);
260 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
261 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);
262 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
263 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
264 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
265 ASSERT_BIT_CLEAR(data, 0xF800);
266
267 data = qpci_config_readw(ahci->dev, PCI_STATUS);
268 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);
269 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
270 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);
271 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);
272 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
273 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
274 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
275 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
276 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
277 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
278
279
280 datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
281 if (ahci_pedantic) {
282
283
284 ASSERT_BIT_CLEAR(datal, 0xFF);
285 }
286
287
288 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
289 if (PCI_SCC(datal) == 0x01) {
290
291 ASSERT_BIT_SET(0x80000000, datal);
292 ASSERT_BIT_CLEAR(0x60000000, datal);
293 } else if (PCI_SCC(datal) == 0x04) {
294
295 g_assert_cmphex(PCI_PI(datal), ==, 0);
296 } else if (PCI_SCC(datal) == 0x06) {
297
298 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
299 } else {
300 g_assert_not_reached();
301 }
302
303 datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
304 g_assert_cmphex(datab, ==, 0);
305
306 datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
307 g_assert_cmphex(datab, ==, 0);
308
309
310 datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
311 ASSERT_BIT_CLEAR(datab, 0x7F);
312
313
314 datab = qpci_config_readb(ahci->dev, PCI_BIST);
315 ASSERT_BIT_CLEAR(datab, 0x7F);
316
317
318 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
319 g_assert_cmphex(datal, ==, 0);
320
321 qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
322 datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
323
324
325 ASSERT_BIT_CLEAR(datal, 0xFF);
326
327
328 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
329
330 ASSERT_BIT_CLEAR(datal, ~0xFF);
331 g_assert_cmphex(datal, !=, 0);
332
333
334 data = qpci_config_readw(ahci->dev, datal);
335
336 switch (ahci->fingerprint) {
337 case AHCI_INTEL_ICH9:
338
339 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
340 break;
341 default:
342
343 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
344 }
345
346 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
347
348
349 datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
350 g_assert_cmphex(datal, ==, 0);
351
352
353 datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
354 g_assert_cmphex(datab, ==, 0);
355}
356
357
358
359
360static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
361 uint8_t offset)
362{
363 uint8_t cid = header & 0xFF;
364 uint8_t next = header >> 8;
365
366 g_test_message("CID: %02x; next: %02x", cid, next);
367
368 switch (cid) {
369 case PCI_CAP_ID_PM:
370 ahci_test_pmcap(ahci, offset);
371 break;
372 case PCI_CAP_ID_MSI:
373 ahci_test_msicap(ahci, offset);
374 break;
375 case PCI_CAP_ID_SATA:
376 ahci_test_satacap(ahci, offset);
377 break;
378
379 default:
380 g_test_message("Unknown CAP 0x%02x", cid);
381 }
382
383 if (next) {
384 ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
385 }
386}
387
388
389
390
391static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
392{
393 uint16_t dataw;
394 uint32_t datal;
395
396 g_test_message("Verifying SATACAP");
397
398
399 dataw = qpci_config_readw(ahci->dev, offset + 2);
400 g_assert_cmphex(dataw, ==, 0x10);
401
402
403 datal = qpci_config_readw(ahci->dev, offset + 4);
404
405 switch (datal & 0x0F) {
406 case 0x04:
407 case 0x05:
408 case 0x06:
409 case 0x07:
410 case 0x08:
411 case 0x09:
412 case 0x0F:
413 break;
414 default:
415
416 g_assert_not_reached();
417 }
418
419
420 g_assert_cmphex((datal >> 24), ==, 0x00);
421}
422
423
424
425
426static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
427{
428 uint16_t dataw;
429 uint32_t datal;
430
431 g_test_message("Verifying MSICAP");
432
433 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
434 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
435 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
436 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
437
438 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
439 g_assert_cmphex(datal, ==, 0);
440
441 if (dataw & PCI_MSI_FLAGS_64BIT) {
442 g_test_message("MSICAP is 64bit");
443 datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
444 g_assert_cmphex(datal, ==, 0);
445 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
446 g_assert_cmphex(dataw, ==, 0);
447 } else {
448 g_test_message("MSICAP is 32bit");
449 dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
450 g_assert_cmphex(dataw, ==, 0);
451 }
452}
453
454
455
456
457static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
458{
459 uint16_t dataw;
460
461 g_test_message("Verifying PMCAP");
462
463 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
464 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
465 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
466 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
467 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
468
469 dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
470 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
471 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
472 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
473 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
474}
475
476static void ahci_test_hba_spec(AHCIQState *ahci)
477{
478 unsigned i;
479 uint32_t reg;
480 uint32_t ports;
481 uint8_t nports_impl;
482 uint8_t maxports;
483
484 g_assert(ahci != NULL);
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
508 ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
509
510
511 reg = ahci_rreg(ahci, AHCI_GHC);
512 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
513 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
514 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
515 if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
516 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
517 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
518 } else {
519 g_test_message("Supports AHCI/Legacy mix.");
520 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
521 }
522
523
524 reg = ahci_rreg(ahci, AHCI_IS);
525 g_assert_cmphex(reg, ==, 0);
526
527
528 ports = ahci_rreg(ahci, AHCI_PI);
529
530 g_assert_cmphex(ports, !=, 0);
531
532 nports_impl = ctpopl(ports);
533 g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
534
535
536
537
538 g_assert_cmphex(ahci->barsize, >, 0);
539 maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
540
541 g_assert_cmphex((reg >> maxports), ==, 0);
542
543
544 reg = ahci_rreg(ahci, AHCI_VS);
545 switch (reg) {
546 case AHCI_VERSION_0_95:
547 case AHCI_VERSION_1_0:
548 case AHCI_VERSION_1_1:
549 case AHCI_VERSION_1_2:
550 case AHCI_VERSION_1_3:
551 break;
552 default:
553 g_assert_not_reached();
554 }
555
556
557 reg = ahci_rreg(ahci, AHCI_CCCCTL);
558 if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
559 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
560 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
561 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
562 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
563 } else {
564 g_assert_cmphex(reg, ==, 0);
565 }
566
567
568 reg = ahci_rreg(ahci, AHCI_CCCPORTS);
569
570 g_assert_cmphex(reg, ==, 0);
571
572
573 reg = ahci_rreg(ahci, AHCI_EMLOC);
574 if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
575 g_assert_cmphex(reg, ==, 0);
576 }
577
578
579 reg = ahci_rreg(ahci, AHCI_EMCTL);
580 if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
581 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
582 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
583 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
584 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
585 } else {
586 g_assert_cmphex(reg, ==, 0);
587 }
588
589
590 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
591 ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
592
593
594 reg = ahci_rreg(ahci, AHCI_BOHC);
595 g_assert_cmphex(reg, ==, 0);
596
597
598 g_test_message("Verifying HBA reserved area is empty.");
599 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
600 reg = ahci_rreg(ahci, i);
601 g_assert_cmphex(reg, ==, 0);
602 }
603
604
605 if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
606 g_test_message("Verifying HBA/NVMHCI area is empty.");
607 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
608 reg = ahci_rreg(ahci, i);
609 g_assert_cmphex(reg, ==, 0);
610 }
611 }
612
613
614 g_test_message("Verifying HBA/Vendor area is empty.");
615 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
616 reg = ahci_rreg(ahci, i);
617 g_assert_cmphex(reg, ==, 0);
618 }
619
620
621 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
622 if (BITSET(ports, 0x1)) {
623 g_test_message("Testing port %u for spec", i);
624 ahci_test_port_spec(ahci, i);
625 } else {
626 uint16_t j;
627 uint16_t low = AHCI_PORTS + (32 * i);
628 uint16_t high = AHCI_PORTS + (32 * (i + 1));
629 g_test_message("Asserting unimplemented port %u "
630 "(reg [%u-%u]) is empty.",
631 i, low, high - 1);
632 for (j = low; j < high; ++j) {
633 reg = ahci_rreg(ahci, j);
634 g_assert_cmphex(reg, ==, 0);
635 }
636 }
637 }
638}
639
640
641
642
643static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
644{
645 uint32_t reg;
646 unsigned i;
647
648
649 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
650 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
651
652
653 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
654 reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
655 g_assert_cmphex(reg, ==, 0);
656 }
657
658
659 reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
660 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
661
662
663 if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
664 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
665 g_assert_cmphex(reg, ==, 0);
666 }
667
668
669 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
670 g_assert_cmphex(reg, ==, 0);
671
672
673 reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
674 g_assert_cmphex(reg, ==, 0);
675
676
677 reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
678 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
679 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
680 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
681 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
682 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
683 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA);
684 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE);
685 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
686 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
687 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);
688 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);
689 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
690
691 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
692 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
693 }
694
695 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
696 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
697 }
698
699 if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
700 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
701 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
702 }
703
704 if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
705 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
706 }
707
708 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
709
710 if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
711 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
712 }
713
714
715 reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
716 g_assert_cmphex(reg, ==, 0);
717
718
719 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
720
721
722 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
723 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
724 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
725 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
726 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
727 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
728 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
729
730
731
732
733
734
735
736
737 reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
738 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
739
740
741
742
743 reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
744 g_assert_cmphex(reg, ==, 0);
745
746
747 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
748 g_assert_cmphex(reg, ==, 0);
749
750
751 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
752 g_assert_cmphex(reg, ==, 0);
753
754
755 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
756 g_assert_cmphex(reg, ==, 0);
757
758
759 reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
760 g_assert_cmphex(reg, ==, 0);
761
762
763 reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
764 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
765 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
766 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
767 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
768 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
769 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
770 if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
771
772 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
773 }
774
775
776 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
777 reg = ahci_px_rreg(ahci, port, i);
778 g_assert_cmphex(reg, ==, 0);
779 }
780
781
782 for (i = AHCI_PX_VS; i < 32; ++i) {
783 reg = ahci_px_rreg(ahci, port, i);
784 if (reg) {
785 g_test_message("INFO: Vendor register %u non-empty", i);
786 }
787 }
788}
789
790
791
792
793
794static void ahci_test_identify(AHCIQState *ahci)
795{
796 uint16_t buff[256];
797 unsigned px;
798 int rc;
799 uint16_t sect_size;
800 const size_t buffsize = 512;
801
802 g_assert(ahci != NULL);
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826 px = ahci_port_select(ahci);
827 g_test_message("Selected port %u for test", px);
828
829
830 ahci_port_clear(ahci, px);
831
832
833 ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
834
835
836
837
838
839
840 string_bswap16(&buff[10], 20);
841 rc = memcmp(&buff[10], "testdisk ", 20);
842 g_assert_cmphex(rc, ==, 0);
843
844 string_bswap16(&buff[23], 8);
845 rc = memcmp(&buff[23], "version ", 8);
846 g_assert_cmphex(rc, ==, 0);
847
848 sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
849 g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
850}
851
852static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
853 uint64_t sector, uint8_t read_cmd,
854 uint8_t write_cmd)
855{
856 uint64_t ptr;
857 uint8_t port;
858 unsigned char *tx = g_malloc(bufsize);
859 unsigned char *rx = g_malloc0(bufsize);
860
861 g_assert(ahci != NULL);
862
863
864 port = ahci_port_select(ahci);
865 ahci_port_clear(ahci, port);
866
867
868
869 ptr = ahci_alloc(ahci, bufsize);
870 g_assert(ptr);
871
872
873 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
874 bufwrite(ptr, tx, bufsize);
875
876
877 ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
878 qmemset(ptr, 0x00, bufsize);
879 ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
880
881
882 bufread(ptr, rx, bufsize);
883 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
884
885 ahci_free(ahci, ptr);
886 g_free(tx);
887 g_free(rx);
888}
889
890static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
891{
892 uint8_t port;
893
894
895 port = ahci_port_select(ahci);
896 ahci_port_clear(ahci, port);
897
898 ahci_io(ahci, port, ide_cmd, NULL, 0, 0);
899
900 return port;
901}
902
903static void ahci_test_flush(AHCIQState *ahci)
904{
905 ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
906}
907
908static void ahci_test_max(AHCIQState *ahci)
909{
910 RegD2HFIS *d2h = g_malloc0(0x20);
911 uint64_t nsect;
912 uint8_t port;
913 uint8_t cmd;
914 uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1;
915
916 if (config_sect > 0xFFFFFF) {
917 cmd = CMD_READ_MAX_EXT;
918 } else {
919 cmd = CMD_READ_MAX;
920 }
921
922 port = ahci_test_nondata(ahci, cmd);
923 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
924 nsect = (uint64_t)d2h->lba_hi[2] << 40 |
925 (uint64_t)d2h->lba_hi[1] << 32 |
926 (uint64_t)d2h->lba_hi[0] << 24 |
927 (uint64_t)d2h->lba_lo[2] << 16 |
928 (uint64_t)d2h->lba_lo[1] << 8 |
929 (uint64_t)d2h->lba_lo[0];
930
931 g_assert_cmphex(nsect, ==, config_sect);
932 g_free(d2h);
933}
934
935
936
937
938
939
940
941
942
943static void test_sanity(void)
944{
945 AHCIQState *ahci;
946 ahci = ahci_boot(NULL);
947 ahci_shutdown(ahci);
948}
949
950
951
952
953
954static void test_pci_spec(void)
955{
956 AHCIQState *ahci;
957 ahci = ahci_boot(NULL);
958 ahci_test_pci_spec(ahci);
959 ahci_shutdown(ahci);
960}
961
962
963
964
965
966static void test_pci_enable(void)
967{
968 AHCIQState *ahci;
969 ahci = ahci_boot(NULL);
970 ahci_pci_enable(ahci);
971 ahci_shutdown(ahci);
972}
973
974
975
976
977
978static void test_hba_spec(void)
979{
980 AHCIQState *ahci;
981
982 ahci = ahci_boot(NULL);
983 ahci_pci_enable(ahci);
984 ahci_test_hba_spec(ahci);
985 ahci_shutdown(ahci);
986}
987
988
989
990
991
992static void test_hba_enable(void)
993{
994 AHCIQState *ahci;
995
996 ahci = ahci_boot(NULL);
997 ahci_pci_enable(ahci);
998 ahci_hba_enable(ahci);
999 ahci_shutdown(ahci);
1000}
1001
1002
1003
1004
1005
1006static void test_identify(void)
1007{
1008 AHCIQState *ahci;
1009
1010 ahci = ahci_boot_and_enable(NULL);
1011 ahci_test_identify(ahci);
1012 ahci_shutdown(ahci);
1013}
1014
1015
1016
1017
1018
1019
1020
1021static void test_dma_fragmented(void)
1022{
1023 AHCIQState *ahci;
1024 AHCICommand *cmd;
1025 uint8_t px;
1026 size_t bufsize = 4096;
1027 unsigned char *tx = g_malloc(bufsize);
1028 unsigned char *rx = g_malloc0(bufsize);
1029 uint64_t ptr;
1030
1031 ahci = ahci_boot_and_enable(NULL);
1032 px = ahci_port_select(ahci);
1033 ahci_port_clear(ahci, px);
1034
1035
1036 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1037
1038
1039 ptr = guest_alloc(ahci->parent->alloc, bufsize);
1040 g_assert(ptr);
1041 bufwrite(ptr, tx, bufsize);
1042
1043 cmd = ahci_command_create(CMD_WRITE_DMA);
1044 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1045 ahci_command_commit(ahci, cmd, px);
1046 ahci_command_issue(ahci, cmd);
1047 ahci_command_verify(ahci, cmd);
1048 ahci_command_free(cmd);
1049
1050 cmd = ahci_command_create(CMD_READ_DMA);
1051 ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
1052 ahci_command_commit(ahci, cmd, px);
1053 ahci_command_issue(ahci, cmd);
1054 ahci_command_verify(ahci, cmd);
1055 ahci_command_free(cmd);
1056
1057
1058 bufread(ptr, rx, bufsize);
1059 guest_free(ahci->parent->alloc, ptr);
1060
1061 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1062
1063 ahci_shutdown(ahci);
1064
1065 g_free(rx);
1066 g_free(tx);
1067}
1068
1069
1070
1071
1072
1073static void make_dirty(AHCIQState* ahci, uint8_t port)
1074{
1075 uint64_t ptr;
1076 unsigned bufsize = 512;
1077
1078 ptr = ahci_alloc(ahci, bufsize);
1079 g_assert(ptr);
1080
1081 ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1);
1082 ahci_free(ahci, ptr);
1083}
1084
1085static void test_flush(void)
1086{
1087 AHCIQState *ahci;
1088 uint8_t port;
1089
1090 ahci = ahci_boot_and_enable(NULL);
1091
1092 port = ahci_port_select(ahci);
1093 ahci_port_clear(ahci, port);
1094
1095 make_dirty(ahci, port);
1096
1097 ahci_test_flush(ahci);
1098 ahci_shutdown(ahci);
1099}
1100
1101static void test_flush_retry(void)
1102{
1103 AHCIQState *ahci;
1104 AHCICommand *cmd;
1105 uint8_t port;
1106
1107 prepare_blkdebug_script(debug_path, "flush_to_disk");
1108 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1109 "format=%s,cache=writeback,"
1110 "rerror=stop,werror=stop "
1111 "-M q35 "
1112 "-device ide-hd,drive=drive0 ",
1113 debug_path,
1114 tmp_path, imgfmt);
1115
1116 port = ahci_port_select(ahci);
1117 ahci_port_clear(ahci, port);
1118
1119
1120 make_dirty(ahci, port);
1121
1122
1123 cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0);
1124 ahci_guest_io_resume(ahci, cmd);
1125
1126 ahci_shutdown(ahci);
1127}
1128
1129
1130
1131
1132static void test_migrate_sanity(void)
1133{
1134 AHCIQState *src, *dst;
1135 char *uri = g_strdup_printf("unix:%s", mig_socket);
1136
1137 src = ahci_boot("-m 384 -M q35 "
1138 "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt);
1139 dst = ahci_boot("-m 384 -M q35 "
1140 "-drive if=ide,file=%s,format=%s "
1141 "-incoming %s", tmp_path, imgfmt, uri);
1142
1143 ahci_migrate(src, dst, uri);
1144
1145 ahci_shutdown(src);
1146 ahci_shutdown(dst);
1147 g_free(uri);
1148}
1149
1150
1151
1152
1153static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write)
1154{
1155 AHCIQState *src, *dst;
1156 uint8_t px;
1157 size_t bufsize = 4096;
1158 unsigned char *tx = g_malloc(bufsize);
1159 unsigned char *rx = g_malloc0(bufsize);
1160 char *uri = g_strdup_printf("unix:%s", mig_socket);
1161
1162 src = ahci_boot_and_enable("-m 384 -M q35 "
1163 "-drive if=ide,format=%s,file=%s ",
1164 imgfmt, tmp_path);
1165 dst = ahci_boot("-m 384 -M q35 "
1166 "-drive if=ide,format=%s,file=%s "
1167 "-incoming %s", imgfmt, tmp_path, uri);
1168
1169 set_context(src->parent);
1170
1171
1172 px = ahci_port_select(src);
1173 ahci_port_clear(src, px);
1174
1175
1176 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1177
1178
1179 ahci_io(src, px, cmd_write, tx, bufsize, 0);
1180 ahci_migrate(src, dst, uri);
1181 ahci_io(dst, px, cmd_read, rx, bufsize, 0);
1182
1183
1184 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1185
1186 ahci_shutdown(src);
1187 ahci_shutdown(dst);
1188 g_free(rx);
1189 g_free(tx);
1190 g_free(uri);
1191}
1192
1193static void test_migrate_dma(void)
1194{
1195 ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA);
1196}
1197
1198static void test_migrate_ncq(void)
1199{
1200 ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1201}
1202
1203
1204
1205
1206
1207
1208
1209
1210static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write)
1211{
1212 AHCIQState *ahci;
1213 uint8_t port;
1214 size_t bufsize = 4096;
1215 unsigned char *tx = g_malloc(bufsize);
1216 unsigned char *rx = g_malloc0(bufsize);
1217 uint64_t ptr;
1218 AHCICommand *cmd;
1219
1220 prepare_blkdebug_script(debug_path, "write_aio");
1221
1222 ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1223 "format=%s,cache=writeback,"
1224 "rerror=stop,werror=stop "
1225 "-M q35 "
1226 "-device ide-hd,drive=drive0 ",
1227 debug_path,
1228 tmp_path, imgfmt);
1229
1230
1231 port = ahci_port_select(ahci);
1232 ahci_port_clear(ahci, port);
1233
1234
1235 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1236 ptr = ahci_alloc(ahci, bufsize);
1237 g_assert(ptr);
1238 memwrite(ptr, tx, bufsize);
1239
1240
1241 cmd = ahci_guest_io_halt(ahci, port, cmd_write,
1242 ptr, bufsize, 0);
1243
1244
1245 ahci_guest_io_resume(ahci, cmd);
1246 ahci_free(ahci, ptr);
1247
1248
1249 ahci_io(ahci, port, cmd_read, rx, bufsize, 0);
1250 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1251
1252
1253 ahci_shutdown(ahci);
1254 g_free(rx);
1255 g_free(tx);
1256}
1257
1258static void test_halted_dma(void)
1259{
1260 ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA);
1261}
1262
1263static void test_halted_ncq(void)
1264{
1265 ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1266}
1267
1268
1269
1270
1271
1272
1273
1274
1275static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write)
1276{
1277 AHCIQState *src, *dst;
1278 uint8_t port;
1279 size_t bufsize = 4096;
1280 unsigned char *tx = g_malloc(bufsize);
1281 unsigned char *rx = g_malloc0(bufsize);
1282 uint64_t ptr;
1283 AHCICommand *cmd;
1284 char *uri = g_strdup_printf("unix:%s", mig_socket);
1285
1286 prepare_blkdebug_script(debug_path, "write_aio");
1287
1288 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1289 "format=%s,cache=writeback,"
1290 "rerror=stop,werror=stop "
1291 "-M q35 "
1292 "-device ide-hd,drive=drive0 ",
1293 debug_path,
1294 tmp_path, imgfmt);
1295
1296 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1297 "format=%s,cache=writeback,"
1298 "rerror=stop,werror=stop "
1299 "-M q35 "
1300 "-device ide-hd,drive=drive0 "
1301 "-incoming %s",
1302 tmp_path, imgfmt, uri);
1303
1304 set_context(src->parent);
1305
1306
1307 port = ahci_port_select(src);
1308 ahci_port_clear(src, port);
1309 generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
1310
1311
1312 ptr = ahci_alloc(src, bufsize);
1313 g_assert(ptr);
1314 memwrite(ptr, tx, bufsize);
1315
1316
1317 cmd = ahci_guest_io_halt(src, port, cmd_write,
1318 ptr, bufsize, 0);
1319 ahci_migrate(src, dst, uri);
1320 ahci_guest_io_resume(dst, cmd);
1321 ahci_free(dst, ptr);
1322
1323
1324 ahci_io(dst, port, cmd_read, rx, bufsize, 0);
1325
1326
1327 g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
1328
1329
1330 ahci_shutdown(src);
1331 ahci_shutdown(dst);
1332 g_free(rx);
1333 g_free(tx);
1334 g_free(uri);
1335}
1336
1337static void test_migrate_halted_dma(void)
1338{
1339 ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA);
1340}
1341
1342static void test_migrate_halted_ncq(void)
1343{
1344 ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED);
1345}
1346
1347
1348
1349
1350static void test_flush_migrate(void)
1351{
1352 AHCIQState *src, *dst;
1353 AHCICommand *cmd;
1354 uint8_t px;
1355 const char *s;
1356 char *uri = g_strdup_printf("unix:%s", mig_socket);
1357
1358 prepare_blkdebug_script(debug_path, "flush_to_disk");
1359
1360 src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1361 "cache=writeback,rerror=stop,werror=stop,"
1362 "format=%s "
1363 "-M q35 "
1364 "-device ide-hd,drive=drive0 ",
1365 debug_path, tmp_path, imgfmt);
1366 dst = ahci_boot("-drive file=%s,if=none,id=drive0,"
1367 "cache=writeback,rerror=stop,werror=stop,"
1368 "format=%s "
1369 "-M q35 "
1370 "-device ide-hd,drive=drive0 "
1371 "-incoming %s", tmp_path, imgfmt, uri);
1372
1373 set_context(src->parent);
1374
1375 px = ahci_port_select(src);
1376 ahci_port_clear(src, px);
1377
1378
1379 make_dirty(src, px);
1380
1381
1382 cmd = ahci_command_create(CMD_FLUSH_CACHE);
1383 ahci_command_commit(src, cmd, px);
1384 ahci_command_issue_async(src, cmd);
1385 qmp_eventwait("STOP");
1386
1387
1388 ahci_migrate(src, dst, uri);
1389
1390
1391 s = "{'execute':'cont' }";
1392 qmp_async(s);
1393 qmp_eventwait("RESUME");
1394 ahci_command_wait(dst, cmd);
1395 ahci_command_verify(dst, cmd);
1396
1397 ahci_command_free(cmd);
1398 ahci_shutdown(src);
1399 ahci_shutdown(dst);
1400 g_free(uri);
1401}
1402
1403static void test_max(void)
1404{
1405 AHCIQState *ahci;
1406
1407 ahci = ahci_boot_and_enable(NULL);
1408 ahci_test_max(ahci);
1409 ahci_shutdown(ahci);
1410}
1411
1412static void test_reset(void)
1413{
1414 AHCIQState *ahci;
1415 int i;
1416
1417 ahci = ahci_boot(NULL);
1418 ahci_test_pci_spec(ahci);
1419 ahci_pci_enable(ahci);
1420
1421 for (i = 0; i < 2; i++) {
1422 ahci_test_hba_spec(ahci);
1423 ahci_hba_enable(ahci);
1424 ahci_test_identify(ahci);
1425 ahci_test_io_rw_simple(ahci, 4096, 0,
1426 CMD_READ_DMA_EXT,
1427 CMD_WRITE_DMA_EXT);
1428 ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
1429 ahci_clean_mem(ahci);
1430 }
1431
1432 ahci_shutdown(ahci);
1433}
1434
1435static void test_ncq_simple(void)
1436{
1437 AHCIQState *ahci;
1438
1439 ahci = ahci_boot_and_enable(NULL);
1440 ahci_test_io_rw_simple(ahci, 4096, 0,
1441 READ_FPDMA_QUEUED,
1442 WRITE_FPDMA_QUEUED);
1443 ahci_shutdown(ahci);
1444}
1445
1446static int prepare_iso(size_t size, unsigned char **buf, char **name)
1447{
1448 char cdrom_path[] = "/tmp/qtest.iso.XXXXXX";
1449 unsigned char *patt;
1450 ssize_t ret;
1451 int fd = mkstemp(cdrom_path);
1452
1453 g_assert(buf);
1454 g_assert(name);
1455 patt = g_malloc(size);
1456
1457
1458 generate_pattern(patt, size, ATAPI_SECTOR_SIZE);
1459 ret = write(fd, patt, size);
1460 g_assert(ret == size);
1461
1462 *name = g_strdup(cdrom_path);
1463 *buf = patt;
1464 return fd;
1465}
1466
1467static void remove_iso(int fd, char *name)
1468{
1469 unlink(name);
1470 g_free(name);
1471 close(fd);
1472}
1473
1474static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd,
1475 const AHCIOpts *opts)
1476{
1477 unsigned char *tx = opts->opaque;
1478 unsigned char *rx;
1479
1480 if (!opts->size) {
1481 return 0;
1482 }
1483
1484 rx = g_malloc0(opts->size);
1485 bufread(opts->buffer, rx, opts->size);
1486 g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0);
1487 g_free(rx);
1488
1489 return 0;
1490}
1491
1492static void ahci_test_cdrom(int nsectors, bool dma, uint8_t cmd,
1493 bool override_bcl, uint16_t bcl)
1494{
1495 AHCIQState *ahci;
1496 unsigned char *tx;
1497 char *iso;
1498 int fd;
1499 AHCIOpts opts = {
1500 .size = (ATAPI_SECTOR_SIZE * nsectors),
1501 .atapi = true,
1502 .atapi_dma = dma,
1503 .post_cb = ahci_cb_cmp_buff,
1504 .set_bcl = override_bcl,
1505 .bcl = bcl,
1506 };
1507 uint64_t iso_size = ATAPI_SECTOR_SIZE * (nsectors + 1);
1508
1509
1510 fd = prepare_iso(iso_size, &tx, &iso);
1511 opts.opaque = tx;
1512
1513
1514 ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1515 "-M q35 "
1516 "-device ide-cd,drive=drive0 ", iso);
1517
1518
1519 ahci_exec(ahci, ahci_port_select(ahci), cmd, &opts);
1520
1521
1522 g_free(tx);
1523 ahci_shutdown(ahci);
1524 remove_iso(fd, iso);
1525}
1526
1527static void ahci_test_cdrom_read10(int nsectors, bool dma)
1528{
1529 ahci_test_cdrom(nsectors, dma, CMD_ATAPI_READ_10, false, 0);
1530}
1531
1532static void test_cdrom_dma(void)
1533{
1534 ahci_test_cdrom_read10(1, true);
1535}
1536
1537static void test_cdrom_dma_multi(void)
1538{
1539 ahci_test_cdrom_read10(3, true);
1540}
1541
1542static void test_cdrom_pio(void)
1543{
1544 ahci_test_cdrom_read10(1, false);
1545}
1546
1547static void test_cdrom_pio_multi(void)
1548{
1549 ahci_test_cdrom_read10(3, false);
1550}
1551
1552
1553
1554static void test_atapi_bcl(void)
1555{
1556 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD, true, 0);
1557}
1558
1559
1560static void atapi_wait_tray(bool open)
1561{
1562 QDict *rsp = qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1563 QDict *data = qdict_get_qdict(rsp, "data");
1564 if (open) {
1565 g_assert(qdict_get_bool(data, "tray-open"));
1566 } else {
1567 g_assert(!qdict_get_bool(data, "tray-open"));
1568 }
1569 qobject_unref(rsp);
1570}
1571
1572static void test_atapi_tray(void)
1573{
1574 AHCIQState *ahci;
1575 unsigned char *tx;
1576 char *iso;
1577 int fd;
1578 uint8_t port, sense, asc;
1579 uint64_t iso_size = ATAPI_SECTOR_SIZE;
1580 QDict *rsp;
1581
1582 fd = prepare_iso(iso_size, &tx, &iso);
1583 ahci = ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1584 "-M q35 "
1585 "-device ide-cd,id=cd0,drive=drive0 ", iso);
1586 port = ahci_port_select(ahci);
1587
1588 ahci_atapi_eject(ahci, port);
1589 atapi_wait_tray(true);
1590
1591 ahci_atapi_load(ahci, port);
1592 atapi_wait_tray(false);
1593
1594
1595 qmp_async("{'execute': 'blockdev-open-tray', "
1596 "'arguments': {'id': 'cd0'}}");
1597 atapi_wait_tray(true);
1598 rsp = qmp_receive();
1599 qobject_unref(rsp);
1600
1601 qmp_discard_response("{'execute': 'blockdev-remove-medium', "
1602 "'arguments': {'id': 'cd0'}}");
1603
1604
1605 ahci_atapi_load(ahci, port);
1606 atapi_wait_tray(false);
1607
1608 ahci_atapi_eject(ahci, port);
1609 atapi_wait_tray(true);
1610
1611
1612 qmp_discard_response("{'execute': 'blockdev-add', "
1613 "'arguments': {'node-name': 'node0', "
1614 "'driver': 'raw', "
1615 "'file': { 'driver': 'file', "
1616 "'filename': %s }}}", iso);
1617 qmp_discard_response("{'execute': 'blockdev-insert-medium',"
1618 "'arguments': { 'id': 'cd0', "
1619 "'node-name': 'node0' }}");
1620
1621
1622 qmp_async("{'execute': 'blockdev-close-tray', "
1623 "'arguments': {'id': 'cd0'}}");
1624 atapi_wait_tray(false);
1625 rsp = qmp_receive();
1626 qobject_unref(rsp);
1627
1628
1629 ahci_atapi_test_ready(ahci, port, false, SENSE_NOT_READY);
1630 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1631 g_assert_cmpuint(sense, ==, SENSE_NOT_READY);
1632 g_assert_cmpuint(asc, ==, ASC_MEDIUM_NOT_PRESENT);
1633
1634 ahci_atapi_test_ready(ahci, port, false, SENSE_UNIT_ATTENTION);
1635 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1636 g_assert_cmpuint(sense, ==, SENSE_UNIT_ATTENTION);
1637 g_assert_cmpuint(asc, ==, ASC_MEDIUM_MAY_HAVE_CHANGED);
1638
1639 ahci_atapi_test_ready(ahci, port, true, SENSE_NO_SENSE);
1640 ahci_atapi_get_sense(ahci, port, &sense, &asc);
1641 g_assert_cmpuint(sense, ==, SENSE_NO_SENSE);
1642
1643
1644 ahci_atapi_eject(ahci, port);
1645 atapi_wait_tray(true);
1646
1647 ahci_atapi_load(ahci, port);
1648 atapi_wait_tray(false);
1649
1650
1651 g_free(tx);
1652 ahci_shutdown(ahci);
1653 remove_iso(fd, iso);
1654}
1655
1656
1657
1658
1659enum BuffLen {
1660 LEN_BEGIN = 0,
1661 LEN_SIMPLE = LEN_BEGIN,
1662 LEN_DOUBLE,
1663 LEN_LONG,
1664 LEN_SHORT,
1665 NUM_LENGTHS
1666};
1667
1668static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1669 "long", "short" };
1670
1671enum AddrMode {
1672 ADDR_MODE_BEGIN = 0,
1673 ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1674 ADDR_MODE_LBA48,
1675 NUM_ADDR_MODES
1676};
1677
1678static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1679
1680enum IOMode {
1681 MODE_BEGIN = 0,
1682 MODE_PIO = MODE_BEGIN,
1683 MODE_DMA,
1684 NUM_MODES
1685};
1686
1687static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1688
1689enum IOOps {
1690 IO_BEGIN = 0,
1691 IO_READ = IO_BEGIN,
1692 IO_WRITE,
1693 NUM_IO_OPS
1694};
1695
1696enum OffsetType {
1697 OFFSET_BEGIN = 0,
1698 OFFSET_ZERO = OFFSET_BEGIN,
1699 OFFSET_LOW,
1700 OFFSET_HIGH,
1701 NUM_OFFSETS
1702};
1703
1704static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1705
1706typedef struct AHCIIOTestOptions {
1707 enum BuffLen length;
1708 enum AddrMode address_type;
1709 enum IOMode io_type;
1710 enum OffsetType offset;
1711} AHCIIOTestOptions;
1712
1713static uint64_t offset_sector(enum OffsetType ofst,
1714 enum AddrMode addr_type,
1715 uint64_t buffsize)
1716{
1717 uint64_t ceil;
1718 uint64_t nsectors;
1719
1720 switch (ofst) {
1721 case OFFSET_ZERO:
1722 return 0;
1723 case OFFSET_LOW:
1724 return 1;
1725 case OFFSET_HIGH:
1726 ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1727 ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1);
1728 nsectors = buffsize / AHCI_SECTOR_SIZE;
1729 return ceil - nsectors + 1;
1730 default:
1731 g_assert_not_reached();
1732 }
1733}
1734
1735
1736
1737
1738static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1739 [MODE_PIO] = {
1740 [ADDR_MODE_LBA28] = {
1741 [IO_READ] = CMD_READ_PIO,
1742 [IO_WRITE] = CMD_WRITE_PIO },
1743 [ADDR_MODE_LBA48] = {
1744 [IO_READ] = CMD_READ_PIO_EXT,
1745 [IO_WRITE] = CMD_WRITE_PIO_EXT }
1746 },
1747 [MODE_DMA] = {
1748 [ADDR_MODE_LBA28] = {
1749 [IO_READ] = CMD_READ_DMA,
1750 [IO_WRITE] = CMD_WRITE_DMA },
1751 [ADDR_MODE_LBA48] = {
1752 [IO_READ] = CMD_READ_DMA_EXT,
1753 [IO_WRITE] = CMD_WRITE_DMA_EXT }
1754 }
1755};
1756
1757
1758
1759
1760
1761static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1762 unsigned bufsize, uint64_t sector)
1763{
1764 AHCIQState *ahci;
1765
1766 ahci = ahci_boot_and_enable(NULL);
1767 ahci_test_io_rw_simple(ahci, bufsize, sector,
1768 io_cmds[dma][lba48][IO_READ],
1769 io_cmds[dma][lba48][IO_WRITE]);
1770 ahci_shutdown(ahci);
1771}
1772
1773
1774
1775
1776static void test_io_interface(gconstpointer opaque)
1777{
1778 AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1779 unsigned bufsize;
1780 uint64_t sector;
1781
1782 switch (opts->length) {
1783 case LEN_SIMPLE:
1784 bufsize = 4096;
1785 break;
1786 case LEN_DOUBLE:
1787 bufsize = 8192;
1788 break;
1789 case LEN_LONG:
1790 bufsize = 4096 * 64;
1791 break;
1792 case LEN_SHORT:
1793 bufsize = 512;
1794 break;
1795 default:
1796 g_assert_not_reached();
1797 }
1798
1799 sector = offset_sector(opts->offset, opts->address_type, bufsize);
1800 test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1801 g_free(opts);
1802 return;
1803}
1804
1805static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1806 enum BuffLen len, enum OffsetType offset)
1807{
1808 char *name;
1809 AHCIIOTestOptions *opts;
1810
1811 opts = g_new(AHCIIOTestOptions, 1);
1812 opts->length = len;
1813 opts->address_type = addr;
1814 opts->io_type = type;
1815 opts->offset = offset;
1816
1817 name = g_strdup_printf("ahci/io/%s/%s/%s/%s",
1818 io_mode_str[type],
1819 addr_mode_str[addr],
1820 buff_len_str[len],
1821 offset_str[offset]);
1822
1823 if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) &&
1824 (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) {
1825 g_test_message("%s: skipped; test image too small", name);
1826 g_free(opts);
1827 g_free(name);
1828 return;
1829 }
1830
1831 qtest_add_data_func(name, opts, test_io_interface);
1832 g_free(name);
1833}
1834
1835
1836
1837int main(int argc, char **argv)
1838{
1839 const char *arch;
1840 int ret;
1841 int fd;
1842 int c;
1843 int i, j, k, m;
1844
1845 static struct option long_options[] = {
1846 {"pedantic", no_argument, 0, 'p' },
1847 {0, 0, 0, 0},
1848 };
1849
1850
1851 g_test_init(&argc, &argv, NULL);
1852
1853 while (1) {
1854 c = getopt_long(argc, argv, "", long_options, NULL);
1855 if (c == -1) {
1856 break;
1857 }
1858 switch (c) {
1859 case -1:
1860 break;
1861 case 'p':
1862 ahci_pedantic = 1;
1863 break;
1864 default:
1865 fprintf(stderr, "Unrecognized ahci_test option.\n");
1866 g_assert_not_reached();
1867 }
1868 }
1869
1870
1871 arch = qtest_get_arch();
1872 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1873 g_test_message("Skipping test for non-x86");
1874 return 0;
1875 }
1876
1877
1878 fd = mkstemp(tmp_path);
1879 g_assert(fd >= 0);
1880 if (have_qemu_img()) {
1881 imgfmt = "qcow2";
1882 test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE;
1883 mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE);
1884 } else {
1885 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1886 "skipping LBA48 high-sector tests");
1887 imgfmt = "raw";
1888 test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL;
1889 ret = ftruncate(fd, test_image_size_mb * 1024 * 1024);
1890 g_assert(ret == 0);
1891 }
1892 close(fd);
1893
1894
1895 fd = mkstemp(debug_path);
1896 g_assert(fd >= 0);
1897 close(fd);
1898
1899
1900 fd = mkstemp(mig_socket);
1901 g_assert(fd >= 0);
1902 close(fd);
1903
1904
1905 qtest_add_func("/ahci/sanity", test_sanity);
1906 qtest_add_func("/ahci/pci_spec", test_pci_spec);
1907 qtest_add_func("/ahci/pci_enable", test_pci_enable);
1908 qtest_add_func("/ahci/hba_spec", test_hba_spec);
1909 qtest_add_func("/ahci/hba_enable", test_hba_enable);
1910 qtest_add_func("/ahci/identify", test_identify);
1911
1912 for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1913 for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1914 for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1915 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1916 create_ahci_io_test(i, j, k, m);
1917 }
1918 }
1919 }
1920 }
1921
1922 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1923
1924 qtest_add_func("/ahci/flush/simple", test_flush);
1925 qtest_add_func("/ahci/flush/retry", test_flush_retry);
1926 qtest_add_func("/ahci/flush/migrate", test_flush_migrate);
1927
1928 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity);
1929 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma);
1930 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma);
1931 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma);
1932
1933 qtest_add_func("/ahci/max", test_max);
1934 qtest_add_func("/ahci/reset", test_reset);
1935
1936 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple);
1937 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq);
1938 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq);
1939 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq);
1940
1941 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma);
1942 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi);
1943 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio);
1944 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi);
1945
1946 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl);
1947 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray);
1948
1949 ret = g_test_run();
1950
1951
1952 unlink(tmp_path);
1953 unlink(debug_path);
1954 unlink(mig_socket);
1955
1956 return ret;
1957}
1958