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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "hw/sysbus.h"
34#include "hw/arm/arm.h"
35#include "hw/arm/primecell.h"
36#include "hw/arm/virt.h"
37#include "hw/vfio/vfio-calxeda-xgmac.h"
38#include "hw/vfio/vfio-amd-xgbe.h"
39#include "hw/display/ramfb.h"
40#include "hw/devices.h"
41#include "net/net.h"
42#include "sysemu/device_tree.h"
43#include "sysemu/numa.h"
44#include "sysemu/sysemu.h"
45#include "sysemu/kvm.h"
46#include "hw/compat.h"
47#include "hw/loader.h"
48#include "exec/address-spaces.h"
49#include "qemu/bitops.h"
50#include "qemu/error-report.h"
51#include "hw/pci-host/gpex.h"
52#include "hw/arm/sysbus-fdt.h"
53#include "hw/platform-bus.h"
54#include "hw/arm/fdt.h"
55#include "hw/intc/arm_gic.h"
56#include "hw/intc/arm_gicv3_common.h"
57#include "kvm_arm.h"
58#include "hw/smbios/smbios.h"
59#include "qapi/visitor.h"
60#include "standard-headers/linux/input.h"
61#include "hw/arm/smmuv3.h"
62
63#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
65 void *data) \
66 { \
67 MachineClass *mc = MACHINE_CLASS(oc); \
68 virt_machine_##major##_##minor##_options(mc); \
69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
70 if (latest) { \
71 mc->alias = "virt"; \
72 } \
73 } \
74 static const TypeInfo machvirt_##major##_##minor##_info = { \
75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
76 .parent = TYPE_VIRT_MACHINE, \
77 .instance_init = virt_##major##_##minor##_instance_init, \
78 .class_init = virt_##major##_##minor##_class_init, \
79 }; \
80 static void machvirt_machine_##major##_##minor##_init(void) \
81 { \
82 type_register_static(&machvirt_##major##_##minor##_info); \
83 } \
84 type_init(machvirt_machine_##major##_##minor##_init);
85
86#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
88#define DEFINE_VIRT_MACHINE(major, minor) \
89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
90
91
92
93#define NUM_IRQS 256
94
95#define PLATFORM_BUS_NUM_IRQS 64
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110
111#define RAMLIMIT_GB 255
112#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
113
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125
126static const MemMapEntry a15memmap[] = {
127
128 [VIRT_FLASH] = { 0, 0x08000000 },
129 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
130
131 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
132 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
133 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
134
135 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
136
137 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
138 [VIRT_UART] = { 0x09000000, 0x00001000 },
139 [VIRT_RTC] = { 0x09010000, 0x00001000 },
140 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
141 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
142 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
143 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
144 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
145
146 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
147 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
148 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
149 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
150 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
151 [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
152
153 [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
154 [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 },
155
156 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
157};
158
159static const int a15irqmap[] = {
160 [VIRT_UART] = 1,
161 [VIRT_RTC] = 2,
162 [VIRT_PCIE] = 3,
163 [VIRT_GPIO] = 7,
164 [VIRT_SECURE_UART] = 8,
165 [VIRT_MMIO] = 16,
166 [VIRT_GIC_V2M] = 48,
167 [VIRT_SMMU] = 74,
168 [VIRT_PLATFORM_BUS] = 112,
169};
170
171static const char *valid_cpus[] = {
172 ARM_CPU_TYPE_NAME("cortex-a15"),
173 ARM_CPU_TYPE_NAME("cortex-a53"),
174 ARM_CPU_TYPE_NAME("cortex-a57"),
175 ARM_CPU_TYPE_NAME("host"),
176 ARM_CPU_TYPE_NAME("max"),
177};
178
179static bool cpu_type_valid(const char *cpu)
180{
181 int i;
182
183 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
184 if (strcmp(cpu, valid_cpus[i]) == 0) {
185 return true;
186 }
187 }
188 return false;
189}
190
191static void create_fdt(VirtMachineState *vms)
192{
193 void *fdt = create_device_tree(&vms->fdt_size);
194
195 if (!fdt) {
196 error_report("create_device_tree() failed");
197 exit(1);
198 }
199
200 vms->fdt = fdt;
201
202
203 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
204 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
205 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
206
207
208 qemu_fdt_add_subnode(fdt, "/chosen");
209
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214
215 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
216 qemu_fdt_add_subnode(fdt, "/apb-pclk");
217 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
218 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
219 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
220 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
221 "clk24mhz");
222 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
223
224 if (have_numa_distance) {
225 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
226 uint32_t *matrix = g_malloc0(size);
227 int idx, i, j;
228
229 for (i = 0; i < nb_numa_nodes; i++) {
230 for (j = 0; j < nb_numa_nodes; j++) {
231 idx = (i * nb_numa_nodes + j) * 3;
232 matrix[idx + 0] = cpu_to_be32(i);
233 matrix[idx + 1] = cpu_to_be32(j);
234 matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
235 }
236 }
237
238 qemu_fdt_add_subnode(fdt, "/distance-map");
239 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
240 "numa-distance-map-v1");
241 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
242 matrix, size);
243 g_free(matrix);
244 }
245}
246
247static void fdt_add_timer_nodes(const VirtMachineState *vms)
248{
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267 ARMCPU *armcpu;
268 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
269 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
270
271 if (vmc->claim_edge_triggered_timers) {
272 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
273 }
274
275 if (vms->gic_version == 2) {
276 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
277 GIC_FDT_IRQ_PPI_CPU_WIDTH,
278 (1 << vms->smp_cpus) - 1);
279 }
280
281 qemu_fdt_add_subnode(vms->fdt, "/timer");
282
283 armcpu = ARM_CPU(qemu_get_cpu(0));
284 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
285 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
286 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
287 compat, sizeof(compat));
288 } else {
289 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
290 "arm,armv7-timer");
291 }
292 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
293 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
294 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
295 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
298}
299
300static void fdt_add_cpu_nodes(const VirtMachineState *vms)
301{
302 int cpu;
303 int addr_cells = 1;
304 const MachineState *ms = MACHINE(vms);
305
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318
319 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
320 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
321
322 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
323 addr_cells = 2;
324 break;
325 }
326 }
327
328 qemu_fdt_add_subnode(vms->fdt, "/cpus");
329 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
330 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
331
332 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
333 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
334 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
335 CPUState *cs = CPU(armcpu);
336
337 qemu_fdt_add_subnode(vms->fdt, nodename);
338 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
339 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
340 armcpu->dtb_compatible);
341
342 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
343 && vms->smp_cpus > 1) {
344 qemu_fdt_setprop_string(vms->fdt, nodename,
345 "enable-method", "psci");
346 }
347
348 if (addr_cells == 2) {
349 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
350 armcpu->mp_affinity);
351 } else {
352 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
353 armcpu->mp_affinity);
354 }
355
356 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
357 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
358 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
359 }
360
361 g_free(nodename);
362 }
363}
364
365static void fdt_add_its_gic_node(VirtMachineState *vms)
366{
367 char *nodename;
368
369 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
370 nodename = g_strdup_printf("/intc/its@%" PRIx64,
371 vms->memmap[VIRT_GIC_ITS].base);
372 qemu_fdt_add_subnode(vms->fdt, nodename);
373 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
374 "arm,gic-v3-its");
375 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
376 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
377 2, vms->memmap[VIRT_GIC_ITS].base,
378 2, vms->memmap[VIRT_GIC_ITS].size);
379 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
380 g_free(nodename);
381}
382
383static void fdt_add_v2m_gic_node(VirtMachineState *vms)
384{
385 char *nodename;
386
387 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
388 vms->memmap[VIRT_GIC_V2M].base);
389 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
390 qemu_fdt_add_subnode(vms->fdt, nodename);
391 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
392 "arm,gic-v2m-frame");
393 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
394 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
395 2, vms->memmap[VIRT_GIC_V2M].base,
396 2, vms->memmap[VIRT_GIC_V2M].size);
397 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
398 g_free(nodename);
399}
400
401static void fdt_add_gic_node(VirtMachineState *vms)
402{
403 char *nodename;
404
405 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
406 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
407
408 nodename = g_strdup_printf("/intc@%" PRIx64,
409 vms->memmap[VIRT_GIC_DIST].base);
410 qemu_fdt_add_subnode(vms->fdt, nodename);
411 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
412 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
413 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
414 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
415 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
416 if (vms->gic_version == 3) {
417 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
418
419 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
420 "arm,gic-v3");
421
422 qemu_fdt_setprop_cell(vms->fdt, nodename,
423 "#redistributor-regions", nb_redist_regions);
424
425 if (nb_redist_regions == 1) {
426 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
427 2, vms->memmap[VIRT_GIC_DIST].base,
428 2, vms->memmap[VIRT_GIC_DIST].size,
429 2, vms->memmap[VIRT_GIC_REDIST].base,
430 2, vms->memmap[VIRT_GIC_REDIST].size);
431 } else {
432 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
433 2, vms->memmap[VIRT_GIC_DIST].base,
434 2, vms->memmap[VIRT_GIC_DIST].size,
435 2, vms->memmap[VIRT_GIC_REDIST].base,
436 2, vms->memmap[VIRT_GIC_REDIST].size,
437 2, vms->memmap[VIRT_GIC_REDIST2].base,
438 2, vms->memmap[VIRT_GIC_REDIST2].size);
439 }
440
441 if (vms->virt) {
442 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
443 GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
444 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
445 }
446 } else {
447
448 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
449 "arm,cortex-a15-gic");
450 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
451 2, vms->memmap[VIRT_GIC_DIST].base,
452 2, vms->memmap[VIRT_GIC_DIST].size,
453 2, vms->memmap[VIRT_GIC_CPU].base,
454 2, vms->memmap[VIRT_GIC_CPU].size);
455 }
456
457 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
458 g_free(nodename);
459}
460
461static void fdt_add_pmu_nodes(const VirtMachineState *vms)
462{
463 CPUState *cpu;
464 ARMCPU *armcpu;
465 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
466
467 CPU_FOREACH(cpu) {
468 armcpu = ARM_CPU(cpu);
469 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
470 return;
471 }
472 if (kvm_enabled()) {
473 if (kvm_irqchip_in_kernel()) {
474 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
475 }
476 kvm_arm_pmu_init(cpu);
477 }
478 }
479
480 if (vms->gic_version == 2) {
481 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
482 GIC_FDT_IRQ_PPI_CPU_WIDTH,
483 (1 << vms->smp_cpus) - 1);
484 }
485
486 armcpu = ARM_CPU(qemu_get_cpu(0));
487 qemu_fdt_add_subnode(vms->fdt, "/pmu");
488 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
489 const char compat[] = "arm,armv8-pmuv3";
490 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
491 compat, sizeof(compat));
492 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
493 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
494 }
495}
496
497static void create_its(VirtMachineState *vms, DeviceState *gicdev)
498{
499 const char *itsclass = its_class_name();
500 DeviceState *dev;
501
502 if (!itsclass) {
503
504 return;
505 }
506
507 dev = qdev_create(NULL, itsclass);
508
509 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
510 &error_abort);
511 qdev_init_nofail(dev);
512 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
513
514 fdt_add_its_gic_node(vms);
515}
516
517static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
518{
519 int i;
520 int irq = vms->irqmap[VIRT_GIC_V2M];
521 DeviceState *dev;
522
523 dev = qdev_create(NULL, "arm-gicv2m");
524 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
525 qdev_prop_set_uint32(dev, "base-spi", irq);
526 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
527 qdev_init_nofail(dev);
528
529 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
530 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
531 }
532
533 fdt_add_v2m_gic_node(vms);
534}
535
536static void create_gic(VirtMachineState *vms, qemu_irq *pic)
537{
538
539 DeviceState *gicdev;
540 SysBusDevice *gicbusdev;
541 const char *gictype;
542 int type = vms->gic_version, i;
543 uint32_t nb_redist_regions = 0;
544
545 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
546
547 gicdev = qdev_create(NULL, gictype);
548 qdev_prop_set_uint32(gicdev, "revision", type);
549 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
550
551
552
553 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
554 if (!kvm_irqchip_in_kernel()) {
555 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
556 }
557
558 if (type == 3) {
559 uint32_t redist0_capacity =
560 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
561 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
562
563 nb_redist_regions = virt_gicv3_redist_region_count(vms);
564
565 qdev_prop_set_uint32(gicdev, "len-redist-region-count",
566 nb_redist_regions);
567 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
568
569 if (nb_redist_regions == 2) {
570 uint32_t redist1_capacity =
571 vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
572
573 qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
574 MIN(smp_cpus - redist0_count, redist1_capacity));
575 }
576 }
577 qdev_init_nofail(gicdev);
578 gicbusdev = SYS_BUS_DEVICE(gicdev);
579 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
580 if (type == 3) {
581 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
582 if (nb_redist_regions == 2) {
583 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base);
584 }
585 } else {
586 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
587 }
588
589
590
591
592
593 for (i = 0; i < smp_cpus; i++) {
594 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
595 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
596 int irq;
597
598
599
600 const int timer_irq[] = {
601 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
602 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
603 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
604 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
605 };
606
607 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
608 qdev_connect_gpio_out(cpudev, irq,
609 qdev_get_gpio_in(gicdev,
610 ppibase + timer_irq[irq]));
611 }
612
613 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
614 qdev_get_gpio_in(gicdev, ppibase
615 + ARCH_GICV3_MAINT_IRQ));
616 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
617 qdev_get_gpio_in(gicdev, ppibase
618 + VIRTUAL_PMU_IRQ));
619
620 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
621 sysbus_connect_irq(gicbusdev, i + smp_cpus,
622 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
623 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
624 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
625 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
626 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
627 }
628
629 for (i = 0; i < NUM_IRQS; i++) {
630 pic[i] = qdev_get_gpio_in(gicdev, i);
631 }
632
633 fdt_add_gic_node(vms);
634
635 if (type == 3 && vms->its) {
636 create_its(vms, gicdev);
637 } else if (type == 2) {
638 create_v2m(vms, pic);
639 }
640}
641
642static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
643 MemoryRegion *mem, Chardev *chr)
644{
645 char *nodename;
646 hwaddr base = vms->memmap[uart].base;
647 hwaddr size = vms->memmap[uart].size;
648 int irq = vms->irqmap[uart];
649 const char compat[] = "arm,pl011\0arm,primecell";
650 const char clocknames[] = "uartclk\0apb_pclk";
651 DeviceState *dev = qdev_create(NULL, "pl011");
652 SysBusDevice *s = SYS_BUS_DEVICE(dev);
653
654 qdev_prop_set_chr(dev, "chardev", chr);
655 qdev_init_nofail(dev);
656 memory_region_add_subregion(mem, base,
657 sysbus_mmio_get_region(s, 0));
658 sysbus_connect_irq(s, 0, pic[irq]);
659
660 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
661 qemu_fdt_add_subnode(vms->fdt, nodename);
662
663 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
664 compat, sizeof(compat));
665 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
666 2, base, 2, size);
667 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
668 GIC_FDT_IRQ_TYPE_SPI, irq,
669 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
670 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
671 vms->clock_phandle, vms->clock_phandle);
672 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
673 clocknames, sizeof(clocknames));
674
675 if (uart == VIRT_UART) {
676 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
677 } else {
678
679 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
680 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
681 }
682
683 g_free(nodename);
684}
685
686static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
687{
688 char *nodename;
689 hwaddr base = vms->memmap[VIRT_RTC].base;
690 hwaddr size = vms->memmap[VIRT_RTC].size;
691 int irq = vms->irqmap[VIRT_RTC];
692 const char compat[] = "arm,pl031\0arm,primecell";
693
694 sysbus_create_simple("pl031", base, pic[irq]);
695
696 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
697 qemu_fdt_add_subnode(vms->fdt, nodename);
698 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
699 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
700 2, base, 2, size);
701 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
702 GIC_FDT_IRQ_TYPE_SPI, irq,
703 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
704 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
705 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
706 g_free(nodename);
707}
708
709static DeviceState *gpio_key_dev;
710static void virt_powerdown_req(Notifier *n, void *opaque)
711{
712
713 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
714}
715
716static Notifier virt_system_powerdown_notifier = {
717 .notify = virt_powerdown_req
718};
719
720static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
721{
722 char *nodename;
723 DeviceState *pl061_dev;
724 hwaddr base = vms->memmap[VIRT_GPIO].base;
725 hwaddr size = vms->memmap[VIRT_GPIO].size;
726 int irq = vms->irqmap[VIRT_GPIO];
727 const char compat[] = "arm,pl061\0arm,primecell";
728
729 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
730
731 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
732 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
733 qemu_fdt_add_subnode(vms->fdt, nodename);
734 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
735 2, base, 2, size);
736 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
737 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
738 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
739 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
740 GIC_FDT_IRQ_TYPE_SPI, irq,
741 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
742 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
743 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
744 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
745
746 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
747 qdev_get_gpio_in(pl061_dev, 3));
748 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
749 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
750 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
751 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
752
753 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
754 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
755 "label", "GPIO Key Poweroff");
756 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
757 KEY_POWER);
758 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
759 "gpios", phandle, 3, 0);
760
761
762 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
763
764 g_free(nodename);
765}
766
767static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
768{
769 int i;
770 hwaddr size = vms->memmap[VIRT_MMIO].size;
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
800 int irq = vms->irqmap[VIRT_MMIO] + i;
801 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
802
803 sysbus_create_simple("virtio-mmio", base, pic[irq]);
804 }
805
806
807
808
809
810
811
812
813 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
814 char *nodename;
815 int irq = vms->irqmap[VIRT_MMIO] + i;
816 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
817
818 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
819 qemu_fdt_add_subnode(vms->fdt, nodename);
820 qemu_fdt_setprop_string(vms->fdt, nodename,
821 "compatible", "virtio,mmio");
822 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
823 2, base, 2, size);
824 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
825 GIC_FDT_IRQ_TYPE_SPI, irq,
826 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
827 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
828 g_free(nodename);
829 }
830}
831
832static void create_one_flash(const char *name, hwaddr flashbase,
833 hwaddr flashsize, const char *file,
834 MemoryRegion *sysmem)
835{
836
837
838
839 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
840 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
841 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
842 const uint64_t sectorlength = 256 * 1024;
843
844 if (dinfo) {
845 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
846 &error_abort);
847 }
848
849 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
850 qdev_prop_set_uint64(dev, "sector-length", sectorlength);
851 qdev_prop_set_uint8(dev, "width", 4);
852 qdev_prop_set_uint8(dev, "device-width", 2);
853 qdev_prop_set_bit(dev, "big-endian", false);
854 qdev_prop_set_uint16(dev, "id0", 0x89);
855 qdev_prop_set_uint16(dev, "id1", 0x18);
856 qdev_prop_set_uint16(dev, "id2", 0x00);
857 qdev_prop_set_uint16(dev, "id3", 0x00);
858 qdev_prop_set_string(dev, "name", name);
859 qdev_init_nofail(dev);
860
861 memory_region_add_subregion(sysmem, flashbase,
862 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
863
864 if (file) {
865 char *fn;
866 int image_size;
867
868 if (drive_get(IF_PFLASH, 0, 0)) {
869 error_report("The contents of the first flash device may be "
870 "specified with -bios or with -drive if=pflash... "
871 "but you cannot use both options at once");
872 exit(1);
873 }
874 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
875 if (!fn) {
876 error_report("Could not find ROM image '%s'", file);
877 exit(1);
878 }
879 image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
880 g_free(fn);
881 if (image_size < 0) {
882 error_report("Could not load ROM image '%s'", file);
883 exit(1);
884 }
885 }
886}
887
888static void create_flash(const VirtMachineState *vms,
889 MemoryRegion *sysmem,
890 MemoryRegion *secure_sysmem)
891{
892
893
894
895
896
897
898
899
900 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
901 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
902 char *nodename;
903
904 create_one_flash("virt.flash0", flashbase, flashsize,
905 bios_name, secure_sysmem);
906 create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
907 NULL, sysmem);
908
909 if (sysmem == secure_sysmem) {
910
911 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
912 qemu_fdt_add_subnode(vms->fdt, nodename);
913 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
914 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
915 2, flashbase, 2, flashsize,
916 2, flashbase + flashsize, 2, flashsize);
917 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
918 g_free(nodename);
919 } else {
920
921
922
923 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
924 qemu_fdt_add_subnode(vms->fdt, nodename);
925 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
926 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
927 2, flashbase, 2, flashsize);
928 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
929 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
930 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
931 g_free(nodename);
932
933 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
934 qemu_fdt_add_subnode(vms->fdt, nodename);
935 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
936 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
937 2, flashbase + flashsize, 2, flashsize);
938 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
939 g_free(nodename);
940 }
941}
942
943static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
944{
945 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
946 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
947 FWCfgState *fw_cfg;
948 char *nodename;
949
950 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
951 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
952
953 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
954 qemu_fdt_add_subnode(vms->fdt, nodename);
955 qemu_fdt_setprop_string(vms->fdt, nodename,
956 "compatible", "qemu,fw-cfg-mmio");
957 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
958 2, base, 2, size);
959 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
960 g_free(nodename);
961 return fw_cfg;
962}
963
964static void create_pcie_irq_map(const VirtMachineState *vms,
965 uint32_t gic_phandle,
966 int first_irq, const char *nodename)
967{
968 int devfn, pin;
969 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
970 uint32_t *irq_map = full_irq_map;
971
972 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
973 for (pin = 0; pin < 4; pin++) {
974 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
975 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
976 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
977 int i;
978
979 uint32_t map[] = {
980 devfn << 8, 0, 0,
981 pin + 1,
982 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
983
984
985 for (i = 0; i < 10; i++) {
986 irq_map[i] = cpu_to_be32(map[i]);
987 }
988 irq_map += 10;
989 }
990 }
991
992 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
993 full_irq_map, sizeof(full_irq_map));
994
995 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
996 0x1800, 0, 0,
997 0x7 );
998}
999
1000static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1001 PCIBus *bus)
1002{
1003 char *node;
1004 const char compat[] = "arm,smmu-v3";
1005 int irq = vms->irqmap[VIRT_SMMU];
1006 int i;
1007 hwaddr base = vms->memmap[VIRT_SMMU].base;
1008 hwaddr size = vms->memmap[VIRT_SMMU].size;
1009 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1010 DeviceState *dev;
1011
1012 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1013 return;
1014 }
1015
1016 dev = qdev_create(NULL, "arm-smmuv3");
1017
1018 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1019 &error_abort);
1020 qdev_init_nofail(dev);
1021 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1022 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1023 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1024 }
1025
1026 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1027 qemu_fdt_add_subnode(vms->fdt, node);
1028 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1029 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1030
1031 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1032 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1033 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1034 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1035 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1036
1037 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1038 sizeof(irq_names));
1039
1040 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1041 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1042 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1043
1044 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1045
1046 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1047 g_free(node);
1048}
1049
1050static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1051{
1052 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1053 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1054 hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base;
1055 hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
1056 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1057 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1058 hwaddr base_ecam, size_ecam;
1059 hwaddr base = base_mmio;
1060 int nr_pcie_buses;
1061 int irq = vms->irqmap[VIRT_PCIE];
1062 MemoryRegion *mmio_alias;
1063 MemoryRegion *mmio_reg;
1064 MemoryRegion *ecam_alias;
1065 MemoryRegion *ecam_reg;
1066 DeviceState *dev;
1067 char *nodename;
1068 int i, ecam_id;
1069 PCIHostState *pci;
1070
1071 dev = qdev_create(NULL, TYPE_GPEX_HOST);
1072 qdev_init_nofail(dev);
1073
1074 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1075 base_ecam = vms->memmap[ecam_id].base;
1076 size_ecam = vms->memmap[ecam_id].size;
1077 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1078
1079 ecam_alias = g_new0(MemoryRegion, 1);
1080 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1081 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1082 ecam_reg, 0, size_ecam);
1083 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1084
1085
1086
1087
1088
1089
1090 mmio_alias = g_new0(MemoryRegion, 1);
1091 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1092 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1093 mmio_reg, base_mmio, size_mmio);
1094 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1095
1096 if (vms->highmem) {
1097
1098 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1099
1100 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1101 mmio_reg, base_mmio_high, size_mmio_high);
1102 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1103 high_mmio_alias);
1104 }
1105
1106
1107 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1108
1109 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1110 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1111 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1112 }
1113
1114 pci = PCI_HOST_BRIDGE(dev);
1115 if (pci->bus) {
1116 for (i = 0; i < nb_nics; i++) {
1117 NICInfo *nd = &nd_table[i];
1118
1119 if (!nd->model) {
1120 nd->model = g_strdup("virtio");
1121 }
1122
1123 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1124 }
1125 }
1126
1127 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1128 qemu_fdt_add_subnode(vms->fdt, nodename);
1129 qemu_fdt_setprop_string(vms->fdt, nodename,
1130 "compatible", "pci-host-ecam-generic");
1131 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1132 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1133 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1134 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1135 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1136 nr_pcie_buses - 1);
1137 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1138
1139 if (vms->msi_phandle) {
1140 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1141 vms->msi_phandle);
1142 }
1143
1144 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1145 2, base_ecam, 2, size_ecam);
1146
1147 if (vms->highmem) {
1148 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1149 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1150 2, base_pio, 2, size_pio,
1151 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1152 2, base_mmio, 2, size_mmio,
1153 1, FDT_PCI_RANGE_MMIO_64BIT,
1154 2, base_mmio_high,
1155 2, base_mmio_high, 2, size_mmio_high);
1156 } else {
1157 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1158 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1159 2, base_pio, 2, size_pio,
1160 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1161 2, base_mmio, 2, size_mmio);
1162 }
1163
1164 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1165 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1166
1167 if (vms->iommu) {
1168 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1169
1170 create_smmu(vms, pic, pci->bus);
1171
1172 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1173 0x0, vms->iommu_phandle, 0x0, 0x10000);
1174 }
1175
1176 g_free(nodename);
1177}
1178
1179static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1180{
1181 DeviceState *dev;
1182 SysBusDevice *s;
1183 int i;
1184 MemoryRegion *sysmem = get_system_memory();
1185
1186 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1187 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1188 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1189 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1190 qdev_init_nofail(dev);
1191 vms->platform_bus_dev = dev;
1192
1193 s = SYS_BUS_DEVICE(dev);
1194 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1195 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1196 sysbus_connect_irq(s, i, pic[irqn]);
1197 }
1198
1199 memory_region_add_subregion(sysmem,
1200 vms->memmap[VIRT_PLATFORM_BUS].base,
1201 sysbus_mmio_get_region(s, 0));
1202}
1203
1204static void create_secure_ram(VirtMachineState *vms,
1205 MemoryRegion *secure_sysmem)
1206{
1207 MemoryRegion *secram = g_new(MemoryRegion, 1);
1208 char *nodename;
1209 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1210 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1211
1212 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1213 &error_fatal);
1214 memory_region_add_subregion(secure_sysmem, base, secram);
1215
1216 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1217 qemu_fdt_add_subnode(vms->fdt, nodename);
1218 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1219 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1220 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1221 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1222
1223 g_free(nodename);
1224}
1225
1226static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1227{
1228 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1229 bootinfo);
1230
1231 *fdt_size = board->fdt_size;
1232 return board->fdt;
1233}
1234
1235static void virt_build_smbios(VirtMachineState *vms)
1236{
1237 MachineClass *mc = MACHINE_GET_CLASS(vms);
1238 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1239 uint8_t *smbios_tables, *smbios_anchor;
1240 size_t smbios_tables_len, smbios_anchor_len;
1241 const char *product = "QEMU Virtual Machine";
1242
1243 if (!vms->fw_cfg) {
1244 return;
1245 }
1246
1247 if (kvm_enabled()) {
1248 product = "KVM Virtual Machine";
1249 }
1250
1251 smbios_set_defaults("QEMU", product,
1252 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1253 true, SMBIOS_ENTRY_POINT_30);
1254
1255 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
1256 &smbios_anchor, &smbios_anchor_len);
1257
1258 if (smbios_anchor) {
1259 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1260 smbios_tables, smbios_tables_len);
1261 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1262 smbios_anchor, smbios_anchor_len);
1263 }
1264}
1265
1266static
1267void virt_machine_done(Notifier *notifier, void *data)
1268{
1269 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1270 machine_done);
1271 ARMCPU *cpu = ARM_CPU(first_cpu);
1272 struct arm_boot_info *info = &vms->bootinfo;
1273 AddressSpace *as = arm_boot_address_space(cpu, info);
1274
1275
1276
1277
1278
1279
1280
1281
1282 if (info->dtb_filename == NULL) {
1283 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1284 vms->memmap[VIRT_PLATFORM_BUS].base,
1285 vms->memmap[VIRT_PLATFORM_BUS].size,
1286 vms->irqmap[VIRT_PLATFORM_BUS]);
1287 }
1288 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
1289 exit(1);
1290 }
1291
1292 virt_acpi_setup(vms);
1293 virt_build_smbios(vms);
1294}
1295
1296static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1297{
1298 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1299 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1300
1301 if (!vmc->disallow_affinity_adjustment) {
1302
1303
1304
1305
1306
1307
1308
1309
1310 if (vms->gic_version == 3) {
1311 clustersz = GICV3_TARGETLIST_BITS;
1312 } else {
1313 clustersz = GIC_TARGETLIST_BITS;
1314 }
1315 }
1316 return arm_cpu_mp_affinity(idx, clustersz);
1317}
1318
1319static void machvirt_init(MachineState *machine)
1320{
1321 VirtMachineState *vms = VIRT_MACHINE(machine);
1322 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1323 MachineClass *mc = MACHINE_GET_CLASS(machine);
1324 const CPUArchIdList *possible_cpus;
1325 qemu_irq pic[NUM_IRQS];
1326 MemoryRegion *sysmem = get_system_memory();
1327 MemoryRegion *secure_sysmem = NULL;
1328 int n, virt_max_cpus;
1329 MemoryRegion *ram = g_new(MemoryRegion, 1);
1330 bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1331 bool aarch64 = true;
1332
1333
1334
1335
1336 if (vms->gic_version <= 0) {
1337
1338 if (!kvm_enabled()) {
1339 if (vms->gic_version == 0) {
1340 error_report("gic-version=host requires KVM");
1341 exit(1);
1342 } else {
1343
1344 vms->gic_version = 3;
1345 }
1346 } else {
1347 vms->gic_version = kvm_arm_vgic_probe();
1348 if (!vms->gic_version) {
1349 error_report(
1350 "Unable to determine GIC version supported by host");
1351 exit(1);
1352 }
1353 }
1354 }
1355
1356 if (!cpu_type_valid(machine->cpu_type)) {
1357 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1358 exit(1);
1359 }
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371 if (vms->secure && firmware_loaded) {
1372 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1373 } else if (vms->virt) {
1374 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1375 } else {
1376 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1377 }
1378
1379
1380
1381
1382 if (vms->gic_version == 3) {
1383 virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1384 virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1385 } else {
1386 virt_max_cpus = GIC_NCPU;
1387 }
1388
1389 if (max_cpus > virt_max_cpus) {
1390 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1391 "supported by machine 'mach-virt' (%d)",
1392 max_cpus, virt_max_cpus);
1393 exit(1);
1394 }
1395
1396 vms->smp_cpus = smp_cpus;
1397
1398 if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
1399 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
1400 exit(1);
1401 }
1402
1403 if (vms->virt && kvm_enabled()) {
1404 error_report("mach-virt: KVM does not support providing "
1405 "Virtualization extensions to the guest CPU");
1406 exit(1);
1407 }
1408
1409 if (vms->secure) {
1410 if (kvm_enabled()) {
1411 error_report("mach-virt: KVM does not support Security extensions");
1412 exit(1);
1413 }
1414
1415
1416
1417
1418
1419
1420 secure_sysmem = g_new(MemoryRegion, 1);
1421 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1422 UINT64_MAX);
1423 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1424 }
1425
1426 create_fdt(vms);
1427
1428 possible_cpus = mc->possible_cpu_arch_ids(machine);
1429 for (n = 0; n < possible_cpus->len; n++) {
1430 Object *cpuobj;
1431 CPUState *cs;
1432
1433 if (n >= smp_cpus) {
1434 break;
1435 }
1436
1437 cpuobj = object_new(possible_cpus->cpus[n].type);
1438 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1439 "mp-affinity", NULL);
1440
1441 cs = CPU(cpuobj);
1442 cs->cpu_index = n;
1443
1444 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1445 &error_fatal);
1446
1447 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1448
1449 if (!vms->secure) {
1450 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1451 }
1452
1453 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1454 object_property_set_bool(cpuobj, false, "has_el2", NULL);
1455 }
1456
1457 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1458 object_property_set_int(cpuobj, vms->psci_conduit,
1459 "psci-conduit", NULL);
1460
1461
1462 if (n > 0) {
1463 object_property_set_bool(cpuobj, true,
1464 "start-powered-off", NULL);
1465 }
1466 }
1467
1468 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1469 object_property_set_bool(cpuobj, false, "pmu", NULL);
1470 }
1471
1472 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1473 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1474 "reset-cbar", &error_abort);
1475 }
1476
1477 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1478 &error_abort);
1479 if (vms->secure) {
1480 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1481 "secure-memory", &error_abort);
1482 }
1483
1484 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1485 object_unref(cpuobj);
1486 }
1487 fdt_add_timer_nodes(vms);
1488 fdt_add_cpu_nodes(vms);
1489
1490 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1491 machine->ram_size);
1492 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1493
1494 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
1495
1496 create_gic(vms, pic);
1497
1498 fdt_add_pmu_nodes(vms);
1499
1500 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1501
1502 if (vms->secure) {
1503 create_secure_ram(vms, secure_sysmem);
1504 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1505 }
1506
1507 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1508
1509 create_rtc(vms, pic);
1510
1511 create_pcie(vms, pic);
1512
1513 create_gpio(vms, pic);
1514
1515
1516
1517
1518
1519 create_virtio_devices(vms, pic);
1520
1521 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1522 rom_set_fw(vms->fw_cfg);
1523
1524 create_platform_bus(vms, pic);
1525
1526 vms->bootinfo.ram_size = machine->ram_size;
1527 vms->bootinfo.kernel_filename = machine->kernel_filename;
1528 vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1529 vms->bootinfo.initrd_filename = machine->initrd_filename;
1530 vms->bootinfo.nb_cpus = smp_cpus;
1531 vms->bootinfo.board_id = -1;
1532 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1533 vms->bootinfo.get_dtb = machvirt_dtb;
1534 vms->bootinfo.skip_dtb_autoload = true;
1535 vms->bootinfo.firmware_loaded = firmware_loaded;
1536 arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
1537
1538 vms->machine_done.notify = virt_machine_done;
1539 qemu_add_machine_init_done_notifier(&vms->machine_done);
1540}
1541
1542static bool virt_get_secure(Object *obj, Error **errp)
1543{
1544 VirtMachineState *vms = VIRT_MACHINE(obj);
1545
1546 return vms->secure;
1547}
1548
1549static void virt_set_secure(Object *obj, bool value, Error **errp)
1550{
1551 VirtMachineState *vms = VIRT_MACHINE(obj);
1552
1553 vms->secure = value;
1554}
1555
1556static bool virt_get_virt(Object *obj, Error **errp)
1557{
1558 VirtMachineState *vms = VIRT_MACHINE(obj);
1559
1560 return vms->virt;
1561}
1562
1563static void virt_set_virt(Object *obj, bool value, Error **errp)
1564{
1565 VirtMachineState *vms = VIRT_MACHINE(obj);
1566
1567 vms->virt = value;
1568}
1569
1570static bool virt_get_highmem(Object *obj, Error **errp)
1571{
1572 VirtMachineState *vms = VIRT_MACHINE(obj);
1573
1574 return vms->highmem;
1575}
1576
1577static void virt_set_highmem(Object *obj, bool value, Error **errp)
1578{
1579 VirtMachineState *vms = VIRT_MACHINE(obj);
1580
1581 vms->highmem = value;
1582}
1583
1584static bool virt_get_its(Object *obj, Error **errp)
1585{
1586 VirtMachineState *vms = VIRT_MACHINE(obj);
1587
1588 return vms->its;
1589}
1590
1591static void virt_set_its(Object *obj, bool value, Error **errp)
1592{
1593 VirtMachineState *vms = VIRT_MACHINE(obj);
1594
1595 vms->its = value;
1596}
1597
1598static char *virt_get_gic_version(Object *obj, Error **errp)
1599{
1600 VirtMachineState *vms = VIRT_MACHINE(obj);
1601 const char *val = vms->gic_version == 3 ? "3" : "2";
1602
1603 return g_strdup(val);
1604}
1605
1606static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1607{
1608 VirtMachineState *vms = VIRT_MACHINE(obj);
1609
1610 if (!strcmp(value, "3")) {
1611 vms->gic_version = 3;
1612 } else if (!strcmp(value, "2")) {
1613 vms->gic_version = 2;
1614 } else if (!strcmp(value, "host")) {
1615 vms->gic_version = 0;
1616 } else if (!strcmp(value, "max")) {
1617 vms->gic_version = -1;
1618 } else {
1619 error_setg(errp, "Invalid gic-version value");
1620 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1621 }
1622}
1623
1624static char *virt_get_iommu(Object *obj, Error **errp)
1625{
1626 VirtMachineState *vms = VIRT_MACHINE(obj);
1627
1628 switch (vms->iommu) {
1629 case VIRT_IOMMU_NONE:
1630 return g_strdup("none");
1631 case VIRT_IOMMU_SMMUV3:
1632 return g_strdup("smmuv3");
1633 default:
1634 g_assert_not_reached();
1635 }
1636}
1637
1638static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1639{
1640 VirtMachineState *vms = VIRT_MACHINE(obj);
1641
1642 if (!strcmp(value, "smmuv3")) {
1643 vms->iommu = VIRT_IOMMU_SMMUV3;
1644 } else if (!strcmp(value, "none")) {
1645 vms->iommu = VIRT_IOMMU_NONE;
1646 } else {
1647 error_setg(errp, "Invalid iommu value");
1648 error_append_hint(errp, "Valid values are none, smmuv3.\n");
1649 }
1650}
1651
1652static CpuInstanceProperties
1653virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1654{
1655 MachineClass *mc = MACHINE_GET_CLASS(ms);
1656 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1657
1658 assert(cpu_index < possible_cpus->len);
1659 return possible_cpus->cpus[cpu_index].props;
1660}
1661
1662static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1663{
1664 return idx % nb_numa_nodes;
1665}
1666
1667static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1668{
1669 int n;
1670 VirtMachineState *vms = VIRT_MACHINE(ms);
1671
1672 if (ms->possible_cpus) {
1673 assert(ms->possible_cpus->len == max_cpus);
1674 return ms->possible_cpus;
1675 }
1676
1677 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1678 sizeof(CPUArchId) * max_cpus);
1679 ms->possible_cpus->len = max_cpus;
1680 for (n = 0; n < ms->possible_cpus->len; n++) {
1681 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1682 ms->possible_cpus->cpus[n].arch_id =
1683 virt_cpu_mp_affinity(vms, n);
1684 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1685 ms->possible_cpus->cpus[n].props.thread_id = n;
1686 }
1687 return ms->possible_cpus;
1688}
1689
1690static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1691 DeviceState *dev, Error **errp)
1692{
1693 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1694
1695 if (vms->platform_bus_dev) {
1696 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1697 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1698 SYS_BUS_DEVICE(dev));
1699 }
1700 }
1701}
1702
1703static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1704 DeviceState *dev)
1705{
1706 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1707 return HOTPLUG_HANDLER(machine);
1708 }
1709
1710 return NULL;
1711}
1712
1713static void virt_machine_class_init(ObjectClass *oc, void *data)
1714{
1715 MachineClass *mc = MACHINE_CLASS(oc);
1716 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1717
1718 mc->init = machvirt_init;
1719
1720
1721
1722
1723 mc->max_cpus = 512;
1724 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1725 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1726 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1727 mc->block_default_type = IF_VIRTIO;
1728 mc->no_cdrom = 1;
1729 mc->pci_allow_0_address = true;
1730
1731 mc->minimum_page_bits = 12;
1732 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1733 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1734 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1735 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1736 assert(!mc->get_hotplug_handler);
1737 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1738 hc->plug = virt_machine_device_plug_cb;
1739}
1740
1741static const TypeInfo virt_machine_info = {
1742 .name = TYPE_VIRT_MACHINE,
1743 .parent = TYPE_MACHINE,
1744 .abstract = true,
1745 .instance_size = sizeof(VirtMachineState),
1746 .class_size = sizeof(VirtMachineClass),
1747 .class_init = virt_machine_class_init,
1748 .interfaces = (InterfaceInfo[]) {
1749 { TYPE_HOTPLUG_HANDLER },
1750 { }
1751 },
1752};
1753
1754static void machvirt_machine_init(void)
1755{
1756 type_register_static(&virt_machine_info);
1757}
1758type_init(machvirt_machine_init);
1759
1760#define VIRT_COMPAT_2_12 \
1761 HW_COMPAT_2_12
1762
1763static void virt_3_0_instance_init(Object *obj)
1764{
1765 VirtMachineState *vms = VIRT_MACHINE(obj);
1766 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1767
1768
1769
1770
1771
1772 vms->secure = false;
1773 object_property_add_bool(obj, "secure", virt_get_secure,
1774 virt_set_secure, NULL);
1775 object_property_set_description(obj, "secure",
1776 "Set on/off to enable/disable the ARM "
1777 "Security Extensions (TrustZone)",
1778 NULL);
1779
1780
1781 vms->virt = false;
1782 object_property_add_bool(obj, "virtualization", virt_get_virt,
1783 virt_set_virt, NULL);
1784 object_property_set_description(obj, "virtualization",
1785 "Set on/off to enable/disable emulating a "
1786 "guest CPU which implements the ARM "
1787 "Virtualization Extensions",
1788 NULL);
1789
1790
1791 vms->highmem = true;
1792 object_property_add_bool(obj, "highmem", virt_get_highmem,
1793 virt_set_highmem, NULL);
1794 object_property_set_description(obj, "highmem",
1795 "Set on/off to enable/disable using "
1796 "physical address space above 32 bits",
1797 NULL);
1798
1799 vms->gic_version = 2;
1800 object_property_add_str(obj, "gic-version", virt_get_gic_version,
1801 virt_set_gic_version, NULL);
1802 object_property_set_description(obj, "gic-version",
1803 "Set GIC version. "
1804 "Valid values are 2, 3 and host", NULL);
1805
1806 vms->highmem_ecam = !vmc->no_highmem_ecam;
1807
1808 if (vmc->no_its) {
1809 vms->its = false;
1810 } else {
1811
1812 vms->its = true;
1813 object_property_add_bool(obj, "its", virt_get_its,
1814 virt_set_its, NULL);
1815 object_property_set_description(obj, "its",
1816 "Set on/off to enable/disable "
1817 "ITS instantiation",
1818 NULL);
1819 }
1820
1821
1822 vms->iommu = VIRT_IOMMU_NONE;
1823 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
1824 object_property_set_description(obj, "iommu",
1825 "Set the IOMMU type. "
1826 "Valid values are none and smmuv3",
1827 NULL);
1828
1829 vms->memmap = a15memmap;
1830 vms->irqmap = a15irqmap;
1831}
1832
1833static void virt_machine_3_0_options(MachineClass *mc)
1834{
1835}
1836DEFINE_VIRT_MACHINE_AS_LATEST(3, 0)
1837
1838static void virt_2_12_instance_init(Object *obj)
1839{
1840 virt_3_0_instance_init(obj);
1841}
1842
1843static void virt_machine_2_12_options(MachineClass *mc)
1844{
1845 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1846
1847 virt_machine_3_0_options(mc);
1848 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12);
1849 vmc->no_highmem_ecam = true;
1850 mc->max_cpus = 255;
1851}
1852DEFINE_VIRT_MACHINE(2, 12)
1853
1854#define VIRT_COMPAT_2_11 \
1855 HW_COMPAT_2_11
1856
1857static void virt_2_11_instance_init(Object *obj)
1858{
1859 virt_2_12_instance_init(obj);
1860}
1861
1862static void virt_machine_2_11_options(MachineClass *mc)
1863{
1864 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1865
1866 virt_machine_2_12_options(mc);
1867 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
1868 vmc->smbios_old_sys_ver = true;
1869}
1870DEFINE_VIRT_MACHINE(2, 11)
1871
1872#define VIRT_COMPAT_2_10 \
1873 HW_COMPAT_2_10
1874
1875static void virt_2_10_instance_init(Object *obj)
1876{
1877 virt_2_11_instance_init(obj);
1878}
1879
1880static void virt_machine_2_10_options(MachineClass *mc)
1881{
1882 virt_machine_2_11_options(mc);
1883 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10);
1884
1885 mc->ignore_memory_transaction_failures = true;
1886}
1887DEFINE_VIRT_MACHINE(2, 10)
1888
1889#define VIRT_COMPAT_2_9 \
1890 HW_COMPAT_2_9
1891
1892static void virt_2_9_instance_init(Object *obj)
1893{
1894 virt_2_10_instance_init(obj);
1895}
1896
1897static void virt_machine_2_9_options(MachineClass *mc)
1898{
1899 virt_machine_2_10_options(mc);
1900 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
1901}
1902DEFINE_VIRT_MACHINE(2, 9)
1903
1904#define VIRT_COMPAT_2_8 \
1905 HW_COMPAT_2_8
1906
1907static void virt_2_8_instance_init(Object *obj)
1908{
1909 virt_2_9_instance_init(obj);
1910}
1911
1912static void virt_machine_2_8_options(MachineClass *mc)
1913{
1914 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1915
1916 virt_machine_2_9_options(mc);
1917 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8);
1918
1919
1920
1921 vmc->claim_edge_triggered_timers = true;
1922}
1923DEFINE_VIRT_MACHINE(2, 8)
1924
1925#define VIRT_COMPAT_2_7 \
1926 HW_COMPAT_2_7
1927
1928static void virt_2_7_instance_init(Object *obj)
1929{
1930 virt_2_8_instance_init(obj);
1931}
1932
1933static void virt_machine_2_7_options(MachineClass *mc)
1934{
1935 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1936
1937 virt_machine_2_8_options(mc);
1938 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7);
1939
1940 vmc->no_its = true;
1941
1942 mc->minimum_page_bits = 0;
1943}
1944DEFINE_VIRT_MACHINE(2, 7)
1945
1946#define VIRT_COMPAT_2_6 \
1947 HW_COMPAT_2_6
1948
1949static void virt_2_6_instance_init(Object *obj)
1950{
1951 virt_2_7_instance_init(obj);
1952}
1953
1954static void virt_machine_2_6_options(MachineClass *mc)
1955{
1956 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
1957
1958 virt_machine_2_7_options(mc);
1959 SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
1960 vmc->disallow_affinity_adjustment = true;
1961
1962 vmc->no_pmu = true;
1963}
1964DEFINE_VIRT_MACHINE(2, 6)
1965