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26#include "qemu/osdep.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29#include "vga_int.h"
30#include "ui/pixel_ops.h"
31#include "qemu/timer.h"
32#include "hw/loader.h"
33
34enum vga_pci_flags {
35 PCI_VGA_FLAG_ENABLE_MMIO = 1,
36 PCI_VGA_FLAG_ENABLE_QEXT = 2,
37};
38
39typedef struct PCIVGAState {
40 PCIDevice dev;
41 VGACommonState vga;
42 uint32_t flags;
43 MemoryRegion mmio;
44 MemoryRegion mrs[3];
45} PCIVGAState;
46
47#define TYPE_PCI_VGA "pci-vga"
48#define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
49
50static const VMStateDescription vmstate_vga_pci = {
51 .name = "vga",
52 .version_id = 2,
53 .minimum_version_id = 2,
54 .fields = (VMStateField[]) {
55 VMSTATE_PCI_DEVICE(dev, PCIVGAState),
56 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
57 VMSTATE_END_OF_LIST()
58 }
59};
60
61static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
62 unsigned size)
63{
64 VGACommonState *s = ptr;
65 uint64_t ret = 0;
66
67 switch (size) {
68 case 1:
69 ret = vga_ioport_read(s, addr + 0x3c0);
70 break;
71 case 2:
72 ret = vga_ioport_read(s, addr + 0x3c0);
73 ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
74 break;
75 }
76 return ret;
77}
78
79static void pci_vga_ioport_write(void *ptr, hwaddr addr,
80 uint64_t val, unsigned size)
81{
82 VGACommonState *s = ptr;
83
84 switch (size) {
85 case 1:
86 vga_ioport_write(s, addr + 0x3c0, val);
87 break;
88 case 2:
89
90
91
92
93
94 vga_ioport_write(s, addr + 0x3c0, val & 0xff);
95 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
96 break;
97 }
98}
99
100static const MemoryRegionOps pci_vga_ioport_ops = {
101 .read = pci_vga_ioport_read,
102 .write = pci_vga_ioport_write,
103 .valid.min_access_size = 1,
104 .valid.max_access_size = 4,
105 .impl.min_access_size = 1,
106 .impl.max_access_size = 2,
107 .endianness = DEVICE_LITTLE_ENDIAN,
108};
109
110static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
111 unsigned size)
112{
113 VGACommonState *s = ptr;
114 int index = addr >> 1;
115
116 vbe_ioport_write_index(s, 0, index);
117 return vbe_ioport_read_data(s, 0);
118}
119
120static void pci_vga_bochs_write(void *ptr, hwaddr addr,
121 uint64_t val, unsigned size)
122{
123 VGACommonState *s = ptr;
124 int index = addr >> 1;
125
126 vbe_ioport_write_index(s, 0, index);
127 vbe_ioport_write_data(s, 0, val);
128}
129
130static const MemoryRegionOps pci_vga_bochs_ops = {
131 .read = pci_vga_bochs_read,
132 .write = pci_vga_bochs_write,
133 .valid.min_access_size = 1,
134 .valid.max_access_size = 4,
135 .impl.min_access_size = 2,
136 .impl.max_access_size = 2,
137 .endianness = DEVICE_LITTLE_ENDIAN,
138};
139
140static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
141{
142 VGACommonState *s = ptr;
143
144 switch (addr) {
145 case PCI_VGA_QEXT_REG_SIZE:
146 return PCI_VGA_QEXT_SIZE;
147 case PCI_VGA_QEXT_REG_BYTEORDER:
148 return s->big_endian_fb ?
149 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
150 default:
151 return 0;
152 }
153}
154
155static void pci_vga_qext_write(void *ptr, hwaddr addr,
156 uint64_t val, unsigned size)
157{
158 VGACommonState *s = ptr;
159
160 switch (addr) {
161 case PCI_VGA_QEXT_REG_BYTEORDER:
162 if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
163 s->big_endian_fb = true;
164 }
165 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
166 s->big_endian_fb = false;
167 }
168 break;
169 }
170}
171
172static bool vga_get_big_endian_fb(Object *obj, Error **errp)
173{
174 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
175
176 return d->vga.big_endian_fb;
177}
178
179static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
180{
181 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
182
183 d->vga.big_endian_fb = value;
184}
185
186static const MemoryRegionOps pci_vga_qext_ops = {
187 .read = pci_vga_qext_read,
188 .write = pci_vga_qext_write,
189 .valid.min_access_size = 4,
190 .valid.max_access_size = 4,
191 .endianness = DEVICE_LITTLE_ENDIAN,
192};
193
194void pci_std_vga_mmio_region_init(VGACommonState *s,
195 Object *owner,
196 MemoryRegion *parent,
197 MemoryRegion *subs,
198 bool qext)
199{
200 memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
201 "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
202 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
203 &subs[0]);
204
205 memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
206 "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
207 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
208 &subs[1]);
209
210 if (qext) {
211 memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
212 "qemu extended regs", PCI_VGA_QEXT_SIZE);
213 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
214 &subs[2]);
215 }
216}
217
218static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
219{
220 PCIVGAState *d = PCI_VGA(dev);
221 VGACommonState *s = &d->vga;
222 bool qext = false;
223
224
225 vga_common_init(s, OBJECT(dev));
226 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
227 true);
228
229 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
230
231
232 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
233
234
235 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
236 memory_region_init(&d->mmio, NULL, "vga.mmio",
237 PCI_VGA_MMIO_SIZE);
238
239 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
240 qext = true;
241 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
242 }
243 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext);
244
245 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
246 }
247
248 if (!dev->rom_bar) {
249
250 vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
251 }
252}
253
254static void pci_std_vga_init(Object *obj)
255{
256
257 object_property_add_bool(obj, "big-endian-framebuffer",
258 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
259}
260
261static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
262{
263 PCIVGAState *d = PCI_VGA(dev);
264 VGACommonState *s = &d->vga;
265 bool qext = false;
266
267
268 vga_common_init(s, OBJECT(dev));
269 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
270
271
272 memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio",
273 PCI_VGA_MMIO_SIZE);
274
275 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
276 qext = true;
277 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
278 }
279 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext);
280
281 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
282 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
283}
284
285static void pci_secondary_vga_exit(PCIDevice *dev)
286{
287 PCIVGAState *d = PCI_VGA(dev);
288 VGACommonState *s = &d->vga;
289
290 graphic_console_close(s->con);
291}
292
293static void pci_secondary_vga_init(Object *obj)
294{
295
296 object_property_add_bool(obj, "big-endian-framebuffer",
297 vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
298}
299
300static void pci_secondary_vga_reset(DeviceState *dev)
301{
302 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
303 vga_common_reset(&d->vga);
304}
305
306static Property vga_pci_properties[] = {
307 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
308 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
309 DEFINE_PROP_BIT("qemu-extended-regs",
310 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
311 DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
312 DEFINE_PROP_END_OF_LIST(),
313};
314
315static Property secondary_pci_properties[] = {
316 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
317 DEFINE_PROP_BIT("qemu-extended-regs",
318 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
319 DEFINE_PROP_END_OF_LIST(),
320};
321
322static void vga_pci_class_init(ObjectClass *klass, void *data)
323{
324 DeviceClass *dc = DEVICE_CLASS(klass);
325 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
326
327 k->vendor_id = PCI_VENDOR_ID_QEMU;
328 k->device_id = PCI_DEVICE_ID_QEMU_VGA;
329 dc->vmsd = &vmstate_vga_pci;
330 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
331}
332
333static const TypeInfo vga_pci_type_info = {
334 .name = TYPE_PCI_VGA,
335 .parent = TYPE_PCI_DEVICE,
336 .instance_size = sizeof(PCIVGAState),
337 .abstract = true,
338 .class_init = vga_pci_class_init,
339 .interfaces = (InterfaceInfo[]) {
340 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
341 { },
342 },
343};
344
345static void vga_class_init(ObjectClass *klass, void *data)
346{
347 DeviceClass *dc = DEVICE_CLASS(klass);
348 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
349
350 k->realize = pci_std_vga_realize;
351 k->romfile = "vgabios-stdvga.bin";
352 k->class_id = PCI_CLASS_DISPLAY_VGA;
353 dc->props = vga_pci_properties;
354 dc->hotpluggable = false;
355}
356
357static void secondary_class_init(ObjectClass *klass, void *data)
358{
359 DeviceClass *dc = DEVICE_CLASS(klass);
360 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
361
362 k->realize = pci_secondary_vga_realize;
363 k->exit = pci_secondary_vga_exit;
364 k->class_id = PCI_CLASS_DISPLAY_OTHER;
365 dc->props = secondary_pci_properties;
366 dc->reset = pci_secondary_vga_reset;
367}
368
369static const TypeInfo vga_info = {
370 .name = "VGA",
371 .parent = TYPE_PCI_VGA,
372 .instance_init = pci_std_vga_init,
373 .class_init = vga_class_init,
374};
375
376static const TypeInfo secondary_info = {
377 .name = "secondary-vga",
378 .parent = TYPE_PCI_VGA,
379 .instance_init = pci_secondary_vga_init,
380 .class_init = secondary_class_init,
381};
382
383static void vga_register_types(void)
384{
385 type_register_static(&vga_pci_type_info);
386 type_register_static(&vga_info);
387 type_register_static(&secondary_info);
388}
389
390type_init(vga_register_types)
391
