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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "hw/hw.h"
33#include "trace.h"
34#include "qemu/timer.h"
35#include "hw/ppc/xics.h"
36#include "qemu/error-report.h"
37#include "qapi/visitor.h"
38#include "monitor/monitor.h"
39#include "hw/intc/intc.h"
40
41void icp_pic_print_info(ICPState *icp, Monitor *mon)
42{
43 ICPStateClass *icpc = ICP_GET_CLASS(icp);
44 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
45
46 if (!icp->output) {
47 return;
48 }
49
50 if (icpc->synchronize_state) {
51 icpc->synchronize_state(icp);
52 }
53
54 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
55 cpu_index, icp->xirr, icp->xirr_owner,
56 icp->pending_priority, icp->mfrr);
57}
58
59void ics_pic_print_info(ICSState *ics, Monitor *mon)
60{
61 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
62 uint32_t i;
63
64 monitor_printf(mon, "ICS %4x..%4x %p\n",
65 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
66
67 if (!ics->irqs) {
68 return;
69 }
70
71 if (icsc->synchronize_state) {
72 icsc->synchronize_state(ics);
73 }
74
75 for (i = 0; i < ics->nr_irqs; i++) {
76 ICSIRQState *irq = ics->irqs + i;
77
78 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
79 continue;
80 }
81 monitor_printf(mon, " %4x %s %02x %02x\n",
82 ics->offset + i,
83 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
84 "LSI" : "MSI",
85 irq->priority, irq->status);
86 }
87}
88
89
90
91
92
93#define XISR_MASK 0x00ffffff
94#define CPPR_MASK 0xff000000
95
96#define XISR(icp) (((icp)->xirr) & XISR_MASK)
97#define CPPR(icp) (((icp)->xirr) >> 24)
98
99static void ics_reject(ICSState *ics, uint32_t nr)
100{
101 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
102
103 if (k->reject) {
104 k->reject(ics, nr);
105 }
106}
107
108void ics_resend(ICSState *ics)
109{
110 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
111
112 if (k->resend) {
113 k->resend(ics);
114 }
115}
116
117static void ics_eoi(ICSState *ics, int nr)
118{
119 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
120
121 if (k->eoi) {
122 k->eoi(ics, nr);
123 }
124}
125
126static void icp_check_ipi(ICPState *icp)
127{
128 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
129 return;
130 }
131
132 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
133
134 if (XISR(icp) && icp->xirr_owner) {
135 ics_reject(icp->xirr_owner, XISR(icp));
136 }
137
138 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
139 icp->pending_priority = icp->mfrr;
140 icp->xirr_owner = NULL;
141 qemu_irq_raise(icp->output);
142}
143
144void icp_resend(ICPState *icp)
145{
146 XICSFabric *xi = icp->xics;
147 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
148
149 if (icp->mfrr < CPPR(icp)) {
150 icp_check_ipi(icp);
151 }
152
153 xic->ics_resend(xi);
154}
155
156void icp_set_cppr(ICPState *icp, uint8_t cppr)
157{
158 uint8_t old_cppr;
159 uint32_t old_xisr;
160
161 old_cppr = CPPR(icp);
162 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
163
164 if (cppr < old_cppr) {
165 if (XISR(icp) && (cppr <= icp->pending_priority)) {
166 old_xisr = XISR(icp);
167 icp->xirr &= ~XISR_MASK;
168 icp->pending_priority = 0xff;
169 qemu_irq_lower(icp->output);
170 if (icp->xirr_owner) {
171 ics_reject(icp->xirr_owner, old_xisr);
172 icp->xirr_owner = NULL;
173 }
174 }
175 } else {
176 if (!XISR(icp)) {
177 icp_resend(icp);
178 }
179 }
180}
181
182void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
183{
184 icp->mfrr = mfrr;
185 if (mfrr < CPPR(icp)) {
186 icp_check_ipi(icp);
187 }
188}
189
190uint32_t icp_accept(ICPState *icp)
191{
192 uint32_t xirr = icp->xirr;
193
194 qemu_irq_lower(icp->output);
195 icp->xirr = icp->pending_priority << 24;
196 icp->pending_priority = 0xff;
197 icp->xirr_owner = NULL;
198
199 trace_xics_icp_accept(xirr, icp->xirr);
200
201 return xirr;
202}
203
204uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
205{
206 if (mfrr) {
207 *mfrr = icp->mfrr;
208 }
209 return icp->xirr;
210}
211
212void icp_eoi(ICPState *icp, uint32_t xirr)
213{
214 XICSFabric *xi = icp->xics;
215 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
216 ICSState *ics;
217 uint32_t irq;
218
219
220 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
221 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
222 irq = xirr & XISR_MASK;
223
224 ics = xic->ics_get(xi, irq);
225 if (ics) {
226 ics_eoi(ics, irq);
227 }
228 if (!XISR(icp)) {
229 icp_resend(icp);
230 }
231}
232
233static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
234{
235 ICPState *icp = xics_icp_get(ics->xics, server);
236
237 trace_xics_icp_irq(server, nr, priority);
238
239 if ((priority >= CPPR(icp))
240 || (XISR(icp) && (icp->pending_priority <= priority))) {
241 ics_reject(ics, nr);
242 } else {
243 if (XISR(icp) && icp->xirr_owner) {
244 ics_reject(icp->xirr_owner, XISR(icp));
245 icp->xirr_owner = NULL;
246 }
247 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
248 icp->xirr_owner = ics;
249 icp->pending_priority = priority;
250 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
251 qemu_irq_raise(icp->output);
252 }
253}
254
255static int icp_dispatch_pre_save(void *opaque)
256{
257 ICPState *icp = opaque;
258 ICPStateClass *info = ICP_GET_CLASS(icp);
259
260 if (info->pre_save) {
261 info->pre_save(icp);
262 }
263
264 return 0;
265}
266
267static int icp_dispatch_post_load(void *opaque, int version_id)
268{
269 ICPState *icp = opaque;
270 ICPStateClass *info = ICP_GET_CLASS(icp);
271
272 if (info->post_load) {
273 return info->post_load(icp, version_id);
274 }
275
276 return 0;
277}
278
279static const VMStateDescription vmstate_icp_server = {
280 .name = "icp/server",
281 .version_id = 1,
282 .minimum_version_id = 1,
283 .pre_save = icp_dispatch_pre_save,
284 .post_load = icp_dispatch_post_load,
285 .fields = (VMStateField[]) {
286
287 VMSTATE_UINT32(xirr, ICPState),
288 VMSTATE_UINT8(pending_priority, ICPState),
289 VMSTATE_UINT8(mfrr, ICPState),
290 VMSTATE_END_OF_LIST()
291 },
292};
293
294static void icp_reset(DeviceState *dev)
295{
296 ICPState *icp = ICP(dev);
297
298 icp->xirr = 0;
299 icp->pending_priority = 0xff;
300 icp->mfrr = 0xff;
301
302
303 qemu_set_irq(icp->output, 0);
304}
305
306static void icp_reset_handler(void *dev)
307{
308 DeviceClass *dc = DEVICE_GET_CLASS(dev);
309
310 dc->reset(dev);
311}
312
313static void icp_realize(DeviceState *dev, Error **errp)
314{
315 ICPState *icp = ICP(dev);
316 PowerPCCPU *cpu;
317 CPUPPCState *env;
318 Object *obj;
319 Error *err = NULL;
320
321 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
322 if (!obj) {
323 error_propagate(errp, err);
324 error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
325 return;
326 }
327
328 icp->xics = XICS_FABRIC(obj);
329
330 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
331 if (!obj) {
332 error_propagate(errp, err);
333 error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
334 return;
335 }
336
337 cpu = POWERPC_CPU(obj);
338 icp->cs = CPU(obj);
339
340 env = &cpu->env;
341 switch (PPC_INPUT(env)) {
342 case PPC_FLAGS_INPUT_POWER7:
343 icp->output = env->irq_inputs[POWER7_INPUT_INT];
344 break;
345
346 case PPC_FLAGS_INPUT_970:
347 icp->output = env->irq_inputs[PPC970_INPUT_INT];
348 break;
349
350 default:
351 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
352 return;
353 }
354
355 qemu_register_reset(icp_reset_handler, dev);
356 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
357}
358
359static void icp_unrealize(DeviceState *dev, Error **errp)
360{
361 ICPState *icp = ICP(dev);
362
363 vmstate_unregister(NULL, &vmstate_icp_server, icp);
364 qemu_unregister_reset(icp_reset_handler, dev);
365}
366
367static void icp_class_init(ObjectClass *klass, void *data)
368{
369 DeviceClass *dc = DEVICE_CLASS(klass);
370
371 dc->realize = icp_realize;
372 dc->unrealize = icp_unrealize;
373 dc->reset = icp_reset;
374}
375
376static const TypeInfo icp_info = {
377 .name = TYPE_ICP,
378 .parent = TYPE_DEVICE,
379 .instance_size = sizeof(ICPState),
380 .class_init = icp_class_init,
381 .class_size = sizeof(ICPStateClass),
382};
383
384Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
385{
386 Error *local_err = NULL;
387 Object *obj;
388
389 obj = object_new(type);
390 object_property_add_child(cpu, type, obj, &error_abort);
391 object_unref(obj);
392 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
393 &error_abort);
394 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
395 object_property_set_bool(obj, true, "realized", &local_err);
396 if (local_err) {
397 object_unparent(obj);
398 error_propagate(errp, local_err);
399 obj = NULL;
400 }
401
402 return obj;
403}
404
405
406
407
408static void ics_simple_resend_msi(ICSState *ics, int srcno)
409{
410 ICSIRQState *irq = ics->irqs + srcno;
411
412
413 if (irq->status & XICS_STATUS_REJECTED) {
414 irq->status &= ~XICS_STATUS_REJECTED;
415 if (irq->priority != 0xff) {
416 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
417 }
418 }
419}
420
421static void ics_simple_resend_lsi(ICSState *ics, int srcno)
422{
423 ICSIRQState *irq = ics->irqs + srcno;
424
425 if ((irq->priority != 0xff)
426 && (irq->status & XICS_STATUS_ASSERTED)
427 && !(irq->status & XICS_STATUS_SENT)) {
428 irq->status |= XICS_STATUS_SENT;
429 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
430 }
431}
432
433static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
434{
435 ICSIRQState *irq = ics->irqs + srcno;
436
437 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
438
439 if (val) {
440 if (irq->priority == 0xff) {
441 irq->status |= XICS_STATUS_MASKED_PENDING;
442 trace_xics_masked_pending();
443 } else {
444 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
445 }
446 }
447}
448
449static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
450{
451 ICSIRQState *irq = ics->irqs + srcno;
452
453 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
454 if (val) {
455 irq->status |= XICS_STATUS_ASSERTED;
456 } else {
457 irq->status &= ~XICS_STATUS_ASSERTED;
458 }
459 ics_simple_resend_lsi(ics, srcno);
460}
461
462static void ics_simple_set_irq(void *opaque, int srcno, int val)
463{
464 ICSState *ics = (ICSState *)opaque;
465
466 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
467 ics_simple_set_irq_lsi(ics, srcno, val);
468 } else {
469 ics_simple_set_irq_msi(ics, srcno, val);
470 }
471}
472
473static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
474{
475 ICSIRQState *irq = ics->irqs + srcno;
476
477 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
478 || (irq->priority == 0xff)) {
479 return;
480 }
481
482 irq->status &= ~XICS_STATUS_MASKED_PENDING;
483 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
484}
485
486static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
487{
488 ics_simple_resend_lsi(ics, srcno);
489}
490
491void ics_simple_write_xive(ICSState *ics, int srcno, int server,
492 uint8_t priority, uint8_t saved_priority)
493{
494 ICSIRQState *irq = ics->irqs + srcno;
495
496 irq->server = server;
497 irq->priority = priority;
498 irq->saved_priority = saved_priority;
499
500 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
501 priority);
502
503 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
504 ics_simple_write_xive_lsi(ics, srcno);
505 } else {
506 ics_simple_write_xive_msi(ics, srcno);
507 }
508}
509
510static void ics_simple_reject(ICSState *ics, uint32_t nr)
511{
512 ICSIRQState *irq = ics->irqs + nr - ics->offset;
513
514 trace_xics_ics_simple_reject(nr, nr - ics->offset);
515 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
516 irq->status |= XICS_STATUS_REJECTED;
517 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
518 irq->status &= ~XICS_STATUS_SENT;
519 }
520}
521
522static void ics_simple_resend(ICSState *ics)
523{
524 int i;
525
526 for (i = 0; i < ics->nr_irqs; i++) {
527
528 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
529 ics_simple_resend_lsi(ics, i);
530 } else {
531 ics_simple_resend_msi(ics, i);
532 }
533 }
534}
535
536static void ics_simple_eoi(ICSState *ics, uint32_t nr)
537{
538 int srcno = nr - ics->offset;
539 ICSIRQState *irq = ics->irqs + srcno;
540
541 trace_xics_ics_simple_eoi(nr);
542
543 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
544 irq->status &= ~XICS_STATUS_SENT;
545 }
546}
547
548static void ics_simple_reset(DeviceState *dev)
549{
550 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
551
552 icsc->parent_reset(dev);
553}
554
555static void ics_simple_reset_handler(void *dev)
556{
557 ics_simple_reset(dev);
558}
559
560static void ics_simple_realize(DeviceState *dev, Error **errp)
561{
562 ICSState *ics = ICS_SIMPLE(dev);
563 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
564 Error *local_err = NULL;
565
566 icsc->parent_realize(dev, &local_err);
567 if (local_err) {
568 error_propagate(errp, local_err);
569 return;
570 }
571
572 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
573
574 qemu_register_reset(ics_simple_reset_handler, ics);
575}
576
577static void ics_simple_class_init(ObjectClass *klass, void *data)
578{
579 DeviceClass *dc = DEVICE_CLASS(klass);
580 ICSStateClass *isc = ICS_BASE_CLASS(klass);
581
582 device_class_set_parent_realize(dc, ics_simple_realize,
583 &isc->parent_realize);
584 device_class_set_parent_reset(dc, ics_simple_reset,
585 &isc->parent_reset);
586
587 isc->reject = ics_simple_reject;
588 isc->resend = ics_simple_resend;
589 isc->eoi = ics_simple_eoi;
590}
591
592static const TypeInfo ics_simple_info = {
593 .name = TYPE_ICS_SIMPLE,
594 .parent = TYPE_ICS_BASE,
595 .instance_size = sizeof(ICSState),
596 .class_init = ics_simple_class_init,
597 .class_size = sizeof(ICSStateClass),
598};
599
600static void ics_base_reset(DeviceState *dev)
601{
602 ICSState *ics = ICS_BASE(dev);
603 int i;
604 uint8_t flags[ics->nr_irqs];
605
606 for (i = 0; i < ics->nr_irqs; i++) {
607 flags[i] = ics->irqs[i].flags;
608 }
609
610 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
611
612 for (i = 0; i < ics->nr_irqs; i++) {
613 ics->irqs[i].priority = 0xff;
614 ics->irqs[i].saved_priority = 0xff;
615 ics->irqs[i].flags = flags[i];
616 }
617}
618
619static void ics_base_realize(DeviceState *dev, Error **errp)
620{
621 ICSState *ics = ICS_BASE(dev);
622 Object *obj;
623 Error *err = NULL;
624
625 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
626 if (!obj) {
627 error_propagate(errp, err);
628 error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
629 return;
630 }
631 ics->xics = XICS_FABRIC(obj);
632
633 if (!ics->nr_irqs) {
634 error_setg(errp, "Number of interrupts needs to be greater 0");
635 return;
636 }
637 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
638}
639
640static void ics_base_instance_init(Object *obj)
641{
642 ICSState *ics = ICS_BASE(obj);
643
644 ics->offset = XICS_IRQ_BASE;
645}
646
647static int ics_base_dispatch_pre_save(void *opaque)
648{
649 ICSState *ics = opaque;
650 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
651
652 if (info->pre_save) {
653 info->pre_save(ics);
654 }
655
656 return 0;
657}
658
659static int ics_base_dispatch_post_load(void *opaque, int version_id)
660{
661 ICSState *ics = opaque;
662 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
663
664 if (info->post_load) {
665 return info->post_load(ics, version_id);
666 }
667
668 return 0;
669}
670
671static const VMStateDescription vmstate_ics_base_irq = {
672 .name = "ics/irq",
673 .version_id = 2,
674 .minimum_version_id = 1,
675 .fields = (VMStateField[]) {
676 VMSTATE_UINT32(server, ICSIRQState),
677 VMSTATE_UINT8(priority, ICSIRQState),
678 VMSTATE_UINT8(saved_priority, ICSIRQState),
679 VMSTATE_UINT8(status, ICSIRQState),
680 VMSTATE_UINT8(flags, ICSIRQState),
681 VMSTATE_END_OF_LIST()
682 },
683};
684
685static const VMStateDescription vmstate_ics_base = {
686 .name = "ics",
687 .version_id = 1,
688 .minimum_version_id = 1,
689 .pre_save = ics_base_dispatch_pre_save,
690 .post_load = ics_base_dispatch_post_load,
691 .fields = (VMStateField[]) {
692
693 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
694
695 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
696 vmstate_ics_base_irq,
697 ICSIRQState),
698 VMSTATE_END_OF_LIST()
699 },
700};
701
702static Property ics_base_properties[] = {
703 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
704 DEFINE_PROP_END_OF_LIST(),
705};
706
707static void ics_base_class_init(ObjectClass *klass, void *data)
708{
709 DeviceClass *dc = DEVICE_CLASS(klass);
710
711 dc->realize = ics_base_realize;
712 dc->props = ics_base_properties;
713 dc->reset = ics_base_reset;
714 dc->vmsd = &vmstate_ics_base;
715}
716
717static const TypeInfo ics_base_info = {
718 .name = TYPE_ICS_BASE,
719 .parent = TYPE_DEVICE,
720 .abstract = true,
721 .instance_size = sizeof(ICSState),
722 .instance_init = ics_base_instance_init,
723 .class_init = ics_base_class_init,
724 .class_size = sizeof(ICSStateClass),
725};
726
727static const TypeInfo xics_fabric_info = {
728 .name = TYPE_XICS_FABRIC,
729 .parent = TYPE_INTERFACE,
730 .class_size = sizeof(XICSFabricClass),
731};
732
733
734
735
736ICPState *xics_icp_get(XICSFabric *xi, int server)
737{
738 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
739
740 return xic->icp_get(xi, server);
741}
742
743void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
744{
745 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
746
747 ics->irqs[srcno].flags |=
748 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
749}
750
751static void xics_register_types(void)
752{
753 type_register_static(&ics_simple_info);
754 type_register_static(&ics_base_info);
755 type_register_static(&icp_info);
756 type_register_static(&xics_fabric_info);
757}
758
759type_init(xics_register_types)
760
