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26
27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "qapi/visitor.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/numa.h"
32#include "hw/hw.h"
33#include "qemu/log.h"
34#include "hw/fw-path-provider.h"
35#include "elf.h"
36#include "net/net.h"
37#include "sysemu/device_tree.h"
38#include "sysemu/cpus.h"
39#include "sysemu/hw_accel.h"
40#include "kvm_ppc.h"
41#include "migration/misc.h"
42#include "migration/global_state.h"
43#include "migration/register.h"
44#include "mmu-hash64.h"
45#include "mmu-book3s-v3.h"
46#include "cpu-models.h"
47#include "qom/cpu.h"
48
49#include "hw/boards.h"
50#include "hw/ppc/ppc.h"
51#include "hw/loader.h"
52
53#include "hw/ppc/fdt.h"
54#include "hw/ppc/spapr.h"
55#include "hw/ppc/spapr_vio.h"
56#include "hw/pci-host/spapr.h"
57#include "hw/ppc/xics.h"
58#include "hw/pci/msi.h"
59
60#include "hw/pci/pci.h"
61#include "hw/scsi/scsi.h"
62#include "hw/virtio/virtio-scsi.h"
63#include "hw/virtio/vhost-scsi-common.h"
64
65#include "exec/address-spaces.h"
66#include "exec/ram_addr.h"
67#include "hw/usb.h"
68#include "qemu/config-file.h"
69#include "qemu/error-report.h"
70#include "trace.h"
71#include "hw/nmi.h"
72#include "hw/intc/intc.h"
73
74#include "hw/compat.h"
75#include "qemu/cutils.h"
76#include "hw/ppc/spapr_cpu_core.h"
77#include "hw/mem/memory-device.h"
78
79#include <libfdt.h>
80
81
82
83
84
85
86
87
88
89
90
91#define FDT_MAX_SIZE 0x100000
92#define RTAS_MAX_SIZE 0x10000
93#define RTAS_MAX_ADDR 0x80000000
94#define FW_MAX_SIZE 0x400000
95#define FW_FILE_NAME "slof.bin"
96#define FW_OVERHEAD 0x2800000
97#define KERNEL_LOAD_ADDR FW_MAX_SIZE
98
99#define MIN_RMA_SLOF 128UL
100
101#define PHANDLE_XICP 0x00001111
102
103
104
105
106
107static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
108{
109 assert(spapr->vsmt);
110 return
111 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
112}
113static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
114 PowerPCCPU *cpu)
115{
116 assert(spapr->vsmt);
117 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
118}
119
120static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
121 const char *type_ics,
122 int nr_irqs, Error **errp)
123{
124 Error *local_err = NULL;
125 Object *obj;
126
127 obj = object_new(type_ics);
128 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
129 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
130 &error_abort);
131 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
132 if (local_err) {
133 goto error;
134 }
135 object_property_set_bool(obj, true, "realized", &local_err);
136 if (local_err) {
137 goto error;
138 }
139
140 return ICS_BASE(obj);
141
142error:
143 error_propagate(errp, local_err);
144 return NULL;
145}
146
147static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
148{
149
150
151
152
153 return false;
154}
155
156static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
157 .name = "icp/server",
158 .version_id = 1,
159 .minimum_version_id = 1,
160 .needed = pre_2_10_vmstate_dummy_icp_needed,
161 .fields = (VMStateField[]) {
162 VMSTATE_UNUSED(4),
163 VMSTATE_UNUSED(1),
164 VMSTATE_UNUSED(1),
165 VMSTATE_END_OF_LIST()
166 },
167};
168
169static void pre_2_10_vmstate_register_dummy_icp(int i)
170{
171 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
172 (void *)(uintptr_t) i);
173}
174
175static void pre_2_10_vmstate_unregister_dummy_icp(int i)
176{
177 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
178 (void *)(uintptr_t) i);
179}
180
181static int xics_max_server_number(sPAPRMachineState *spapr)
182{
183 assert(spapr->vsmt);
184 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
185}
186
187static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
188{
189 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
190 Error *local_err = NULL;
191
192 if (kvm_enabled()) {
193 if (machine_kernel_irqchip_allowed(machine) &&
194 !xics_kvm_init(spapr, &local_err)) {
195 spapr->icp_type = TYPE_KVM_ICP;
196 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
197 &local_err);
198 }
199 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
200 error_prepend(&local_err,
201 "kernel_irqchip requested but unavailable: ");
202 goto error;
203 }
204 error_free(local_err);
205 local_err = NULL;
206 }
207
208 if (!spapr->ics) {
209 xics_spapr_init(spapr);
210 spapr->icp_type = TYPE_ICP;
211 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
212 &local_err);
213 }
214
215error:
216 error_propagate(errp, local_err);
217}
218
219static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
220 int smt_threads)
221{
222 int i, ret = 0;
223 uint32_t servers_prop[smt_threads];
224 uint32_t gservers_prop[smt_threads * 2];
225 int index = spapr_get_vcpu_id(cpu);
226
227 if (cpu->compat_pvr) {
228 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
229 if (ret < 0) {
230 return ret;
231 }
232 }
233
234
235 for (i = 0; i < smt_threads; i++) {
236 servers_prop[i] = cpu_to_be32(index + i);
237
238 gservers_prop[i*2] = cpu_to_be32(index + i);
239 gservers_prop[i*2 + 1] = 0;
240 }
241 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
242 servers_prop, sizeof(servers_prop));
243 if (ret < 0) {
244 return ret;
245 }
246 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
247 gservers_prop, sizeof(gservers_prop));
248
249 return ret;
250}
251
252static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
253{
254 int index = spapr_get_vcpu_id(cpu);
255 uint32_t associativity[] = {cpu_to_be32(0x5),
256 cpu_to_be32(0x0),
257 cpu_to_be32(0x0),
258 cpu_to_be32(0x0),
259 cpu_to_be32(cpu->node_id),
260 cpu_to_be32(index)};
261
262
263 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
264 sizeof(associativity));
265}
266
267
268static void spapr_populate_pa_features(sPAPRMachineState *spapr,
269 PowerPCCPU *cpu,
270 void *fdt, int offset,
271 bool legacy_guest)
272{
273 uint8_t pa_features_206[] = { 6, 0,
274 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
275 uint8_t pa_features_207[] = { 24, 0,
276 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
277 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
278 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
279 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
280 uint8_t pa_features_300[] = { 66, 0,
281
282
283 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
284
285 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
286
287 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
288
289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
290
291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
292
293 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
294
295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
296
297 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
298
299 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
300
301 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
302
303 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
304 };
305 uint8_t *pa_features = NULL;
306 size_t pa_size;
307
308 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
309 pa_features = pa_features_206;
310 pa_size = sizeof(pa_features_206);
311 }
312 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
313 pa_features = pa_features_207;
314 pa_size = sizeof(pa_features_207);
315 }
316 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
317 pa_features = pa_features_300;
318 pa_size = sizeof(pa_features_300);
319 }
320 if (!pa_features) {
321 return;
322 }
323
324 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
325
326
327
328
329
330
331
332 pa_features[3] |= 0x20;
333 }
334 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
335 pa_features[24] |= 0x80;
336 }
337 if (legacy_guest && pa_size > 40) {
338
339
340
341 pa_features[40 + 2] &= ~0x80;
342 }
343
344 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
345}
346
347static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
348{
349 int ret = 0, offset, cpus_offset;
350 CPUState *cs;
351 char cpu_model[32];
352 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
353
354 CPU_FOREACH(cs) {
355 PowerPCCPU *cpu = POWERPC_CPU(cs);
356 DeviceClass *dc = DEVICE_GET_CLASS(cs);
357 int index = spapr_get_vcpu_id(cpu);
358 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
359
360 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
361 continue;
362 }
363
364 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
365
366 cpus_offset = fdt_path_offset(fdt, "/cpus");
367 if (cpus_offset < 0) {
368 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
369 if (cpus_offset < 0) {
370 return cpus_offset;
371 }
372 }
373 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
374 if (offset < 0) {
375 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
376 if (offset < 0) {
377 return offset;
378 }
379 }
380
381 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
382 pft_size_prop, sizeof(pft_size_prop));
383 if (ret < 0) {
384 return ret;
385 }
386
387 if (nb_numa_nodes > 1) {
388 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
389 if (ret < 0) {
390 return ret;
391 }
392 }
393
394 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
395 if (ret < 0) {
396 return ret;
397 }
398
399 spapr_populate_pa_features(spapr, cpu, fdt, offset,
400 spapr->cas_legacy_guest_workaround);
401 }
402 return ret;
403}
404
405static hwaddr spapr_node0_size(MachineState *machine)
406{
407 if (nb_numa_nodes) {
408 int i;
409 for (i = 0; i < nb_numa_nodes; ++i) {
410 if (numa_info[i].node_mem) {
411 return MIN(pow2floor(numa_info[i].node_mem),
412 machine->ram_size);
413 }
414 }
415 }
416 return machine->ram_size;
417}
418
419static void add_str(GString *s, const gchar *s1)
420{
421 g_string_append_len(s, s1, strlen(s1) + 1);
422}
423
424static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
425 hwaddr size)
426{
427 uint32_t associativity[] = {
428 cpu_to_be32(0x4),
429 cpu_to_be32(0x0), cpu_to_be32(0x0),
430 cpu_to_be32(0x0), cpu_to_be32(nodeid)
431 };
432 char mem_name[32];
433 uint64_t mem_reg_property[2];
434 int off;
435
436 mem_reg_property[0] = cpu_to_be64(start);
437 mem_reg_property[1] = cpu_to_be64(size);
438
439 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
440 off = fdt_add_subnode(fdt, 0, mem_name);
441 _FDT(off);
442 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
443 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
444 sizeof(mem_reg_property))));
445 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
446 sizeof(associativity))));
447 return off;
448}
449
450static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
451{
452 MachineState *machine = MACHINE(spapr);
453 hwaddr mem_start, node_size;
454 int i, nb_nodes = nb_numa_nodes;
455 NodeInfo *nodes = numa_info;
456 NodeInfo ramnode;
457
458
459 if (!nb_numa_nodes) {
460 nb_nodes = 1;
461 ramnode.node_mem = machine->ram_size;
462 nodes = &ramnode;
463 }
464
465 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
466 if (!nodes[i].node_mem) {
467 continue;
468 }
469 if (mem_start >= machine->ram_size) {
470 node_size = 0;
471 } else {
472 node_size = nodes[i].node_mem;
473 if (node_size > machine->ram_size - mem_start) {
474 node_size = machine->ram_size - mem_start;
475 }
476 }
477 if (!mem_start) {
478
479
480 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
481 mem_start += spapr->rma_size;
482 node_size -= spapr->rma_size;
483 }
484 for ( ; node_size; ) {
485 hwaddr sizetmp = pow2floor(node_size);
486
487
488 if (ctzl(mem_start) < ctzl(sizetmp)) {
489 sizetmp = 1ULL << ctzl(mem_start);
490 }
491
492 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
493 node_size -= sizetmp;
494 mem_start += sizetmp;
495 }
496 }
497
498 return 0;
499}
500
501static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
502 sPAPRMachineState *spapr)
503{
504 PowerPCCPU *cpu = POWERPC_CPU(cs);
505 CPUPPCState *env = &cpu->env;
506 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
507 int index = spapr_get_vcpu_id(cpu);
508 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
509 0xffffffff, 0xffffffff};
510 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
511 : SPAPR_TIMEBASE_FREQ;
512 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
513 uint32_t page_sizes_prop[64];
514 size_t page_sizes_prop_size;
515 uint32_t vcpus_per_socket = smp_threads * smp_cores;
516 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
517 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
518 sPAPRDRConnector *drc;
519 int drc_index;
520 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
521 int i;
522
523 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
524 if (drc) {
525 drc_index = spapr_drc_index(drc);
526 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
527 }
528
529 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
530 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
531
532 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
533 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
534 env->dcache_line_size)));
535 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
536 env->dcache_line_size)));
537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
538 env->icache_line_size)));
539 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
540 env->icache_line_size)));
541
542 if (pcc->l1_dcache_size) {
543 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
544 pcc->l1_dcache_size)));
545 } else {
546 warn_report("Unknown L1 dcache size for cpu");
547 }
548 if (pcc->l1_icache_size) {
549 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
550 pcc->l1_icache_size)));
551 } else {
552 warn_report("Unknown L1 icache size for cpu");
553 }
554
555 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
556 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
557 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
558 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
559 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
560 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
561
562 if (env->spr_cb[SPR_PURR].oea_read) {
563 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
564 }
565
566 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
567 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
568 segs, sizeof(segs))));
569 }
570
571
572
573
574
575
576
577 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
578 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
579 } else {
580 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
581 }
582
583
584
585
586 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
587 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
588 }
589
590 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
591 sizeof(page_sizes_prop));
592 if (page_sizes_prop_size) {
593 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
594 page_sizes_prop, page_sizes_prop_size)));
595 }
596
597 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
598
599 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
600 cs->cpu_index / vcpus_per_socket)));
601
602 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
603 pft_size_prop, sizeof(pft_size_prop))));
604
605 if (nb_numa_nodes > 1) {
606 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
607 }
608
609 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
610
611 if (pcc->radix_page_info) {
612 for (i = 0; i < pcc->radix_page_info->count; i++) {
613 radix_AP_encodings[i] =
614 cpu_to_be32(pcc->radix_page_info->entries[i]);
615 }
616 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
617 radix_AP_encodings,
618 pcc->radix_page_info->count *
619 sizeof(radix_AP_encodings[0]))));
620 }
621}
622
623static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
624{
625 CPUState *cs;
626 int cpus_offset;
627 char *nodename;
628
629 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
630 _FDT(cpus_offset);
631 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
632 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
633
634
635
636
637
638
639 CPU_FOREACH_REVERSE(cs) {
640 PowerPCCPU *cpu = POWERPC_CPU(cs);
641 int index = spapr_get_vcpu_id(cpu);
642 DeviceClass *dc = DEVICE_GET_CLASS(cs);
643 int offset;
644
645 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
646 continue;
647 }
648
649 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
650 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
651 g_free(nodename);
652 _FDT(offset);
653 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
654 }
655
656}
657
658static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
659{
660 MemoryDeviceInfoList *info;
661
662 for (info = list; info; info = info->next) {
663 MemoryDeviceInfo *value = info->value;
664
665 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
666 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
667
668 if (addr >= pcdimm_info->addr &&
669 addr < (pcdimm_info->addr + pcdimm_info->size)) {
670 return pcdimm_info->node;
671 }
672 }
673 }
674
675 return -1;
676}
677
678struct sPAPRDrconfCellV2 {
679 uint32_t seq_lmbs;
680 uint64_t base_addr;
681 uint32_t drc_index;
682 uint32_t aa_index;
683 uint32_t flags;
684} QEMU_PACKED;
685
686typedef struct DrconfCellQueue {
687 struct sPAPRDrconfCellV2 cell;
688 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
689} DrconfCellQueue;
690
691static DrconfCellQueue *
692spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
693 uint32_t drc_index, uint32_t aa_index,
694 uint32_t flags)
695{
696 DrconfCellQueue *elem;
697
698 elem = g_malloc0(sizeof(*elem));
699 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
700 elem->cell.base_addr = cpu_to_be64(base_addr);
701 elem->cell.drc_index = cpu_to_be32(drc_index);
702 elem->cell.aa_index = cpu_to_be32(aa_index);
703 elem->cell.flags = cpu_to_be32(flags);
704
705 return elem;
706}
707
708
709static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt,
710 int offset, MemoryDeviceInfoList *dimms)
711{
712 MachineState *machine = MACHINE(spapr);
713 uint8_t *int_buf, *cur_index, buf_len;
714 int ret;
715 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
716 uint64_t addr, cur_addr, size;
717 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
718 uint64_t mem_end = machine->device_memory->base +
719 memory_region_size(&machine->device_memory->mr);
720 uint32_t node, nr_entries = 0;
721 sPAPRDRConnector *drc;
722 DrconfCellQueue *elem, *next;
723 MemoryDeviceInfoList *info;
724 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
725 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
726
727
728 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
729 SPAPR_LMB_FLAGS_RESERVED |
730 SPAPR_LMB_FLAGS_DRC_INVALID);
731 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
732 nr_entries++;
733
734 cur_addr = machine->device_memory->base;
735 for (info = dimms; info; info = info->next) {
736 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
737
738 addr = di->addr;
739 size = di->size;
740 node = di->node;
741
742
743 if (cur_addr < addr) {
744 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
745 g_assert(drc);
746 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
747 cur_addr, spapr_drc_index(drc), -1, 0);
748 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
749 nr_entries++;
750 }
751
752
753 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
754 g_assert(drc);
755 elem = spapr_get_drconf_cell(size / lmb_size, addr,
756 spapr_drc_index(drc), node,
757 SPAPR_LMB_FLAGS_ASSIGNED);
758 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
759 nr_entries++;
760 cur_addr = addr + size;
761 }
762
763
764 if (cur_addr < mem_end) {
765 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
766 g_assert(drc);
767 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
768 cur_addr, spapr_drc_index(drc), -1, 0);
769 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
770 nr_entries++;
771 }
772
773 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
774 int_buf = cur_index = g_malloc0(buf_len);
775 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
776 cur_index += sizeof(nr_entries);
777
778 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
779 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
780 cur_index += sizeof(elem->cell);
781 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
782 g_free(elem);
783 }
784
785 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
786 g_free(int_buf);
787 if (ret < 0) {
788 return -1;
789 }
790 return 0;
791}
792
793
794static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt,
795 int offset, MemoryDeviceInfoList *dimms)
796{
797 MachineState *machine = MACHINE(spapr);
798 int i, ret;
799 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
800 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
801 uint32_t nr_lmbs = (machine->device_memory->base +
802 memory_region_size(&machine->device_memory->mr)) /
803 lmb_size;
804 uint32_t *int_buf, *cur_index, buf_len;
805
806
807
808
809 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
810 cur_index = int_buf = g_malloc0(buf_len);
811 int_buf[0] = cpu_to_be32(nr_lmbs);
812 cur_index++;
813 for (i = 0; i < nr_lmbs; i++) {
814 uint64_t addr = i * lmb_size;
815 uint32_t *dynamic_memory = cur_index;
816
817 if (i >= device_lmb_start) {
818 sPAPRDRConnector *drc;
819
820 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
821 g_assert(drc);
822
823 dynamic_memory[0] = cpu_to_be32(addr >> 32);
824 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
825 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
826 dynamic_memory[3] = cpu_to_be32(0);
827 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
828 if (memory_region_present(get_system_memory(), addr)) {
829 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
830 } else {
831 dynamic_memory[5] = cpu_to_be32(0);
832 }
833 } else {
834
835
836
837
838
839 dynamic_memory[0] = cpu_to_be32(addr >> 32);
840 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
841 dynamic_memory[2] = cpu_to_be32(0);
842 dynamic_memory[3] = cpu_to_be32(0);
843 dynamic_memory[4] = cpu_to_be32(-1);
844 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
845 SPAPR_LMB_FLAGS_DRC_INVALID);
846 }
847
848 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
849 }
850 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
851 g_free(int_buf);
852 if (ret < 0) {
853 return -1;
854 }
855 return 0;
856}
857
858
859
860
861
862
863static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
864{
865 MachineState *machine = MACHINE(spapr);
866 int ret, i, offset;
867 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
868 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
869 uint32_t *int_buf, *cur_index, buf_len;
870 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
871 MemoryDeviceInfoList *dimms = NULL;
872
873
874
875
876 if (machine->ram_size == machine->maxram_size) {
877 return 0;
878 }
879
880 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
881
882 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
883 sizeof(prop_lmb_size));
884 if (ret < 0) {
885 return ret;
886 }
887
888 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
889 if (ret < 0) {
890 return ret;
891 }
892
893 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
894 if (ret < 0) {
895 return ret;
896 }
897
898
899 dimms = qmp_memory_device_list();
900 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
901 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
902 } else {
903 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
904 }
905 qapi_free_MemoryDeviceInfoList(dimms);
906
907 if (ret < 0) {
908 return ret;
909 }
910
911
912 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
913 cur_index = int_buf = g_malloc0(buf_len);
914
915 cur_index = int_buf;
916 int_buf[0] = cpu_to_be32(nr_nodes);
917 int_buf[1] = cpu_to_be32(4);
918 cur_index += 2;
919 for (i = 0; i < nr_nodes; i++) {
920 uint32_t associativity[] = {
921 cpu_to_be32(0x0),
922 cpu_to_be32(0x0),
923 cpu_to_be32(0x0),
924 cpu_to_be32(i)
925 };
926 memcpy(cur_index, associativity, sizeof(associativity));
927 cur_index += 4;
928 }
929 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
930 (cur_index - int_buf) * sizeof(uint32_t));
931 g_free(int_buf);
932
933 return ret;
934}
935
936static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
937 sPAPROptionVector *ov5_updates)
938{
939 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
940 int ret = 0, offset;
941
942
943 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
944 g_assert(smc->dr_lmb_enabled);
945 ret = spapr_populate_drconf_memory(spapr, fdt);
946 if (ret) {
947 goto out;
948 }
949 }
950
951 offset = fdt_path_offset(fdt, "/chosen");
952 if (offset < 0) {
953 offset = fdt_add_subnode(fdt, 0, "chosen");
954 if (offset < 0) {
955 return offset;
956 }
957 }
958 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
959 "ibm,architecture-vec-5");
960
961out:
962 return ret;
963}
964
965static bool spapr_hotplugged_dev_before_cas(void)
966{
967 Object *drc_container, *obj;
968 ObjectProperty *prop;
969 ObjectPropertyIterator iter;
970
971 drc_container = container_get(object_get_root(), "/dr-connector");
972 object_property_iter_init(&iter, drc_container);
973 while ((prop = object_property_iter_next(&iter))) {
974 if (!strstart(prop->type, "link<", NULL)) {
975 continue;
976 }
977 obj = object_property_get_link(drc_container, prop->name, NULL);
978 if (spapr_drc_needed(obj)) {
979 return true;
980 }
981 }
982 return false;
983}
984
985int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
986 target_ulong addr, target_ulong size,
987 sPAPROptionVector *ov5_updates)
988{
989 void *fdt, *fdt_skel;
990 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
991
992 if (spapr_hotplugged_dev_before_cas()) {
993 return 1;
994 }
995
996 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
997 error_report("SLOF provided an unexpected CAS buffer size "
998 TARGET_FMT_lu " (min: %zu, max: %u)",
999 size, sizeof(hdr), FW_MAX_SIZE);
1000 exit(EXIT_FAILURE);
1001 }
1002
1003 size -= sizeof(hdr);
1004
1005
1006 fdt_skel = g_malloc0(size);
1007 _FDT((fdt_create(fdt_skel, size)));
1008 _FDT((fdt_finish_reservemap(fdt_skel)));
1009 _FDT((fdt_begin_node(fdt_skel, "")));
1010 _FDT((fdt_end_node(fdt_skel)));
1011 _FDT((fdt_finish(fdt_skel)));
1012 fdt = g_malloc0(size);
1013 _FDT((fdt_open_into(fdt_skel, fdt, size)));
1014 g_free(fdt_skel);
1015
1016
1017 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
1018
1019 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1020 return -1;
1021 }
1022
1023
1024 _FDT((fdt_pack(fdt)));
1025
1026 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1027 trace_spapr_cas_failed(size);
1028 return -1;
1029 }
1030
1031 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1032 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1033 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1034 g_free(fdt);
1035
1036 return 0;
1037}
1038
1039static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
1040{
1041 int rtas;
1042 GString *hypertas = g_string_sized_new(256);
1043 GString *qemu_hypertas = g_string_sized_new(256);
1044 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1045 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1046 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1047 uint32_t lrdr_capacity[] = {
1048 cpu_to_be32(max_device_addr >> 32),
1049 cpu_to_be32(max_device_addr & 0xffffffff),
1050 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1051 cpu_to_be32(max_cpus / smp_threads),
1052 };
1053 uint32_t maxdomains[] = {
1054 cpu_to_be32(4),
1055 cpu_to_be32(0),
1056 cpu_to_be32(0),
1057 cpu_to_be32(0),
1058 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0),
1059 };
1060
1061 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1062
1063
1064 add_str(hypertas, "hcall-pft");
1065 add_str(hypertas, "hcall-term");
1066 add_str(hypertas, "hcall-dabr");
1067 add_str(hypertas, "hcall-interrupt");
1068 add_str(hypertas, "hcall-tce");
1069 add_str(hypertas, "hcall-vio");
1070 add_str(hypertas, "hcall-splpar");
1071 add_str(hypertas, "hcall-bulk");
1072 add_str(hypertas, "hcall-set-mode");
1073 add_str(hypertas, "hcall-sprg0");
1074 add_str(hypertas, "hcall-copy");
1075 add_str(hypertas, "hcall-debug");
1076 add_str(qemu_hypertas, "hcall-memop1");
1077
1078 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1079 add_str(hypertas, "hcall-multi-tce");
1080 }
1081
1082 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1083 add_str(hypertas, "hcall-hpt-resize");
1084 }
1085
1086 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1087 hypertas->str, hypertas->len));
1088 g_string_free(hypertas, TRUE);
1089 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1090 qemu_hypertas->str, qemu_hypertas->len));
1091 g_string_free(qemu_hypertas, TRUE);
1092
1093 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1094 refpoints, sizeof(refpoints)));
1095
1096 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1097 maxdomains, sizeof(maxdomains)));
1098
1099 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1100 RTAS_ERROR_LOG_MAX));
1101 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1102 RTAS_EVENT_SCAN_RATE));
1103
1104 g_assert(msi_nonbroken);
1105 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1106
1107
1108
1109
1110
1111
1112
1113
1114 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1115
1116 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1117 lrdr_capacity, sizeof(lrdr_capacity)));
1118
1119 spapr_dt_rtas_tokens(fdt, rtas);
1120}
1121
1122
1123
1124
1125static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
1126{
1127 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1128
1129 char val[2 * 4] = {
1130 23, 0x00,
1131 24, 0x00,
1132 25, 0x00,
1133 26, 0x40,
1134 };
1135
1136 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1137 first_ppc_cpu->compat_pvr)) {
1138
1139 val[3] = 0x00;
1140 } else if (kvm_enabled()) {
1141 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1142 val[3] = 0x80;
1143 } else if (kvmppc_has_cap_mmu_radix()) {
1144 val[3] = 0x40;
1145 } else {
1146 val[3] = 0x00;
1147 }
1148 } else {
1149
1150 val[3] = 0xC0;
1151 }
1152 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1153 val, sizeof(val)));
1154}
1155
1156static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1157{
1158 MachineState *machine = MACHINE(spapr);
1159 int chosen;
1160 const char *boot_device = machine->boot_order;
1161 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1162 size_t cb = 0;
1163 char *bootlist = get_boot_devices_list(&cb, true);
1164
1165 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1166
1167 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1168 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1169 spapr->initrd_base));
1170 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1171 spapr->initrd_base + spapr->initrd_size));
1172
1173 if (spapr->kernel_size) {
1174 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1175 cpu_to_be64(spapr->kernel_size) };
1176
1177 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1178 &kprop, sizeof(kprop)));
1179 if (spapr->kernel_le) {
1180 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1181 }
1182 }
1183 if (boot_menu) {
1184 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1185 }
1186 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1187 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1188 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1189
1190 if (cb && bootlist) {
1191 int i;
1192
1193 for (i = 0; i < cb; i++) {
1194 if (bootlist[i] == '\n') {
1195 bootlist[i] = ' ';
1196 }
1197 }
1198 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1199 }
1200
1201 if (boot_device && strlen(boot_device)) {
1202 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1203 }
1204
1205 if (!spapr->has_graphics && stdout_path) {
1206
1207
1208
1209
1210
1211
1212 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1213 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1214 }
1215
1216 spapr_dt_ov5_platform_support(fdt, chosen);
1217
1218 g_free(stdout_path);
1219 g_free(bootlist);
1220}
1221
1222static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1223{
1224
1225
1226 int hypervisor;
1227 uint8_t hypercall[16];
1228
1229 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1230
1231 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1232 if (kvmppc_has_cap_fixup_hcalls()) {
1233
1234
1235
1236
1237 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1238 sizeof(hypercall))) {
1239 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1240 hypercall, sizeof(hypercall)));
1241 }
1242 }
1243}
1244
1245static void *spapr_build_fdt(sPAPRMachineState *spapr,
1246 hwaddr rtas_addr,
1247 hwaddr rtas_size)
1248{
1249 MachineState *machine = MACHINE(spapr);
1250 MachineClass *mc = MACHINE_GET_CLASS(machine);
1251 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1252 int ret;
1253 void *fdt;
1254 sPAPRPHBState *phb;
1255 char *buf;
1256
1257 fdt = g_malloc0(FDT_MAX_SIZE);
1258 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1259
1260
1261 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1262 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1263 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1264
1265
1266
1267
1268
1269 if (kvmppc_get_host_model(&buf)) {
1270 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1271 g_free(buf);
1272 }
1273 if (kvmppc_get_host_serial(&buf)) {
1274 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1275 g_free(buf);
1276 }
1277
1278 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1279
1280 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1281 if (qemu_uuid_set) {
1282 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1283 }
1284 g_free(buf);
1285
1286 if (qemu_get_vm_name()) {
1287 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1288 qemu_get_vm_name()));
1289 }
1290
1291 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1292 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1293
1294
1295 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
1296
1297 ret = spapr_populate_memory(spapr, fdt);
1298 if (ret < 0) {
1299 error_report("couldn't setup memory nodes in fdt");
1300 exit(1);
1301 }
1302
1303
1304 spapr_dt_vdevice(spapr->vio_bus, fdt);
1305
1306 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1307 ret = spapr_rng_populate_dt(fdt);
1308 if (ret < 0) {
1309 error_report("could not set up rng device in the fdt");
1310 exit(1);
1311 }
1312 }
1313
1314 QLIST_FOREACH(phb, &spapr->phbs, list) {
1315 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1316 if (ret < 0) {
1317 error_report("couldn't setup PCI devices in fdt");
1318 exit(1);
1319 }
1320 }
1321
1322
1323 spapr_populate_cpus_dt_node(fdt, spapr);
1324
1325 if (smc->dr_lmb_enabled) {
1326 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1327 }
1328
1329 if (mc->has_hotpluggable_cpus) {
1330 int offset = fdt_path_offset(fdt, "/cpus");
1331 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1332 SPAPR_DR_CONNECTOR_TYPE_CPU);
1333 if (ret < 0) {
1334 error_report("Couldn't set up CPU DR device tree properties");
1335 exit(1);
1336 }
1337 }
1338
1339
1340 spapr_dt_events(spapr, fdt);
1341
1342
1343 spapr_dt_rtas(spapr, fdt);
1344
1345
1346 spapr_dt_chosen(spapr, fdt);
1347
1348
1349 if (kvm_enabled()) {
1350 spapr_dt_hypervisor(spapr, fdt);
1351 }
1352
1353
1354 if (spapr->kernel_size) {
1355 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1356 }
1357 if (spapr->initrd_size) {
1358 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1359 }
1360
1361
1362 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1363 if (ret < 0) {
1364 error_report("couldn't setup CAS properties fdt");
1365 exit(1);
1366 }
1367
1368 return fdt;
1369}
1370
1371static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1372{
1373 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1374}
1375
1376static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1377 PowerPCCPU *cpu)
1378{
1379 CPUPPCState *env = &cpu->env;
1380
1381
1382 g_assert(qemu_mutex_iothread_locked());
1383
1384 if (msr_pr) {
1385 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1386 env->gpr[3] = H_PRIVILEGE;
1387 } else {
1388 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1389 }
1390}
1391
1392static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1393{
1394 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1395
1396 return spapr->patb_entry;
1397}
1398
1399#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1400#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1401#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1402#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1403#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1404
1405
1406
1407
1408static int get_htab_fd(sPAPRMachineState *spapr)
1409{
1410 Error *local_err = NULL;
1411
1412 if (spapr->htab_fd >= 0) {
1413 return spapr->htab_fd;
1414 }
1415
1416 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1417 if (spapr->htab_fd < 0) {
1418 error_report_err(local_err);
1419 }
1420
1421 return spapr->htab_fd;
1422}
1423
1424void close_htab_fd(sPAPRMachineState *spapr)
1425{
1426 if (spapr->htab_fd >= 0) {
1427 close(spapr->htab_fd);
1428 }
1429 spapr->htab_fd = -1;
1430}
1431
1432static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1433{
1434 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1435
1436 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1437}
1438
1439static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1440{
1441 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1442
1443 assert(kvm_enabled());
1444
1445 if (!spapr->htab) {
1446 return 0;
1447 }
1448
1449 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1450}
1451
1452static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1453 hwaddr ptex, int n)
1454{
1455 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1456 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1457
1458 if (!spapr->htab) {
1459
1460
1461
1462 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1463 kvmppc_read_hptes(hptes, ptex, n);
1464 return hptes;
1465 }
1466
1467
1468
1469
1470
1471 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1472}
1473
1474static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1475 const ppc_hash_pte64_t *hptes,
1476 hwaddr ptex, int n)
1477{
1478 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1479
1480 if (!spapr->htab) {
1481 g_free((void *)hptes);
1482 }
1483
1484
1485}
1486
1487static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1488 uint64_t pte0, uint64_t pte1)
1489{
1490 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1491 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1492
1493 if (!spapr->htab) {
1494 kvmppc_write_hpte(ptex, pte0, pte1);
1495 } else {
1496 stq_p(spapr->htab + offset, pte0);
1497 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1498 }
1499}
1500
1501int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1502{
1503 int shift;
1504
1505
1506
1507
1508 shift = ctz64(pow2ceil(ramsize)) - 7;
1509 shift = MAX(shift, 18);
1510 shift = MIN(shift, 46);
1511 return shift;
1512}
1513
1514void spapr_free_hpt(sPAPRMachineState *spapr)
1515{
1516 g_free(spapr->htab);
1517 spapr->htab = NULL;
1518 spapr->htab_shift = 0;
1519 close_htab_fd(spapr);
1520}
1521
1522void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1523 Error **errp)
1524{
1525 long rc;
1526
1527
1528 spapr_free_hpt(spapr);
1529
1530 rc = kvmppc_reset_htab(shift);
1531 if (rc < 0) {
1532
1533 error_setg_errno(errp, errno,
1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1535 shift);
1536
1537
1538 } else if (rc > 0) {
1539
1540 if (rc != shift) {
1541 error_setg(errp,
1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1543 shift, rc);
1544 }
1545
1546 spapr->htab_shift = shift;
1547 spapr->htab = NULL;
1548 } else {
1549
1550 size_t size = 1ULL << shift;
1551 int i;
1552
1553 spapr->htab = qemu_memalign(size, size);
1554 if (!spapr->htab) {
1555 error_setg_errno(errp, errno,
1556 "Could not allocate HPT of order %d", shift);
1557 return;
1558 }
1559
1560 memset(spapr->htab, 0, size);
1561 spapr->htab_shift = shift;
1562
1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1564 DIRTY_HPTE(HPTE(spapr->htab, i));
1565 }
1566 }
1567
1568 spapr->patb_entry = 0;
1569}
1570
1571void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1572{
1573 int hpt_shift;
1574
1575 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1576 || (spapr->cas_reboot
1577 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1578 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1579 } else {
1580 uint64_t current_ram_size;
1581
1582 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1583 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1584 }
1585 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1586
1587 if (spapr->vrma_adjust) {
1588 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1589 spapr->htab_shift);
1590 }
1591}
1592
1593static int spapr_reset_drcs(Object *child, void *opaque)
1594{
1595 sPAPRDRConnector *drc =
1596 (sPAPRDRConnector *) object_dynamic_cast(child,
1597 TYPE_SPAPR_DR_CONNECTOR);
1598
1599 if (drc) {
1600 spapr_drc_reset(drc);
1601 }
1602
1603 return 0;
1604}
1605
1606static void spapr_machine_reset(void)
1607{
1608 MachineState *machine = MACHINE(qdev_get_machine());
1609 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1610 PowerPCCPU *first_ppc_cpu;
1611 uint32_t rtas_limit;
1612 hwaddr rtas_addr, fdt_addr;
1613 void *fdt;
1614 int rc;
1615
1616 spapr_caps_apply(spapr);
1617
1618 first_ppc_cpu = POWERPC_CPU(first_cpu);
1619 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1620 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1621 spapr->max_compat_pvr)) {
1622
1623
1624
1625 spapr->patb_entry = PATBE1_GR;
1626 } else {
1627 spapr_setup_hpt_and_vrma(spapr);
1628 }
1629
1630
1631
1632 if (!spapr->cas_reboot) {
1633 spapr_ovec_cleanup(spapr->ov5_cas);
1634 spapr->ov5_cas = spapr_ovec_new();
1635
1636 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1637 }
1638
1639 qemu_devices_reset();
1640
1641
1642
1643
1644
1645
1646 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1647
1648 spapr_clear_pending_events(spapr);
1649
1650
1651
1652
1653
1654
1655 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1656 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1657 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1658
1659 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1660
1661 spapr_load_rtas(spapr, fdt, rtas_addr);
1662
1663 rc = fdt_pack(fdt);
1664
1665
1666 assert(rc == 0);
1667
1668 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1669 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1670 fdt_totalsize(fdt), FDT_MAX_SIZE);
1671 exit(1);
1672 }
1673
1674
1675 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1676 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1677 g_free(fdt);
1678
1679
1680 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1681 first_ppc_cpu->env.gpr[5] = 0;
1682
1683 spapr->cas_reboot = false;
1684}
1685
1686static void spapr_create_nvram(sPAPRMachineState *spapr)
1687{
1688 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1689 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1690
1691 if (dinfo) {
1692 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1693 &error_fatal);
1694 }
1695
1696 qdev_init_nofail(dev);
1697
1698 spapr->nvram = (struct sPAPRNVRAM *)dev;
1699}
1700
1701static void spapr_rtc_create(sPAPRMachineState *spapr)
1702{
1703 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1704 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1705 &error_fatal);
1706 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1707 &error_fatal);
1708 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1709 "date", &error_fatal);
1710}
1711
1712
1713static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1714{
1715 switch (vga_interface_type) {
1716 case VGA_NONE:
1717 return false;
1718 case VGA_DEVICE:
1719 return true;
1720 case VGA_STD:
1721 case VGA_VIRTIO:
1722 return pci_vga_init(pci_bus) != NULL;
1723 default:
1724 error_setg(errp,
1725 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1726 return false;
1727 }
1728}
1729
1730static int spapr_pre_load(void *opaque)
1731{
1732 int rc;
1733
1734 rc = spapr_caps_pre_load(opaque);
1735 if (rc) {
1736 return rc;
1737 }
1738
1739 return 0;
1740}
1741
1742static int spapr_post_load(void *opaque, int version_id)
1743{
1744 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1745 int err = 0;
1746
1747 err = spapr_caps_post_migration(spapr);
1748 if (err) {
1749 return err;
1750 }
1751
1752 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1753 CPUState *cs;
1754 CPU_FOREACH(cs) {
1755 PowerPCCPU *cpu = POWERPC_CPU(cs);
1756 icp_resend(ICP(cpu->intc));
1757 }
1758 }
1759
1760
1761
1762
1763
1764 if (version_id < 3) {
1765 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1766 }
1767
1768 if (kvm_enabled() && spapr->patb_entry) {
1769 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1770 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1771 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1772
1773 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1774 if (err) {
1775 error_report("Process table config unsupported by the host");
1776 return -EINVAL;
1777 }
1778 }
1779
1780 return err;
1781}
1782
1783static int spapr_pre_save(void *opaque)
1784{
1785 int rc;
1786
1787 rc = spapr_caps_pre_save(opaque);
1788 if (rc) {
1789 return rc;
1790 }
1791
1792 return 0;
1793}
1794
1795static bool version_before_3(void *opaque, int version_id)
1796{
1797 return version_id < 3;
1798}
1799
1800static bool spapr_pending_events_needed(void *opaque)
1801{
1802 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1803 return !QTAILQ_EMPTY(&spapr->pending_events);
1804}
1805
1806static const VMStateDescription vmstate_spapr_event_entry = {
1807 .name = "spapr_event_log_entry",
1808 .version_id = 1,
1809 .minimum_version_id = 1,
1810 .fields = (VMStateField[]) {
1811 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1812 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1813 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1814 NULL, extended_length),
1815 VMSTATE_END_OF_LIST()
1816 },
1817};
1818
1819static const VMStateDescription vmstate_spapr_pending_events = {
1820 .name = "spapr_pending_events",
1821 .version_id = 1,
1822 .minimum_version_id = 1,
1823 .needed = spapr_pending_events_needed,
1824 .fields = (VMStateField[]) {
1825 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1826 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1827 VMSTATE_END_OF_LIST()
1828 },
1829};
1830
1831static bool spapr_ov5_cas_needed(void *opaque)
1832{
1833 sPAPRMachineState *spapr = opaque;
1834 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1835 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1836 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1837 bool cas_needed;
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1865 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1866 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1867
1868
1869
1870
1871
1872
1873 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1874 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1875
1876 spapr_ovec_cleanup(ov5_mask);
1877 spapr_ovec_cleanup(ov5_legacy);
1878 spapr_ovec_cleanup(ov5_removed);
1879
1880 return cas_needed;
1881}
1882
1883static const VMStateDescription vmstate_spapr_ov5_cas = {
1884 .name = "spapr_option_vector_ov5_cas",
1885 .version_id = 1,
1886 .minimum_version_id = 1,
1887 .needed = spapr_ov5_cas_needed,
1888 .fields = (VMStateField[]) {
1889 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1890 vmstate_spapr_ovec, sPAPROptionVector),
1891 VMSTATE_END_OF_LIST()
1892 },
1893};
1894
1895static bool spapr_patb_entry_needed(void *opaque)
1896{
1897 sPAPRMachineState *spapr = opaque;
1898
1899 return !!spapr->patb_entry;
1900}
1901
1902static const VMStateDescription vmstate_spapr_patb_entry = {
1903 .name = "spapr_patb_entry",
1904 .version_id = 1,
1905 .minimum_version_id = 1,
1906 .needed = spapr_patb_entry_needed,
1907 .fields = (VMStateField[]) {
1908 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1909 VMSTATE_END_OF_LIST()
1910 },
1911};
1912
1913static const VMStateDescription vmstate_spapr = {
1914 .name = "spapr",
1915 .version_id = 3,
1916 .minimum_version_id = 1,
1917 .pre_load = spapr_pre_load,
1918 .post_load = spapr_post_load,
1919 .pre_save = spapr_pre_save,
1920 .fields = (VMStateField[]) {
1921
1922 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1923
1924
1925 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1926
1927 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1928 VMSTATE_END_OF_LIST()
1929 },
1930 .subsections = (const VMStateDescription*[]) {
1931 &vmstate_spapr_ov5_cas,
1932 &vmstate_spapr_patb_entry,
1933 &vmstate_spapr_pending_events,
1934 &vmstate_spapr_cap_htm,
1935 &vmstate_spapr_cap_vsx,
1936 &vmstate_spapr_cap_dfp,
1937 &vmstate_spapr_cap_cfpc,
1938 &vmstate_spapr_cap_sbbc,
1939 &vmstate_spapr_cap_ibs,
1940 NULL
1941 }
1942};
1943
1944static int htab_save_setup(QEMUFile *f, void *opaque)
1945{
1946 sPAPRMachineState *spapr = opaque;
1947
1948
1949 if (!spapr->htab_shift) {
1950 qemu_put_be32(f, -1);
1951 } else {
1952 qemu_put_be32(f, spapr->htab_shift);
1953 }
1954
1955 if (spapr->htab) {
1956 spapr->htab_save_index = 0;
1957 spapr->htab_first_pass = true;
1958 } else {
1959 if (spapr->htab_shift) {
1960 assert(kvm_enabled());
1961 }
1962 }
1963
1964
1965 return 0;
1966}
1967
1968static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1969 int chunkstart, int n_valid, int n_invalid)
1970{
1971 qemu_put_be32(f, chunkstart);
1972 qemu_put_be16(f, n_valid);
1973 qemu_put_be16(f, n_invalid);
1974 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1975 HASH_PTE_SIZE_64 * n_valid);
1976}
1977
1978static void htab_save_end_marker(QEMUFile *f)
1979{
1980 qemu_put_be32(f, 0);
1981 qemu_put_be16(f, 0);
1982 qemu_put_be16(f, 0);
1983}
1984
1985static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1986 int64_t max_ns)
1987{
1988 bool has_timeout = max_ns != -1;
1989 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1990 int index = spapr->htab_save_index;
1991 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1992
1993 assert(spapr->htab_first_pass);
1994
1995 do {
1996 int chunkstart;
1997
1998
1999 while ((index < htabslots)
2000 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2001 CLEAN_HPTE(HPTE(spapr->htab, index));
2002 index++;
2003 }
2004
2005
2006 chunkstart = index;
2007 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2008 && HPTE_VALID(HPTE(spapr->htab, index))) {
2009 CLEAN_HPTE(HPTE(spapr->htab, index));
2010 index++;
2011 }
2012
2013 if (index > chunkstart) {
2014 int n_valid = index - chunkstart;
2015
2016 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2017
2018 if (has_timeout &&
2019 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2020 break;
2021 }
2022 }
2023 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2024
2025 if (index >= htabslots) {
2026 assert(index == htabslots);
2027 index = 0;
2028 spapr->htab_first_pass = false;
2029 }
2030 spapr->htab_save_index = index;
2031}
2032
2033static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
2034 int64_t max_ns)
2035{
2036 bool final = max_ns < 0;
2037 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2038 int examined = 0, sent = 0;
2039 int index = spapr->htab_save_index;
2040 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2041
2042 assert(!spapr->htab_first_pass);
2043
2044 do {
2045 int chunkstart, invalidstart;
2046
2047
2048 while ((index < htabslots)
2049 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2050 index++;
2051 examined++;
2052 }
2053
2054 chunkstart = index;
2055
2056 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2057 && HPTE_DIRTY(HPTE(spapr->htab, index))
2058 && HPTE_VALID(HPTE(spapr->htab, index))) {
2059 CLEAN_HPTE(HPTE(spapr->htab, index));
2060 index++;
2061 examined++;
2062 }
2063
2064 invalidstart = index;
2065
2066 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2067 && HPTE_DIRTY(HPTE(spapr->htab, index))
2068 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2069 CLEAN_HPTE(HPTE(spapr->htab, index));
2070 index++;
2071 examined++;
2072 }
2073
2074 if (index > chunkstart) {
2075 int n_valid = invalidstart - chunkstart;
2076 int n_invalid = index - invalidstart;
2077
2078 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2079 sent += index - chunkstart;
2080
2081 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2082 break;
2083 }
2084 }
2085
2086 if (examined >= htabslots) {
2087 break;
2088 }
2089
2090 if (index >= htabslots) {
2091 assert(index == htabslots);
2092 index = 0;
2093 }
2094 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2095
2096 if (index >= htabslots) {
2097 assert(index == htabslots);
2098 index = 0;
2099 }
2100
2101 spapr->htab_save_index = index;
2102
2103 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2104}
2105
2106#define MAX_ITERATION_NS 5000000
2107#define MAX_KVM_BUF_SIZE 2048
2108
2109static int htab_save_iterate(QEMUFile *f, void *opaque)
2110{
2111 sPAPRMachineState *spapr = opaque;
2112 int fd;
2113 int rc = 0;
2114
2115
2116 if (!spapr->htab_shift) {
2117 qemu_put_be32(f, -1);
2118 return 1;
2119 } else {
2120 qemu_put_be32(f, 0);
2121 }
2122
2123 if (!spapr->htab) {
2124 assert(kvm_enabled());
2125
2126 fd = get_htab_fd(spapr);
2127 if (fd < 0) {
2128 return fd;
2129 }
2130
2131 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2132 if (rc < 0) {
2133 return rc;
2134 }
2135 } else if (spapr->htab_first_pass) {
2136 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2137 } else {
2138 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2139 }
2140
2141 htab_save_end_marker(f);
2142
2143 return rc;
2144}
2145
2146static int htab_save_complete(QEMUFile *f, void *opaque)
2147{
2148 sPAPRMachineState *spapr = opaque;
2149 int fd;
2150
2151
2152 if (!spapr->htab_shift) {
2153 qemu_put_be32(f, -1);
2154 return 0;
2155 } else {
2156 qemu_put_be32(f, 0);
2157 }
2158
2159 if (!spapr->htab) {
2160 int rc;
2161
2162 assert(kvm_enabled());
2163
2164 fd = get_htab_fd(spapr);
2165 if (fd < 0) {
2166 return fd;
2167 }
2168
2169 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2170 if (rc < 0) {
2171 return rc;
2172 }
2173 } else {
2174 if (spapr->htab_first_pass) {
2175 htab_save_first_pass(f, spapr, -1);
2176 }
2177 htab_save_later_pass(f, spapr, -1);
2178 }
2179
2180
2181 htab_save_end_marker(f);
2182
2183 return 0;
2184}
2185
2186static int htab_load(QEMUFile *f, void *opaque, int version_id)
2187{
2188 sPAPRMachineState *spapr = opaque;
2189 uint32_t section_hdr;
2190 int fd = -1;
2191 Error *local_err = NULL;
2192
2193 if (version_id < 1 || version_id > 1) {
2194 error_report("htab_load() bad version");
2195 return -EINVAL;
2196 }
2197
2198 section_hdr = qemu_get_be32(f);
2199
2200 if (section_hdr == -1) {
2201 spapr_free_hpt(spapr);
2202 return 0;
2203 }
2204
2205 if (section_hdr) {
2206
2207 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2208 if (local_err) {
2209 error_report_err(local_err);
2210 return -EINVAL;
2211 }
2212 return 0;
2213 }
2214
2215 if (!spapr->htab) {
2216 assert(kvm_enabled());
2217
2218 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2219 if (fd < 0) {
2220 error_report_err(local_err);
2221 return fd;
2222 }
2223 }
2224
2225 while (true) {
2226 uint32_t index;
2227 uint16_t n_valid, n_invalid;
2228
2229 index = qemu_get_be32(f);
2230 n_valid = qemu_get_be16(f);
2231 n_invalid = qemu_get_be16(f);
2232
2233 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2234
2235 break;
2236 }
2237
2238 if ((index + n_valid + n_invalid) >
2239 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2240
2241 error_report(
2242 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2243 index, n_valid, n_invalid, spapr->htab_shift);
2244 return -EINVAL;
2245 }
2246
2247 if (spapr->htab) {
2248 if (n_valid) {
2249 qemu_get_buffer(f, HPTE(spapr->htab, index),
2250 HASH_PTE_SIZE_64 * n_valid);
2251 }
2252 if (n_invalid) {
2253 memset(HPTE(spapr->htab, index + n_valid), 0,
2254 HASH_PTE_SIZE_64 * n_invalid);
2255 }
2256 } else {
2257 int rc;
2258
2259 assert(fd >= 0);
2260
2261 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2262 if (rc < 0) {
2263 return rc;
2264 }
2265 }
2266 }
2267
2268 if (!spapr->htab) {
2269 assert(fd >= 0);
2270 close(fd);
2271 }
2272
2273 return 0;
2274}
2275
2276static void htab_save_cleanup(void *opaque)
2277{
2278 sPAPRMachineState *spapr = opaque;
2279
2280 close_htab_fd(spapr);
2281}
2282
2283static SaveVMHandlers savevm_htab_handlers = {
2284 .save_setup = htab_save_setup,
2285 .save_live_iterate = htab_save_iterate,
2286 .save_live_complete_precopy = htab_save_complete,
2287 .save_cleanup = htab_save_cleanup,
2288 .load_state = htab_load,
2289};
2290
2291static void spapr_boot_set(void *opaque, const char *boot_device,
2292 Error **errp)
2293{
2294 MachineState *machine = MACHINE(opaque);
2295 machine->boot_order = g_strdup(boot_device);
2296}
2297
2298static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2299{
2300 MachineState *machine = MACHINE(spapr);
2301 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2302 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2303 int i;
2304
2305 for (i = 0; i < nr_lmbs; i++) {
2306 uint64_t addr;
2307
2308 addr = i * lmb_size + machine->device_memory->base;
2309 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2310 addr / lmb_size);
2311 }
2312}
2313
2314
2315
2316
2317
2318
2319static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2320{
2321 int i;
2322
2323 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2324 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2325 " is not aligned to %" PRIu64 " MiB",
2326 machine->ram_size,
2327 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2328 return;
2329 }
2330
2331 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2332 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2333 " is not aligned to %" PRIu64 " MiB",
2334 machine->ram_size,
2335 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2336 return;
2337 }
2338
2339 for (i = 0; i < nb_numa_nodes; i++) {
2340 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2341 error_setg(errp,
2342 "Node %d memory size 0x%" PRIx64
2343 " is not aligned to %" PRIu64 " MiB",
2344 i, numa_info[i].node_mem,
2345 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2346 return;
2347 }
2348 }
2349}
2350
2351
2352static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2353{
2354 int index = id / smp_threads;
2355
2356 if (index >= ms->possible_cpus->len) {
2357 return NULL;
2358 }
2359 if (idx) {
2360 *idx = index;
2361 }
2362 return &ms->possible_cpus->cpus[index];
2363}
2364
2365static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2366{
2367 Error *local_err = NULL;
2368 bool vsmt_user = !!spapr->vsmt;
2369 int kvm_smt = kvmppc_smt_threads();
2370 int ret;
2371
2372 if (!kvm_enabled() && (smp_threads > 1)) {
2373 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2374 "on a pseries machine");
2375 goto out;
2376 }
2377 if (!is_power_of_2(smp_threads)) {
2378 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2379 "machine because it must be a power of 2", smp_threads);
2380 goto out;
2381 }
2382
2383
2384 if (vsmt_user) {
2385 if (spapr->vsmt < smp_threads) {
2386 error_setg(&local_err, "Cannot support VSMT mode %d"
2387 " because it must be >= threads/core (%d)",
2388 spapr->vsmt, smp_threads);
2389 goto out;
2390 }
2391
2392 } else {
2393
2394
2395
2396
2397
2398
2399
2400 spapr->vsmt = MAX(8, smp_threads);
2401 }
2402
2403
2404 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2405 ret = kvmppc_set_smt_threads(spapr->vsmt);
2406 if (ret) {
2407
2408 error_setg(&local_err,
2409 "Failed to set KVM's VSMT mode to %d (errno %d)",
2410 spapr->vsmt, ret);
2411
2412
2413
2414
2415 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2416 warn_report_err(local_err);
2417 local_err = NULL;
2418 goto out;
2419 } else {
2420 if (!vsmt_user) {
2421 error_append_hint(&local_err,
2422 "On PPC, a VM with %d threads/core"
2423 " on a host with %d threads/core"
2424 " requires the use of VSMT mode %d.\n",
2425 smp_threads, kvm_smt, spapr->vsmt);
2426 }
2427 kvmppc_hint_smt_possible(&local_err);
2428 goto out;
2429 }
2430 }
2431 }
2432
2433out:
2434 error_propagate(errp, local_err);
2435}
2436
2437static void spapr_init_cpus(sPAPRMachineState *spapr)
2438{
2439 MachineState *machine = MACHINE(spapr);
2440 MachineClass *mc = MACHINE_GET_CLASS(machine);
2441 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2442 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2443 const CPUArchIdList *possible_cpus;
2444 int boot_cores_nr = smp_cpus / smp_threads;
2445 int i;
2446
2447 possible_cpus = mc->possible_cpu_arch_ids(machine);
2448 if (mc->has_hotpluggable_cpus) {
2449 if (smp_cpus % smp_threads) {
2450 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2451 smp_cpus, smp_threads);
2452 exit(1);
2453 }
2454 if (max_cpus % smp_threads) {
2455 error_report("max_cpus (%u) must be multiple of threads (%u)",
2456 max_cpus, smp_threads);
2457 exit(1);
2458 }
2459 } else {
2460 if (max_cpus != smp_cpus) {
2461 error_report("This machine version does not support CPU hotplug");
2462 exit(1);
2463 }
2464 boot_cores_nr = possible_cpus->len;
2465 }
2466
2467
2468
2469
2470 spapr_set_vsmt_mode(spapr, &error_fatal);
2471
2472 if (smc->pre_2_10_has_unused_icps) {
2473 int i;
2474
2475 for (i = 0; i < xics_max_server_number(spapr); i++) {
2476
2477
2478
2479 pre_2_10_vmstate_register_dummy_icp(i);
2480 }
2481 }
2482
2483 for (i = 0; i < possible_cpus->len; i++) {
2484 int core_id = i * smp_threads;
2485
2486 if (mc->has_hotpluggable_cpus) {
2487 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2488 spapr_vcpu_id(spapr, core_id));
2489 }
2490
2491 if (i < boot_cores_nr) {
2492 Object *core = object_new(type);
2493 int nr_threads = smp_threads;
2494
2495
2496 if ((i + 1) * smp_threads >= smp_cpus) {
2497 nr_threads = smp_cpus - i * smp_threads;
2498 }
2499
2500 object_property_set_int(core, nr_threads, "nr-threads",
2501 &error_fatal);
2502 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2503 &error_fatal);
2504 object_property_set_bool(core, true, "realized", &error_fatal);
2505 }
2506 }
2507}
2508
2509
2510static void spapr_machine_init(MachineState *machine)
2511{
2512 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2513 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2514 const char *kernel_filename = machine->kernel_filename;
2515 const char *initrd_filename = machine->initrd_filename;
2516 PCIHostState *phb;
2517 int i;
2518 MemoryRegion *sysmem = get_system_memory();
2519 MemoryRegion *ram = g_new(MemoryRegion, 1);
2520 hwaddr node0_size = spapr_node0_size(machine);
2521 long load_limit, fw_size;
2522 char *filename;
2523 Error *resize_hpt_err = NULL;
2524
2525 msi_nonbroken = true;
2526
2527 QLIST_INIT(&spapr->phbs);
2528 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2529
2530
2531 spapr_caps_init(spapr);
2532
2533 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2534 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2535
2536
2537
2538
2539
2540
2541 if (resize_hpt_err) {
2542 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2543 error_free(resize_hpt_err);
2544 resize_hpt_err = NULL;
2545 } else {
2546 spapr->resize_hpt = smc->resize_hpt_default;
2547 }
2548 }
2549
2550 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2551
2552 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2553
2554
2555
2556 error_report_err(resize_hpt_err);
2557 exit(1);
2558 }
2559
2560 spapr->rma_size = node0_size;
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571 if (kvm_enabled()) {
2572 spapr->vrma_adjust = 1;
2573 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2574 }
2575
2576
2577
2578
2579
2580
2581 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2582
2583 if (spapr->rma_size > node0_size) {
2584 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2585 spapr->rma_size);
2586 exit(1);
2587 }
2588
2589
2590 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2591
2592
2593 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2594
2595
2596
2597 spapr->ov5 = spapr_ovec_new();
2598 spapr->ov5_cas = spapr_ovec_new();
2599
2600 if (smc->dr_lmb_enabled) {
2601 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2602 spapr_validate_node_memory(machine, &error_fatal);
2603 }
2604
2605 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2606
2607
2608 if (spapr->use_hotplug_event_source) {
2609 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2610 }
2611
2612
2613 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2614 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2615 }
2616
2617
2618 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2619
2620
2621 spapr_init_cpus(spapr);
2622
2623 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2624 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2625 spapr->max_compat_pvr)) {
2626
2627 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2628 }
2629
2630
2631 if (kvm_enabled()) {
2632
2633 kvmppc_enable_logical_ci_hcalls();
2634 kvmppc_enable_set_mode_hcall();
2635
2636
2637 kvmppc_enable_clear_ref_mod_hcalls();
2638 }
2639
2640
2641 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2642 machine->ram_size);
2643 memory_region_add_subregion(sysmem, 0, ram);
2644
2645
2646 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2647
2648
2649 if (machine->ram_size < machine->maxram_size) {
2650 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2651
2652
2653
2654
2655
2656 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2657 SPAPR_MAX_RAM_SLOTS;
2658
2659 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2660 max_memslots = SPAPR_MAX_RAM_SLOTS;
2661 }
2662 if (machine->ram_slots > max_memslots) {
2663 error_report("Specified number of memory slots %"
2664 PRIu64" exceeds max supported %d",
2665 machine->ram_slots, max_memslots);
2666 exit(1);
2667 }
2668
2669 machine->device_memory->base = ROUND_UP(machine->ram_size,
2670 SPAPR_DEVICE_MEM_ALIGN);
2671 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2672 "device-memory", device_mem_size);
2673 memory_region_add_subregion(sysmem, machine->device_memory->base,
2674 &machine->device_memory->mr);
2675 }
2676
2677 if (smc->dr_lmb_enabled) {
2678 spapr_create_lmb_dr_connectors(spapr);
2679 }
2680
2681 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2682 if (!filename) {
2683 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2684 exit(1);
2685 }
2686 spapr->rtas_size = get_image_size(filename);
2687 if (spapr->rtas_size < 0) {
2688 error_report("Could not get size of LPAR rtas '%s'", filename);
2689 exit(1);
2690 }
2691 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2692 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2693 error_report("Could not load LPAR rtas '%s'", filename);
2694 exit(1);
2695 }
2696 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2697 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2698 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2699 exit(1);
2700 }
2701 g_free(filename);
2702
2703
2704 spapr_events_init(spapr);
2705
2706
2707 spapr_rtc_create(spapr);
2708
2709
2710 spapr->vio_bus = spapr_vio_bus_init();
2711
2712 for (i = 0; i < serial_max_hds(); i++) {
2713 if (serial_hd(i)) {
2714 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2715 }
2716 }
2717
2718
2719 spapr_create_nvram(spapr);
2720
2721
2722 spapr_pci_rtas_init();
2723
2724 phb = spapr_create_phb(spapr, 0);
2725
2726 for (i = 0; i < nb_nics; i++) {
2727 NICInfo *nd = &nd_table[i];
2728
2729 if (!nd->model) {
2730 nd->model = g_strdup("spapr-vlan");
2731 }
2732
2733 if (g_str_equal(nd->model, "spapr-vlan") ||
2734 g_str_equal(nd->model, "ibmveth")) {
2735 spapr_vlan_create(spapr->vio_bus, nd);
2736 } else {
2737 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2738 }
2739 }
2740
2741 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2742 spapr_vscsi_create(spapr->vio_bus);
2743 }
2744
2745
2746 if (spapr_vga_init(phb->bus, &error_fatal)) {
2747 spapr->has_graphics = true;
2748 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2749 }
2750
2751 if (machine->usb) {
2752 if (smc->use_ohci_by_default) {
2753 pci_create_simple(phb->bus, -1, "pci-ohci");
2754 } else {
2755 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2756 }
2757
2758 if (spapr->has_graphics) {
2759 USBBus *usb_bus = usb_bus_find(-1);
2760
2761 usb_create_simple(usb_bus, "usb-kbd");
2762 usb_create_simple(usb_bus, "usb-mouse");
2763 }
2764 }
2765
2766 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2767 error_report(
2768 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2769 MIN_RMA_SLOF);
2770 exit(1);
2771 }
2772
2773 if (kernel_filename) {
2774 uint64_t lowaddr = 0;
2775
2776 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2777 NULL, NULL, &lowaddr, NULL, 1,
2778 PPC_ELF_MACHINE, 0, 0);
2779 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2780 spapr->kernel_size = load_elf(kernel_filename,
2781 translate_kernel_address, NULL, NULL,
2782 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2783 0, 0);
2784 spapr->kernel_le = spapr->kernel_size > 0;
2785 }
2786 if (spapr->kernel_size < 0) {
2787 error_report("error loading %s: %s", kernel_filename,
2788 load_elf_strerror(spapr->kernel_size));
2789 exit(1);
2790 }
2791
2792
2793 if (initrd_filename) {
2794
2795
2796
2797 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2798 + 0x1ffff) & ~0xffff;
2799 spapr->initrd_size = load_image_targphys(initrd_filename,
2800 spapr->initrd_base,
2801 load_limit
2802 - spapr->initrd_base);
2803 if (spapr->initrd_size < 0) {
2804 error_report("could not load initial ram disk '%s'",
2805 initrd_filename);
2806 exit(1);
2807 }
2808 }
2809 }
2810
2811 if (bios_name == NULL) {
2812 bios_name = FW_FILE_NAME;
2813 }
2814 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2815 if (!filename) {
2816 error_report("Could not find LPAR firmware '%s'", bios_name);
2817 exit(1);
2818 }
2819 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2820 if (fw_size <= 0) {
2821 error_report("Could not load LPAR firmware '%s'", filename);
2822 exit(1);
2823 }
2824 g_free(filename);
2825
2826
2827
2828
2829 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2830 register_savevm_live(NULL, "spapr/htab", -1, 1,
2831 &savevm_htab_handlers, spapr);
2832
2833 qemu_register_boot_set(spapr_boot_set, spapr);
2834
2835 if (kvm_enabled()) {
2836
2837 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2838 &spapr->tb);
2839
2840 kvmppc_spapr_enable_inkernel_multitce();
2841 }
2842}
2843
2844static int spapr_kvm_type(const char *vm_type)
2845{
2846 if (!vm_type) {
2847 return 0;
2848 }
2849
2850 if (!strcmp(vm_type, "HV")) {
2851 return 1;
2852 }
2853
2854 if (!strcmp(vm_type, "PR")) {
2855 return 2;
2856 }
2857
2858 error_report("Unknown kvm-type specified '%s'", vm_type);
2859 exit(1);
2860}
2861
2862
2863
2864
2865
2866static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2867 DeviceState *dev)
2868{
2869#define CAST(type, obj, name) \
2870 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2871 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2872 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2873 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2874
2875 if (d) {
2876 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2877 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2878 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2879
2880 if (spapr) {
2881
2882
2883
2884
2885
2886 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2887 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2888 (uint64_t)id << 48);
2889 } else if (virtio) {
2890
2891
2892
2893
2894
2895
2896
2897 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2898 if (d->lun >= 256) {
2899
2900 id |= 0x4000;
2901 }
2902 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2903 (uint64_t)id << 32);
2904 } else if (usb) {
2905
2906
2907
2908
2909 unsigned usb_port = atoi(usb->port->path);
2910 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2911 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2912 (uint64_t)id << 32);
2913 }
2914 }
2915
2916
2917
2918
2919
2920
2921
2922 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2923 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2924 if (usb_host_dev_is_scsi_storage(usbdev)) {
2925 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2926 }
2927 }
2928
2929 if (phb) {
2930
2931 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2932 }
2933
2934 if (vsc) {
2935
2936 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2937 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2938 }
2939
2940 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2941
2942 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2943 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2944 }
2945
2946 return NULL;
2947}
2948
2949static char *spapr_get_kvm_type(Object *obj, Error **errp)
2950{
2951 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2952
2953 return g_strdup(spapr->kvm_type);
2954}
2955
2956static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2957{
2958 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2959
2960 g_free(spapr->kvm_type);
2961 spapr->kvm_type = g_strdup(value);
2962}
2963
2964static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2965{
2966 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2967
2968 return spapr->use_hotplug_event_source;
2969}
2970
2971static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2972 Error **errp)
2973{
2974 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2975
2976 spapr->use_hotplug_event_source = value;
2977}
2978
2979static bool spapr_get_msix_emulation(Object *obj, Error **errp)
2980{
2981 return true;
2982}
2983
2984static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2985{
2986 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2987
2988 switch (spapr->resize_hpt) {
2989 case SPAPR_RESIZE_HPT_DEFAULT:
2990 return g_strdup("default");
2991 case SPAPR_RESIZE_HPT_DISABLED:
2992 return g_strdup("disabled");
2993 case SPAPR_RESIZE_HPT_ENABLED:
2994 return g_strdup("enabled");
2995 case SPAPR_RESIZE_HPT_REQUIRED:
2996 return g_strdup("required");
2997 }
2998 g_assert_not_reached();
2999}
3000
3001static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3002{
3003 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3004
3005 if (strcmp(value, "default") == 0) {
3006 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3007 } else if (strcmp(value, "disabled") == 0) {
3008 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3009 } else if (strcmp(value, "enabled") == 0) {
3010 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3011 } else if (strcmp(value, "required") == 0) {
3012 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3013 } else {
3014 error_setg(errp, "Bad value for \"resize-hpt\" property");
3015 }
3016}
3017
3018static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3019 void *opaque, Error **errp)
3020{
3021 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3022}
3023
3024static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3025 void *opaque, Error **errp)
3026{
3027 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3028}
3029
3030static void spapr_instance_init(Object *obj)
3031{
3032 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3033
3034 spapr->htab_fd = -1;
3035 spapr->use_hotplug_event_source = true;
3036 object_property_add_str(obj, "kvm-type",
3037 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3038 object_property_set_description(obj, "kvm-type",
3039 "Specifies the KVM virtualization mode (HV, PR)",
3040 NULL);
3041 object_property_add_bool(obj, "modern-hotplug-events",
3042 spapr_get_modern_hotplug_events,
3043 spapr_set_modern_hotplug_events,
3044 NULL);
3045 object_property_set_description(obj, "modern-hotplug-events",
3046 "Use dedicated hotplug event mechanism in"
3047 " place of standard EPOW events when possible"
3048 " (required for memory hot-unplug support)",
3049 NULL);
3050 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3051 "Maximum permitted CPU compatibility mode",
3052 &error_fatal);
3053
3054 object_property_add_str(obj, "resize-hpt",
3055 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3056 object_property_set_description(obj, "resize-hpt",
3057 "Resizing of the Hash Page Table (enabled, disabled, required)",
3058 NULL);
3059 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3060 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3061 object_property_set_description(obj, "vsmt",
3062 "Virtual SMT: KVM behaves as if this were"
3063 " the host's SMT mode", &error_abort);
3064 object_property_add_bool(obj, "vfio-no-msix-emulation",
3065 spapr_get_msix_emulation, NULL, NULL);
3066}
3067
3068static void spapr_machine_finalizefn(Object *obj)
3069{
3070 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3071
3072 g_free(spapr->kvm_type);
3073}
3074
3075void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3076{
3077 cpu_synchronize_state(cs);
3078 ppc_cpu_do_system_reset(cs);
3079}
3080
3081static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3082{
3083 CPUState *cs;
3084
3085 CPU_FOREACH(cs) {
3086 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3087 }
3088}
3089
3090static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3091 uint32_t node, bool dedicated_hp_event_source,
3092 Error **errp)
3093{
3094 sPAPRDRConnector *drc;
3095 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3096 int i, fdt_offset, fdt_size;
3097 void *fdt;
3098 uint64_t addr = addr_start;
3099 bool hotplugged = spapr_drc_hotplugged(dev);
3100 Error *local_err = NULL;
3101
3102 for (i = 0; i < nr_lmbs; i++) {
3103 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3104 addr / SPAPR_MEMORY_BLOCK_SIZE);
3105 g_assert(drc);
3106
3107 fdt = create_device_tree(&fdt_size);
3108 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
3109 SPAPR_MEMORY_BLOCK_SIZE);
3110
3111 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3112 if (local_err) {
3113 while (addr > addr_start) {
3114 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3115 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3116 addr / SPAPR_MEMORY_BLOCK_SIZE);
3117 spapr_drc_detach(drc);
3118 }
3119 g_free(fdt);
3120 error_propagate(errp, local_err);
3121 return;
3122 }
3123 if (!hotplugged) {
3124 spapr_drc_reset(drc);
3125 }
3126 addr += SPAPR_MEMORY_BLOCK_SIZE;
3127 }
3128
3129
3130
3131 if (hotplugged) {
3132 if (dedicated_hp_event_source) {
3133 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3134 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3135 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3136 nr_lmbs,
3137 spapr_drc_index(drc));
3138 } else {
3139 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3140 nr_lmbs);
3141 }
3142 }
3143}
3144
3145static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3146 Error **errp)
3147{
3148 Error *local_err = NULL;
3149 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3150 PCDIMMDevice *dimm = PC_DIMM(dev);
3151 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3152 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3153 uint64_t align, size, addr;
3154 uint32_t node;
3155
3156 align = memory_region_get_alignment(mr);
3157 size = memory_region_size(mr);
3158
3159 pc_dimm_plug(dev, MACHINE(ms), align, &local_err);
3160 if (local_err) {
3161 goto out;
3162 }
3163
3164 addr = object_property_get_uint(OBJECT(dimm),
3165 PC_DIMM_ADDR_PROP, &local_err);
3166 if (local_err) {
3167 goto out_unplug;
3168 }
3169
3170 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP,
3171 &error_abort);
3172 spapr_add_lmbs(dev, addr, size, node,
3173 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3174 &local_err);
3175 if (local_err) {
3176 goto out_unplug;
3177 }
3178
3179 return;
3180
3181out_unplug:
3182 pc_dimm_unplug(dev, MACHINE(ms));
3183out:
3184 error_propagate(errp, local_err);
3185}
3186
3187static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3188 Error **errp)
3189{
3190 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3191 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3192 PCDIMMDevice *dimm = PC_DIMM(dev);
3193 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3194 MemoryRegion *mr;
3195 uint64_t size;
3196 Object *memdev;
3197 hwaddr pagesize;
3198
3199 if (!smc->dr_lmb_enabled) {
3200 error_setg(errp, "Memory hotplug not supported for this machine");
3201 return;
3202 }
3203
3204 mr = ddc->get_memory_region(dimm, errp);
3205 if (!mr) {
3206 return;
3207 }
3208 size = memory_region_size(mr);
3209
3210 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3211 error_setg(errp, "Hotplugged memory size must be a multiple of "
3212 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3213 return;
3214 }
3215
3216 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3217 &error_abort);
3218 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3219 spapr_check_pagesize(spapr, pagesize, errp);
3220}
3221
3222struct sPAPRDIMMState {
3223 PCDIMMDevice *dimm;
3224 uint32_t nr_lmbs;
3225 QTAILQ_ENTRY(sPAPRDIMMState) next;
3226};
3227
3228static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3229 PCDIMMDevice *dimm)
3230{
3231 sPAPRDIMMState *dimm_state = NULL;
3232
3233 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3234 if (dimm_state->dimm == dimm) {
3235 break;
3236 }
3237 }
3238 return dimm_state;
3239}
3240
3241static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3242 uint32_t nr_lmbs,
3243 PCDIMMDevice *dimm)
3244{
3245 sPAPRDIMMState *ds = NULL;
3246
3247
3248
3249
3250
3251
3252
3253 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3254 if (!ds) {
3255 ds = g_malloc0(sizeof(sPAPRDIMMState));
3256 ds->nr_lmbs = nr_lmbs;
3257 ds->dimm = dimm;
3258 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3259 }
3260 return ds;
3261}
3262
3263static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3264 sPAPRDIMMState *dimm_state)
3265{
3266 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3267 g_free(dimm_state);
3268}
3269
3270static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3271 PCDIMMDevice *dimm)
3272{
3273 sPAPRDRConnector *drc;
3274 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3275 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3276 uint64_t size = memory_region_size(mr);
3277 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3278 uint32_t avail_lmbs = 0;
3279 uint64_t addr_start, addr;
3280 int i;
3281
3282 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3283 &error_abort);
3284
3285 addr = addr_start;
3286 for (i = 0; i < nr_lmbs; i++) {
3287 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3288 addr / SPAPR_MEMORY_BLOCK_SIZE);
3289 g_assert(drc);
3290 if (drc->dev) {
3291 avail_lmbs++;
3292 }
3293 addr += SPAPR_MEMORY_BLOCK_SIZE;
3294 }
3295
3296 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3297}
3298
3299
3300void spapr_lmb_release(DeviceState *dev)
3301{
3302 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3303 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3304 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3305
3306
3307
3308 if (ds == NULL) {
3309 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3310 g_assert(ds);
3311
3312 g_assert(ds->nr_lmbs);
3313 }
3314
3315 if (--ds->nr_lmbs) {
3316 return;
3317 }
3318
3319
3320
3321
3322
3323 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3324}
3325
3326static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3327{
3328 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3329 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3330
3331 pc_dimm_unplug(dev, MACHINE(hotplug_dev));
3332 object_unparent(OBJECT(dev));
3333 spapr_pending_dimm_unplugs_remove(spapr, ds);
3334}
3335
3336static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3337 DeviceState *dev, Error **errp)
3338{
3339 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3340 Error *local_err = NULL;
3341 PCDIMMDevice *dimm = PC_DIMM(dev);
3342 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3343 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3344 uint32_t nr_lmbs;
3345 uint64_t size, addr_start, addr;
3346 int i;
3347 sPAPRDRConnector *drc;
3348
3349 size = memory_region_size(mr);
3350 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3351
3352 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3353 &local_err);
3354 if (local_err) {
3355 goto out;
3356 }
3357
3358
3359
3360
3361
3362
3363
3364 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3365 error_setg(&local_err,
3366 "Memory unplug already in progress for device %s",
3367 dev->id);
3368 goto out;
3369 }
3370
3371 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3372
3373 addr = addr_start;
3374 for (i = 0; i < nr_lmbs; i++) {
3375 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3376 addr / SPAPR_MEMORY_BLOCK_SIZE);
3377 g_assert(drc);
3378
3379 spapr_drc_detach(drc);
3380 addr += SPAPR_MEMORY_BLOCK_SIZE;
3381 }
3382
3383 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3384 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3385 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3386 nr_lmbs, spapr_drc_index(drc));
3387out:
3388 error_propagate(errp, local_err);
3389}
3390
3391static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3392 sPAPRMachineState *spapr)
3393{
3394 PowerPCCPU *cpu = POWERPC_CPU(cs);
3395 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3396 int id = spapr_get_vcpu_id(cpu);
3397 void *fdt;
3398 int offset, fdt_size;
3399 char *nodename;
3400
3401 fdt = create_device_tree(&fdt_size);
3402 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3403 offset = fdt_add_subnode(fdt, 0, nodename);
3404
3405 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3406 g_free(nodename);
3407
3408 *fdt_offset = offset;
3409 return fdt;
3410}
3411
3412
3413void spapr_core_release(DeviceState *dev)
3414{
3415 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3416
3417
3418 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3419}
3420
3421static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3422{
3423 MachineState *ms = MACHINE(hotplug_dev);
3424 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3425 CPUCore *cc = CPU_CORE(dev);
3426 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3427
3428 if (smc->pre_2_10_has_unused_icps) {
3429 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3430 int i;
3431
3432 for (i = 0; i < cc->nr_threads; i++) {
3433 CPUState *cs = CPU(sc->threads[i]);
3434
3435 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3436 }
3437 }
3438
3439 assert(core_slot);
3440 core_slot->cpu = NULL;
3441 object_unparent(OBJECT(dev));
3442}
3443
3444static
3445void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3446 Error **errp)
3447{
3448 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3449 int index;
3450 sPAPRDRConnector *drc;
3451 CPUCore *cc = CPU_CORE(dev);
3452
3453 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3454 error_setg(errp, "Unable to find CPU core with core-id: %d",
3455 cc->core_id);
3456 return;
3457 }
3458 if (index == 0) {
3459 error_setg(errp, "Boot CPU core may not be unplugged");
3460 return;
3461 }
3462
3463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3464 spapr_vcpu_id(spapr, cc->core_id));
3465 g_assert(drc);
3466
3467 spapr_drc_detach(drc);
3468
3469 spapr_hotplug_req_remove_by_index(drc);
3470}
3471
3472static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3473 Error **errp)
3474{
3475 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3476 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3477 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3478 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3479 CPUCore *cc = CPU_CORE(dev);
3480 CPUState *cs = CPU(core->threads[0]);
3481 sPAPRDRConnector *drc;
3482 Error *local_err = NULL;
3483 CPUArchId *core_slot;
3484 int index;
3485 bool hotplugged = spapr_drc_hotplugged(dev);
3486
3487 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3488 if (!core_slot) {
3489 error_setg(errp, "Unable to find CPU core with core-id: %d",
3490 cc->core_id);
3491 return;
3492 }
3493 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3494 spapr_vcpu_id(spapr, cc->core_id));
3495
3496 g_assert(drc || !mc->has_hotpluggable_cpus);
3497
3498 if (drc) {
3499 void *fdt;
3500 int fdt_offset;
3501
3502 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3503
3504 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3505 if (local_err) {
3506 g_free(fdt);
3507 error_propagate(errp, local_err);
3508 return;
3509 }
3510
3511 if (hotplugged) {
3512
3513
3514
3515
3516 spapr_hotplug_req_add_by_index(drc);
3517 } else {
3518 spapr_drc_reset(drc);
3519 }
3520 }
3521
3522 core_slot->cpu = OBJECT(dev);
3523
3524 if (smc->pre_2_10_has_unused_icps) {
3525 int i;
3526
3527 for (i = 0; i < cc->nr_threads; i++) {
3528 cs = CPU(core->threads[i]);
3529 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3530 }
3531 }
3532}
3533
3534static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3535 Error **errp)
3536{
3537 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3538 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3539 Error *local_err = NULL;
3540 CPUCore *cc = CPU_CORE(dev);
3541 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3542 const char *type = object_get_typename(OBJECT(dev));
3543 CPUArchId *core_slot;
3544 int index;
3545
3546 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3547 error_setg(&local_err, "CPU hotplug not supported for this machine");
3548 goto out;
3549 }
3550
3551 if (strcmp(base_core_type, type)) {
3552 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3553 goto out;
3554 }
3555
3556 if (cc->core_id % smp_threads) {
3557 error_setg(&local_err, "invalid core id %d", cc->core_id);
3558 goto out;
3559 }
3560
3561
3562
3563
3564
3565
3566
3567 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3568 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3569 cc->nr_threads, smp_threads);
3570 goto out;
3571 }
3572
3573 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3574 if (!core_slot) {
3575 error_setg(&local_err, "core id %d out of range", cc->core_id);
3576 goto out;
3577 }
3578
3579 if (core_slot->cpu) {
3580 error_setg(&local_err, "core %d already populated", cc->core_id);
3581 goto out;
3582 }
3583
3584 numa_cpu_pre_plug(core_slot, dev, &local_err);
3585
3586out:
3587 error_propagate(errp, local_err);
3588}
3589
3590static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3591 DeviceState *dev, Error **errp)
3592{
3593 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3594 spapr_memory_plug(hotplug_dev, dev, errp);
3595 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3596 spapr_core_plug(hotplug_dev, dev, errp);
3597 }
3598}
3599
3600static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
3601 DeviceState *dev, Error **errp)
3602{
3603 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3604 spapr_memory_unplug(hotplug_dev, dev);
3605 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3606 spapr_core_unplug(hotplug_dev, dev);
3607 }
3608}
3609
3610static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3611 DeviceState *dev, Error **errp)
3612{
3613 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3614 MachineClass *mc = MACHINE_GET_CLASS(sms);
3615
3616 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3617 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3618 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3619 } else {
3620
3621
3622
3623
3624
3625
3626 error_setg(errp, "Memory hot unplug not supported for this guest");
3627 }
3628 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3629 if (!mc->has_hotpluggable_cpus) {
3630 error_setg(errp, "CPU hot unplug not supported on this machine");
3631 return;
3632 }
3633 spapr_core_unplug_request(hotplug_dev, dev, errp);
3634 }
3635}
3636
3637static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3638 DeviceState *dev, Error **errp)
3639{
3640 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3641 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3642 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3643 spapr_core_pre_plug(hotplug_dev, dev, errp);
3644 }
3645}
3646
3647static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3648 DeviceState *dev)
3649{
3650 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3651 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3652 return HOTPLUG_HANDLER(machine);
3653 }
3654 return NULL;
3655}
3656
3657static CpuInstanceProperties
3658spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3659{
3660 CPUArchId *core_slot;
3661 MachineClass *mc = MACHINE_GET_CLASS(machine);
3662
3663
3664 mc->possible_cpu_arch_ids(machine);
3665
3666 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3667 assert(core_slot);
3668 return core_slot->props;
3669}
3670
3671static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3672{
3673 return idx / smp_cores % nb_numa_nodes;
3674}
3675
3676static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3677{
3678 int i;
3679 const char *core_type;
3680 int spapr_max_cores = max_cpus / smp_threads;
3681 MachineClass *mc = MACHINE_GET_CLASS(machine);
3682
3683 if (!mc->has_hotpluggable_cpus) {
3684 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3685 }
3686 if (machine->possible_cpus) {
3687 assert(machine->possible_cpus->len == spapr_max_cores);
3688 return machine->possible_cpus;
3689 }
3690
3691 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3692 if (!core_type) {
3693 error_report("Unable to find sPAPR CPU Core definition");
3694 exit(1);
3695 }
3696
3697 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3698 sizeof(CPUArchId) * spapr_max_cores);
3699 machine->possible_cpus->len = spapr_max_cores;
3700 for (i = 0; i < machine->possible_cpus->len; i++) {
3701 int core_id = i * smp_threads;
3702
3703 machine->possible_cpus->cpus[i].type = core_type;
3704 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3705 machine->possible_cpus->cpus[i].arch_id = core_id;
3706 machine->possible_cpus->cpus[i].props.has_core_id = true;
3707 machine->possible_cpus->cpus[i].props.core_id = core_id;
3708 }
3709 return machine->possible_cpus;
3710}
3711
3712static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3713 uint64_t *buid, hwaddr *pio,
3714 hwaddr *mmio32, hwaddr *mmio64,
3715 unsigned n_dma, uint32_t *liobns, Error **errp)
3716{
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732 const uint64_t base_buid = 0x800000020000000ULL;
3733#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3734 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3735 int i;
3736
3737
3738 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3739 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3740 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3741 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3742
3743 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3744 SPAPR_PCI_MEM32_WIN_SIZE);
3745 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3746 SPAPR_PCI_MEM64_WIN_SIZE);
3747
3748 if (index >= SPAPR_MAX_PHBS) {
3749 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3750 SPAPR_MAX_PHBS - 1);
3751 return;
3752 }
3753
3754 *buid = base_buid + index;
3755 for (i = 0; i < n_dma; ++i) {
3756 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3757 }
3758
3759 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3760 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3761 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3762}
3763
3764static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3765{
3766 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3767
3768 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3769}
3770
3771static void spapr_ics_resend(XICSFabric *dev)
3772{
3773 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3774
3775 ics_resend(spapr->ics);
3776}
3777
3778static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3779{
3780 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3781
3782 return cpu ? ICP(cpu->intc) : NULL;
3783}
3784
3785#define ICS_IRQ_FREE(ics, srcno) \
3786 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3787
3788static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3789{
3790 int first, i;
3791
3792 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3793 if (num > (ics->nr_irqs - first)) {
3794 return -1;
3795 }
3796 for (i = first; i < first + num; ++i) {
3797 if (!ICS_IRQ_FREE(ics, i)) {
3798 break;
3799 }
3800 }
3801 if (i == (first + num)) {
3802 return first;
3803 }
3804 }
3805
3806 return -1;
3807}
3808
3809int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
3810{
3811 ICSState *ics = spapr->ics;
3812 int first = -1;
3813
3814 assert(ics);
3815
3816
3817
3818
3819
3820
3821
3822
3823 if (align) {
3824 assert((num == 1) || (num == 2) || (num == 4) ||
3825 (num == 8) || (num == 16) || (num == 32));
3826 first = ics_find_free_block(ics, num, num);
3827 } else {
3828 first = ics_find_free_block(ics, num, 1);
3829 }
3830
3831 if (first < 0) {
3832 error_setg(errp, "can't find a free %d-IRQ block", num);
3833 return -1;
3834 }
3835
3836 return first + ics->offset;
3837}
3838
3839int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
3840{
3841 ICSState *ics = spapr->ics;
3842
3843 assert(ics);
3844
3845 if (!ics_valid_irq(ics, irq)) {
3846 error_setg(errp, "IRQ %d is invalid", irq);
3847 return -1;
3848 }
3849
3850 if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
3851 error_setg(errp, "IRQ %d is not free", irq);
3852 return -1;
3853 }
3854
3855 ics_set_irq_type(ics, irq - ics->offset, lsi);
3856 return 0;
3857}
3858
3859void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3860{
3861 ICSState *ics = spapr->ics;
3862 int srcno = irq - ics->offset;
3863 int i;
3864
3865 if (ics_valid_irq(ics, irq)) {
3866 trace_spapr_irq_free(0, irq, num);
3867 for (i = srcno; i < srcno + num; ++i) {
3868 if (ICS_IRQ_FREE(ics, i)) {
3869 trace_spapr_irq_free_warn(0, i + ics->offset);
3870 }
3871 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3872 }
3873 }
3874}
3875
3876qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3877{
3878 ICSState *ics = spapr->ics;
3879
3880 if (ics_valid_irq(ics, irq)) {
3881 return ics->qirqs[irq - ics->offset];
3882 }
3883
3884 return NULL;
3885}
3886
3887static void spapr_pic_print_info(InterruptStatsProvider *obj,
3888 Monitor *mon)
3889{
3890 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3891 CPUState *cs;
3892
3893 CPU_FOREACH(cs) {
3894 PowerPCCPU *cpu = POWERPC_CPU(cs);
3895
3896 icp_pic_print_info(ICP(cpu->intc), mon);
3897 }
3898
3899 ics_pic_print_info(spapr->ics, mon);
3900}
3901
3902int spapr_get_vcpu_id(PowerPCCPU *cpu)
3903{
3904 return cpu->vcpu_id;
3905}
3906
3907void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3908{
3909 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3910 int vcpu_id;
3911
3912 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
3913
3914 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3915 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3916 error_append_hint(errp, "Adjust the number of cpus to %d "
3917 "or try to raise the number of threads per core\n",
3918 vcpu_id * smp_threads / spapr->vsmt);
3919 return;
3920 }
3921
3922 cpu->vcpu_id = vcpu_id;
3923}
3924
3925PowerPCCPU *spapr_find_cpu(int vcpu_id)
3926{
3927 CPUState *cs;
3928
3929 CPU_FOREACH(cs) {
3930 PowerPCCPU *cpu = POWERPC_CPU(cs);
3931
3932 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
3933 return cpu;
3934 }
3935 }
3936
3937 return NULL;
3938}
3939
3940static void spapr_machine_class_init(ObjectClass *oc, void *data)
3941{
3942 MachineClass *mc = MACHINE_CLASS(oc);
3943 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3944 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3945 NMIClass *nc = NMI_CLASS(oc);
3946 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3947 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3948 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3949 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3950
3951 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3952
3953
3954
3955
3956
3957
3958 mc->init = spapr_machine_init;
3959 mc->reset = spapr_machine_reset;
3960 mc->block_default_type = IF_SCSI;
3961 mc->max_cpus = 1024;
3962 mc->no_parallel = 1;
3963 mc->default_boot_order = "";
3964 mc->default_ram_size = 512 * MiB;
3965 mc->default_display = "std";
3966 mc->kvm_type = spapr_kvm_type;
3967 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
3968 mc->pci_allow_0_address = true;
3969 assert(!mc->get_hotplug_handler);
3970 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3971 hc->pre_plug = spapr_machine_device_pre_plug;
3972 hc->plug = spapr_machine_device_plug;
3973 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3974 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3975 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3976 hc->unplug_request = spapr_machine_device_unplug_request;
3977 hc->unplug = spapr_machine_device_unplug;
3978
3979 smc->dr_lmb_enabled = true;
3980 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3981 mc->has_hotpluggable_cpus = true;
3982 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3983 fwc->get_dev_path = spapr_get_fw_dev_path;
3984 nc->nmi_monitor_handler = spapr_nmi;
3985 smc->phb_placement = spapr_phb_placement;
3986 vhc->hypercall = emulate_spapr_hypercall;
3987 vhc->hpt_mask = spapr_hpt_mask;
3988 vhc->map_hptes = spapr_map_hptes;
3989 vhc->unmap_hptes = spapr_unmap_hptes;
3990 vhc->store_hpte = spapr_store_hpte;
3991 vhc->get_patbe = spapr_get_patbe;
3992 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3993 xic->ics_get = spapr_ics_get;
3994 xic->ics_resend = spapr_ics_resend;
3995 xic->icp_get = spapr_icp_get;
3996 ispc->print_info = spapr_pic_print_info;
3997
3998
3999
4000
4001 mc->numa_mem_align_shift = 28;
4002
4003 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4004 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4005 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4006 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4007 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4008 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4009 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16;
4010 spapr_caps_add_properties(smc, &error_abort);
4011}
4012
4013static const TypeInfo spapr_machine_info = {
4014 .name = TYPE_SPAPR_MACHINE,
4015 .parent = TYPE_MACHINE,
4016 .abstract = true,
4017 .instance_size = sizeof(sPAPRMachineState),
4018 .instance_init = spapr_instance_init,
4019 .instance_finalize = spapr_machine_finalizefn,
4020 .class_size = sizeof(sPAPRMachineClass),
4021 .class_init = spapr_machine_class_init,
4022 .interfaces = (InterfaceInfo[]) {
4023 { TYPE_FW_PATH_PROVIDER },
4024 { TYPE_NMI },
4025 { TYPE_HOTPLUG_HANDLER },
4026 { TYPE_PPC_VIRTUAL_HYPERVISOR },
4027 { TYPE_XICS_FABRIC },
4028 { TYPE_INTERRUPT_STATS_PROVIDER },
4029 { }
4030 },
4031};
4032
4033#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4034 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4035 void *data) \
4036 { \
4037 MachineClass *mc = MACHINE_CLASS(oc); \
4038 spapr_machine_##suffix##_class_options(mc); \
4039 if (latest) { \
4040 mc->alias = "pseries"; \
4041 mc->is_default = 1; \
4042 } \
4043 } \
4044 static void spapr_machine_##suffix##_instance_init(Object *obj) \
4045 { \
4046 MachineState *machine = MACHINE(obj); \
4047 spapr_machine_##suffix##_instance_options(machine); \
4048 } \
4049 static const TypeInfo spapr_machine_##suffix##_info = { \
4050 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4051 .parent = TYPE_SPAPR_MACHINE, \
4052 .class_init = spapr_machine_##suffix##_class_init, \
4053 .instance_init = spapr_machine_##suffix##_instance_init, \
4054 }; \
4055 static void spapr_machine_register_##suffix(void) \
4056 { \
4057 type_register(&spapr_machine_##suffix##_info); \
4058 } \
4059 type_init(spapr_machine_register_##suffix)
4060
4061
4062
4063
4064static void spapr_machine_3_0_instance_options(MachineState *machine)
4065{
4066}
4067
4068static void spapr_machine_3_0_class_options(MachineClass *mc)
4069{
4070
4071}
4072
4073DEFINE_SPAPR_MACHINE(3_0, "3.0", true);
4074
4075
4076
4077
4078#define SPAPR_COMPAT_2_12 \
4079 HW_COMPAT_2_12 \
4080 { \
4081 .driver = TYPE_POWERPC_CPU, \
4082 .property = "pre-3.0-migration", \
4083 .value = "on", \
4084 }, \
4085 { \
4086 .driver = TYPE_SPAPR_CPU_CORE, \
4087 .property = "pre-3.0-migration", \
4088 .value = "on", \
4089 },
4090
4091static void spapr_machine_2_12_instance_options(MachineState *machine)
4092{
4093 spapr_machine_3_0_instance_options(machine);
4094}
4095
4096static void spapr_machine_2_12_class_options(MachineClass *mc)
4097{
4098 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4099
4100 spapr_machine_3_0_class_options(mc);
4101 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12);
4102
4103
4104
4105
4106
4107
4108 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4109}
4110
4111DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4112
4113static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine)
4114{
4115 spapr_machine_2_12_instance_options(machine);
4116}
4117
4118static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4119{
4120 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4121
4122 spapr_machine_2_12_class_options(mc);
4123 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4124 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4125 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4126}
4127
4128DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4129
4130
4131
4132
4133#define SPAPR_COMPAT_2_11 \
4134 HW_COMPAT_2_11
4135
4136static void spapr_machine_2_11_instance_options(MachineState *machine)
4137{
4138 spapr_machine_2_12_instance_options(machine);
4139}
4140
4141static void spapr_machine_2_11_class_options(MachineClass *mc)
4142{
4143 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4144
4145 spapr_machine_2_12_class_options(mc);
4146 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4147 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
4148}
4149
4150DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4151
4152
4153
4154
4155#define SPAPR_COMPAT_2_10 \
4156 HW_COMPAT_2_10
4157
4158static void spapr_machine_2_10_instance_options(MachineState *machine)
4159{
4160 spapr_machine_2_11_instance_options(machine);
4161}
4162
4163static void spapr_machine_2_10_class_options(MachineClass *mc)
4164{
4165 spapr_machine_2_11_class_options(mc);
4166 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
4167}
4168
4169DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4170
4171
4172
4173
4174#define SPAPR_COMPAT_2_9 \
4175 HW_COMPAT_2_9 \
4176 { \
4177 .driver = TYPE_POWERPC_CPU, \
4178 .property = "pre-2.10-migration", \
4179 .value = "on", \
4180 }, \
4181
4182static void spapr_machine_2_9_instance_options(MachineState *machine)
4183{
4184 spapr_machine_2_10_instance_options(machine);
4185}
4186
4187static void spapr_machine_2_9_class_options(MachineClass *mc)
4188{
4189 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4190
4191 spapr_machine_2_10_class_options(mc);
4192 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4193 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4194 smc->pre_2_10_has_unused_icps = true;
4195 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4196}
4197
4198DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4199
4200
4201
4202
4203#define SPAPR_COMPAT_2_8 \
4204 HW_COMPAT_2_8 \
4205 { \
4206 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4207 .property = "pcie-extended-configuration-space", \
4208 .value = "off", \
4209 },
4210
4211static void spapr_machine_2_8_instance_options(MachineState *machine)
4212{
4213 spapr_machine_2_9_instance_options(machine);
4214}
4215
4216static void spapr_machine_2_8_class_options(MachineClass *mc)
4217{
4218 spapr_machine_2_9_class_options(mc);
4219 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4220 mc->numa_mem_align_shift = 23;
4221}
4222
4223DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4224
4225
4226
4227
4228#define SPAPR_COMPAT_2_7 \
4229 HW_COMPAT_2_7 \
4230 { \
4231 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4232 .property = "mem_win_size", \
4233 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4234 }, \
4235 { \
4236 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4237 .property = "mem64_win_size", \
4238 .value = "0", \
4239 }, \
4240 { \
4241 .driver = TYPE_POWERPC_CPU, \
4242 .property = "pre-2.8-migration", \
4243 .value = "on", \
4244 }, \
4245 { \
4246 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4247 .property = "pre-2.8-migration", \
4248 .value = "on", \
4249 },
4250
4251static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4252 uint64_t *buid, hwaddr *pio,
4253 hwaddr *mmio32, hwaddr *mmio64,
4254 unsigned n_dma, uint32_t *liobns, Error **errp)
4255{
4256
4257 const uint64_t base_buid = 0x800000020000000ULL;
4258 const hwaddr phb_spacing = 0x1000000000ULL;
4259 const hwaddr mmio_offset = 0xa0000000;
4260 const hwaddr pio_offset = 0x80000000;
4261 const uint32_t max_index = 255;
4262 const hwaddr phb0_alignment = 0x10000000000ULL;
4263
4264 uint64_t ram_top = MACHINE(spapr)->ram_size;
4265 hwaddr phb0_base, phb_base;
4266 int i;
4267
4268
4269 if (MACHINE(spapr)->maxram_size > ram_top) {
4270
4271
4272
4273 ram_top = MACHINE(spapr)->device_memory->base +
4274 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4275 }
4276
4277 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4278
4279 if (index > max_index) {
4280 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4281 max_index);
4282 return;
4283 }
4284
4285 *buid = base_buid + index;
4286 for (i = 0; i < n_dma; ++i) {
4287 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4288 }
4289
4290 phb_base = phb0_base + index * phb_spacing;
4291 *pio = phb_base + pio_offset;
4292 *mmio32 = phb_base + mmio_offset;
4293
4294
4295
4296
4297
4298}
4299
4300static void spapr_machine_2_7_instance_options(MachineState *machine)
4301{
4302 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4303
4304 spapr_machine_2_8_instance_options(machine);
4305 spapr->use_hotplug_event_source = false;
4306}
4307
4308static void spapr_machine_2_7_class_options(MachineClass *mc)
4309{
4310 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4311
4312 spapr_machine_2_8_class_options(mc);
4313 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4314 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4315 smc->phb_placement = phb_placement_2_7;
4316}
4317
4318DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4319
4320
4321
4322
4323#define SPAPR_COMPAT_2_6 \
4324 HW_COMPAT_2_6 \
4325 { \
4326 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4327 .property = "ddw",\
4328 .value = stringify(off),\
4329 },
4330
4331static void spapr_machine_2_6_instance_options(MachineState *machine)
4332{
4333 spapr_machine_2_7_instance_options(machine);
4334}
4335
4336static void spapr_machine_2_6_class_options(MachineClass *mc)
4337{
4338 spapr_machine_2_7_class_options(mc);
4339 mc->has_hotpluggable_cpus = false;
4340 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4341}
4342
4343DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4344
4345
4346
4347
4348#define SPAPR_COMPAT_2_5 \
4349 HW_COMPAT_2_5 \
4350 { \
4351 .driver = "spapr-vlan", \
4352 .property = "use-rx-buffer-pools", \
4353 .value = "off", \
4354 },
4355
4356static void spapr_machine_2_5_instance_options(MachineState *machine)
4357{
4358 spapr_machine_2_6_instance_options(machine);
4359}
4360
4361static void spapr_machine_2_5_class_options(MachineClass *mc)
4362{
4363 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4364
4365 spapr_machine_2_6_class_options(mc);
4366 smc->use_ohci_by_default = true;
4367 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4368}
4369
4370DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4371
4372
4373
4374
4375#define SPAPR_COMPAT_2_4 \
4376 HW_COMPAT_2_4
4377
4378static void spapr_machine_2_4_instance_options(MachineState *machine)
4379{
4380 spapr_machine_2_5_instance_options(machine);
4381}
4382
4383static void spapr_machine_2_4_class_options(MachineClass *mc)
4384{
4385 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4386
4387 spapr_machine_2_5_class_options(mc);
4388 smc->dr_lmb_enabled = false;
4389 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4390}
4391
4392DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4393
4394
4395
4396
4397#define SPAPR_COMPAT_2_3 \
4398 HW_COMPAT_2_3 \
4399 {\
4400 .driver = "spapr-pci-host-bridge",\
4401 .property = "dynamic-reconfiguration",\
4402 .value = "off",\
4403 },
4404
4405static void spapr_machine_2_3_instance_options(MachineState *machine)
4406{
4407 spapr_machine_2_4_instance_options(machine);
4408}
4409
4410static void spapr_machine_2_3_class_options(MachineClass *mc)
4411{
4412 spapr_machine_2_4_class_options(mc);
4413 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4414}
4415DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4416
4417
4418
4419
4420
4421#define SPAPR_COMPAT_2_2 \
4422 HW_COMPAT_2_2 \
4423 {\
4424 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4425 .property = "mem_win_size",\
4426 .value = "0x20000000",\
4427 },
4428
4429static void spapr_machine_2_2_instance_options(MachineState *machine)
4430{
4431 spapr_machine_2_3_instance_options(machine);
4432 machine->suppress_vmdesc = true;
4433}
4434
4435static void spapr_machine_2_2_class_options(MachineClass *mc)
4436{
4437 spapr_machine_2_3_class_options(mc);
4438 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4439}
4440DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4441
4442
4443
4444
4445#define SPAPR_COMPAT_2_1 \
4446 HW_COMPAT_2_1
4447
4448static void spapr_machine_2_1_instance_options(MachineState *machine)
4449{
4450 spapr_machine_2_2_instance_options(machine);
4451}
4452
4453static void spapr_machine_2_1_class_options(MachineClass *mc)
4454{
4455 spapr_machine_2_2_class_options(mc);
4456 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4457}
4458DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4459
4460static void spapr_machine_register_types(void)
4461{
4462 type_register_static(&spapr_machine_info);
4463}
4464
4465type_init(spapr_machine_register_types)
4466