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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "sysemu/sysemu.h"
28#include "hw/ptimer.h"
29#include "qemu/log.h"
30#include "qemu/bitops.h"
31#include "hw/ssi/xilinx_spips.h"
32#include "qapi/error.h"
33#include "hw/register.h"
34#include "sysemu/dma.h"
35#include "migration/blocker.h"
36
37#ifndef XILINX_SPIPS_ERR_DEBUG
38#define XILINX_SPIPS_ERR_DEBUG 0
39#endif
40
41#define DB_PRINT_L(level, ...) do { \
42 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
43 fprintf(stderr, ": %s: ", __func__); \
44 fprintf(stderr, ## __VA_ARGS__); \
45 } \
46} while (0)
47
48
49#define R_CONFIG (0x00 / 4)
50#define IFMODE (1U << 31)
51#define R_CONFIG_ENDIAN (1 << 26)
52#define MODEFAIL_GEN_EN (1 << 17)
53#define MAN_START_COM (1 << 16)
54#define MAN_START_EN (1 << 15)
55#define MANUAL_CS (1 << 14)
56#define CS (0xF << 10)
57#define CS_SHIFT (10)
58#define PERI_SEL (1 << 9)
59#define REF_CLK (1 << 8)
60#define FIFO_WIDTH (3 << 6)
61#define BAUD_RATE_DIV (7 << 3)
62#define CLK_PH (1 << 2)
63#define CLK_POL (1 << 1)
64#define MODE_SEL (1 << 0)
65#define R_CONFIG_RSVD (0x7bf40000)
66
67
68#define R_INTR_STATUS (0x04 / 4)
69#define R_INTR_STATUS_RESET (0x104)
70#define R_INTR_EN (0x08 / 4)
71#define R_INTR_DIS (0x0C / 4)
72#define R_INTR_MASK (0x10 / 4)
73#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
74
75#define IXR_RX_FIFO_EMPTY (1 << 11)
76#define IXR_GENERIC_FIFO_FULL (1 << 10)
77#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
78#define IXR_TX_FIFO_EMPTY (1 << 8)
79#define IXR_GENERIC_FIFO_EMPTY (1 << 7)
80#define IXR_RX_FIFO_FULL (1 << 5)
81#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
82#define IXR_TX_FIFO_FULL (1 << 3)
83#define IXR_TX_FIFO_NOT_FULL (1 << 2)
84#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
85#define IXR_RX_FIFO_OVERFLOW (1 << 0)
86#define IXR_ALL ((1 << 13) - 1)
87#define GQSPI_IXR_MASK 0xFBE
88#define IXR_SELF_CLEAR \
89(IXR_GENERIC_FIFO_EMPTY \
90| IXR_GENERIC_FIFO_FULL \
91| IXR_GENERIC_FIFO_NOT_FULL \
92| IXR_TX_FIFO_EMPTY \
93| IXR_TX_FIFO_FULL \
94| IXR_TX_FIFO_NOT_FULL \
95| IXR_RX_FIFO_EMPTY \
96| IXR_RX_FIFO_FULL \
97| IXR_RX_FIFO_NOT_EMPTY)
98
99#define R_EN (0x14 / 4)
100#define R_DELAY (0x18 / 4)
101#define R_TX_DATA (0x1C / 4)
102#define R_RX_DATA (0x20 / 4)
103#define R_SLAVE_IDLE_COUNT (0x24 / 4)
104#define R_TX_THRES (0x28 / 4)
105#define R_RX_THRES (0x2C / 4)
106#define R_GPIO (0x30 / 4)
107#define R_LPBK_DLY_ADJ (0x38 / 4)
108#define R_LPBK_DLY_ADJ_RESET (0x33)
109#define R_TXD1 (0x80 / 4)
110#define R_TXD2 (0x84 / 4)
111#define R_TXD3 (0x88 / 4)
112
113#define R_LQSPI_CFG (0xa0 / 4)
114#define R_LQSPI_CFG_RESET 0x03A002EB
115#define LQSPI_CFG_LQ_MODE (1U << 31)
116#define LQSPI_CFG_TWO_MEM (1 << 30)
117#define LQSPI_CFG_SEP_BUS (1 << 29)
118#define LQSPI_CFG_U_PAGE (1 << 28)
119#define LQSPI_CFG_ADDR4 (1 << 27)
120#define LQSPI_CFG_MODE_EN (1 << 25)
121#define LQSPI_CFG_MODE_WIDTH 8
122#define LQSPI_CFG_MODE_SHIFT 16
123#define LQSPI_CFG_DUMMY_WIDTH 3
124#define LQSPI_CFG_DUMMY_SHIFT 8
125#define LQSPI_CFG_INST_CODE 0xFF
126
127#define R_CMND (0xc0 / 4)
128 #define R_CMND_RXFIFO_DRAIN (1 << 19)
129 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3)
130#define R_CMND_EXT_ADD (1 << 15)
131 FIELD(CMND, RX_DISCARD, 8, 7)
132 FIELD(CMND, DUMMY_CYCLES, 2, 6)
133#define R_CMND_DMA_EN (1 << 1)
134#define R_CMND_PUSH_WAIT (1 << 0)
135#define R_TRANSFER_SIZE (0xc4 / 4)
136#define R_LQSPI_STS (0xA4 / 4)
137#define LQSPI_STS_WR_RECVD (1 << 1)
138
139#define R_MOD_ID (0xFC / 4)
140
141#define R_GQSPI_SELECT (0x144 / 4)
142 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
143#define R_GQSPI_ISR (0x104 / 4)
144#define R_GQSPI_IER (0x108 / 4)
145#define R_GQSPI_IDR (0x10c / 4)
146#define R_GQSPI_IMR (0x110 / 4)
147#define R_GQSPI_IMR_RESET (0xfbe)
148#define R_GQSPI_TX_THRESH (0x128 / 4)
149#define R_GQSPI_RX_THRESH (0x12c / 4)
150#define R_GQSPI_GPIO (0x130 / 4)
151#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
152#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
153#define R_GQSPI_CNFG (0x100 / 4)
154 FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
155 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)
156 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1)
157 FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
158
159 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
160
161 FIELD(GQSPI_CNFG, BR, 3, 3)
162 FIELD(GQSPI_CNFG, CPH, 2, 1)
163 FIELD(GQSPI_CNFG, CPL, 1, 1)
164#define R_GQSPI_GEN_FIFO (0x140 / 4)
165#define R_GQSPI_TXD (0x11c / 4)
166#define R_GQSPI_RXD (0x120 / 4)
167#define R_GQSPI_FIFO_CTRL (0x14c / 4)
168 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1)
169 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1)
170 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1)
171#define R_GQSPI_GFIFO_THRESH (0x150 / 4)
172#define R_GQSPI_DATA_STS (0x15c / 4)
173
174
175
176
177#define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
178 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1)
179 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1)
180 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1)
181 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1)
182 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2)
183 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2)
184 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2)
185 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
186 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
187 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
188#define R_GQSPI_MOD_ID (0x1fc / 4)
189#define R_GQSPI_MOD_ID_RESET (0x10a0000)
190
191#define R_QSPIDMA_DST_CTRL (0x80c / 4)
192#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
193#define R_QSPIDMA_DST_I_MASK (0x820 / 4)
194#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
195#define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
196#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
197
198
199#define RXFF_A (128)
200#define TXFF_A (128)
201
202#define RXFF_A_Q (64 * 4)
203#define TXFF_A_Q (64 * 4)
204
205
206#define LQSPI_ADDRESS_BITS 24
207
208#define SNOOP_CHECKING 0xFF
209#define SNOOP_ADDR 0xF0
210#define SNOOP_NONE 0xEE
211#define SNOOP_STRIPING 0
212
213#define MIN_NUM_BUSSES 1
214#define MAX_NUM_BUSSES 2
215
216static inline int num_effective_busses(XilinxSPIPS *s)
217{
218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
220}
221
222static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
223{
224 int i;
225
226 for (i = 0; i < s->num_cs * s->num_busses; i++) {
227 bool old_state = s->cs_lines_state[i];
228 bool new_state = field & (1 << i);
229
230 if (old_state != new_state) {
231 s->cs_lines_state[i] = new_state;
232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
233 DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i);
234 }
235 qemu_set_irq(s->cs_lines[i], !new_state);
236 }
237 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
238 s->snoop_state = SNOOP_CHECKING;
239 s->cmd_dummies = 0;
240 s->link_state = 1;
241 s->link_state_next = 1;
242 s->link_state_next_when = 0;
243 DB_PRINT_L(1, "moving to snoop check state\n");
244 }
245}
246
247static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
248{
249 if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
250 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
251 bool upper_cs_sel = field & (1 << 1);
252 bool lower_cs_sel = field & 1;
253 bool bus0_enabled;
254 bool bus1_enabled;
255 uint8_t buses;
256 int cs = 0;
257
258 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
259 bus0_enabled = buses & 1;
260 bus1_enabled = buses & (1 << 1);
261
262 if (bus0_enabled && bus1_enabled) {
263 if (lower_cs_sel) {
264 cs |= 1;
265 }
266 if (upper_cs_sel) {
267 cs |= 1 << 3;
268 }
269 } else if (bus0_enabled) {
270 if (lower_cs_sel) {
271 cs |= 1;
272 }
273 if (upper_cs_sel) {
274 cs |= 1 << 1;
275 }
276 } else if (bus1_enabled) {
277 if (lower_cs_sel) {
278 cs |= 1 << 2;
279 }
280 if (upper_cs_sel) {
281 cs |= 1 << 3;
282 }
283 }
284 xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
285 }
286}
287
288static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
289{
290 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT);
291
292
293 if (num_effective_busses(s) == 2) {
294
295 field &= 0x1;
296 field |= field << 3;
297
298 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
299 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
300
301 field &= 0x1;
302
303 field <<= 1;
304 }
305
306 if (!(s->regs[R_CONFIG] & MANUAL_CS) &&
307 fifo8_is_empty(&s->tx_fifo)) {
308 field = 0;
309 }
310 xilinx_spips_update_cs(s, field);
311}
312
313static void xilinx_spips_update_ixr(XilinxSPIPS *s)
314{
315 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
316 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR;
317 s->regs[R_INTR_STATUS] |=
318 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
319 (s->rx_fifo.num >= s->regs[R_RX_THRES] ?
320 IXR_RX_FIFO_NOT_EMPTY : 0) |
321 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
322 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) |
323 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
324 }
325 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
326 IXR_ALL);
327 if (new_irqline != s->irqline) {
328 s->irqline = new_irqline;
329 qemu_set_irq(s->irq, s->irqline);
330 }
331}
332
333static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s)
334{
335 uint32_t gqspi_int;
336 int new_irqline;
337
338 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR;
339 s->regs[R_GQSPI_ISR] |=
340 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) |
341 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) |
342 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ?
343 IXR_GENERIC_FIFO_NOT_FULL : 0) |
344 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) |
345 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) |
346 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ?
347 IXR_RX_FIFO_NOT_EMPTY : 0) |
348 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) |
349 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) |
350 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ?
351 IXR_TX_FIFO_NOT_FULL : 0);
352
353
354 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK;
355 new_irqline = !!(gqspi_int & IXR_ALL);
356
357
358 if (new_irqline != s->gqspi_irqline) {
359 s->gqspi_irqline = new_irqline;
360 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline);
361 }
362}
363
364static void xilinx_spips_reset(DeviceState *d)
365{
366 XilinxSPIPS *s = XILINX_SPIPS(d);
367
368 memset(s->regs, 0, sizeof(s->regs));
369
370 fifo8_reset(&s->rx_fifo);
371 fifo8_reset(&s->rx_fifo);
372
373 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
374 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
375 s->regs[R_TX_THRES] = 1;
376 s->regs[R_RX_THRES] = 1;
377
378 s->regs[R_MOD_ID] = 0x01090106;
379 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
380 s->link_state = 1;
381 s->link_state_next = 1;
382 s->link_state_next_when = 0;
383 s->snoop_state = SNOOP_CHECKING;
384 s->cmd_dummies = 0;
385 s->man_start_com = false;
386 xilinx_spips_update_ixr(s);
387 xilinx_spips_update_cs_lines(s);
388}
389
390static void xlnx_zynqmp_qspips_reset(DeviceState *d)
391{
392 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
393
394 xilinx_spips_reset(d);
395
396 memset(s->regs, 0, sizeof(s->regs));
397
398 fifo8_reset(&s->rx_fifo_g);
399 fifo8_reset(&s->rx_fifo_g);
400 fifo32_reset(&s->fifo_g);
401 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
402 s->regs[R_GPIO] = 1;
403 s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
404 s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
405 s->regs[R_MOD_ID] = 0x01090101;
406 s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
407 s->regs[R_GQSPI_TX_THRESH] = 1;
408 s->regs[R_GQSPI_RX_THRESH] = 1;
409 s->regs[R_GQSPI_GPIO] = 1;
410 s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
411 s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
412 s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
413 s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
414 s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
415 s->man_start_com_g = false;
416 s->gqspi_irqline = 0;
417 xlnx_zynqmp_qspips_update_ixr(s);
418}
419
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428
429
430static inline void stripe8(uint8_t *x, int num, bool dir)
431{
432 uint8_t r[num];
433 memset(r, 0, sizeof(uint8_t) * num);
434 int idx[2] = {0, 0};
435 int bit[2] = {0, 7};
436 int d = dir;
437
438 for (idx[0] = 0; idx[0] < num; ++idx[0]) {
439 for (bit[0] = 7; bit[0] >= 0; bit[0]--) {
440 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
441 idx[1] = (idx[1] + 1) % num;
442 if (!idx[1]) {
443 bit[1]--;
444 }
445 }
446 }
447 memcpy(x, r, sizeof(uint8_t) * num);
448}
449
450static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
451{
452 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) {
453 uint8_t tx_rx[2] = { 0 };
454 int num_stripes = 1;
455 uint8_t busses;
456 int i;
457
458 if (!s->regs[R_GQSPI_DATA_STS]) {
459 uint8_t imm;
460
461 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g);
462 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]);
463 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
464 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
465 continue;
466 }
467 xlnx_zynqmp_qspips_update_cs_lines(s);
468
469 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
470 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
471
472 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
473 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
474 s->regs[R_GQSPI_DATA_STS] = 1;
475
476 } else {
477 s->regs[R_GQSPI_DATA_STS] = 0;
478 }
479 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) {
480 if (imm > 31) {
481 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too"
482 " long - 2 ^ %" PRId8 " requested\n", imm);
483 }
484 s->regs[R_GQSPI_DATA_STS] = 1ul << imm;
485 } else {
486 s->regs[R_GQSPI_DATA_STS] = imm;
487 }
488 }
489
490 if (!s->regs[R_GQSPI_DATA_STS]) {
491 continue;
492 }
493 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) &&
494 fifo8_is_full(&s->rx_fifo_g)) {
495
496 return;
497 }
498 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) &&
499 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
500 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) {
501 num_stripes = 2;
502 }
503 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
504 tx_rx[0] = ARRAY_FIELD_EX32(s->regs,
505 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
506 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) {
507 for (i = 0; i < num_stripes; ++i) {
508 if (!fifo8_is_empty(&s->tx_fifo_g)) {
509 tx_rx[i] = fifo8_pop(&s->tx_fifo_g);
510 s->tx_fifo_g_align++;
511 } else {
512 return;
513 }
514 }
515 }
516 if (num_stripes == 1) {
517
518 tx_rx[1] = tx_rx[0];
519 }
520 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
521 for (i = 0; i < 2; ++i) {
522 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);
523 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]);
524 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);
525 }
526 if (s->regs[R_GQSPI_DATA_STS] > 1 &&
527 busses == 0x3 && num_stripes == 2) {
528 s->regs[R_GQSPI_DATA_STS] -= 2;
529 } else if (s->regs[R_GQSPI_DATA_STS] > 0) {
530 s->regs[R_GQSPI_DATA_STS]--;
531 }
532 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
533 for (i = 0; i < 2; ++i) {
534 if (busses & (1 << i)) {
535 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]);
536 fifo8_push(&s->rx_fifo_g, tx_rx[i]);
537 s->rx_fifo_g_align++;
538 }
539 }
540 }
541 if (!s->regs[R_GQSPI_DATA_STS]) {
542 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) {
543 fifo8_pop(&s->tx_fifo_g);
544 }
545 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) {
546 fifo8_push(&s->rx_fifo_g, 0);
547 }
548 }
549 }
550}
551
552static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
553{
554 if (!qs) {
555
556 return -1;
557 }
558
559 switch (command) {
560 case READ:
561 case PP:
562 case DPP:
563 case QPP:
564 case READ_4:
565 case PP_4:
566 case QPP_4:
567 return 0;
568 case FAST_READ:
569 case DOR:
570 case QOR:
571 case DOR_4:
572 case QOR_4:
573 return 1;
574 case DIOR:
575 case FAST_READ_4:
576 case DIOR_4:
577 return 2;
578 case QIOR:
579 case QIOR_4:
580 return 4;
581 default:
582 return -1;
583 }
584}
585
586static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd)
587{
588 switch (cmd) {
589 case PP_4:
590 case QPP_4:
591 case READ_4:
592 case QIOR_4:
593 case FAST_READ_4:
594 case DOR_4:
595 case QOR_4:
596 case DIOR_4:
597 return 4;
598 default:
599 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3;
600 }
601}
602
603static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
604{
605 int debug_level = 0;
606 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
607 TYPE_XILINX_QSPIPS);
608
609 for (;;) {
610 int i;
611 uint8_t tx = 0;
612 uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 };
613 uint8_t dummy_cycles = 0;
614 uint8_t addr_length;
615
616 if (fifo8_is_empty(&s->tx_fifo)) {
617 xilinx_spips_update_ixr(s);
618 return;
619 } else if (s->snoop_state == SNOOP_STRIPING ||
620 s->snoop_state == SNOOP_NONE) {
621 for (i = 0; i < num_effective_busses(s); ++i) {
622 tx_rx[i] = fifo8_pop(&s->tx_fifo);
623 }
624 stripe8(tx_rx, num_effective_busses(s), false);
625 } else if (s->snoop_state >= SNOOP_ADDR) {
626 tx = fifo8_pop(&s->tx_fifo);
627 for (i = 0; i < num_effective_busses(s); ++i) {
628 tx_rx[i] = tx;
629 }
630 } else {
631
632
633 tx = fifo8_pop(&s->tx_fifo);
634 dummy_cycles = 8 / s->link_state;
635 }
636
637 for (i = 0; i < num_effective_busses(s); ++i) {
638 int bus = num_effective_busses(s) - 1 - i;
639 if (dummy_cycles) {
640 int d;
641 for (d = 0; d < dummy_cycles; ++d) {
642 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
643 }
644 } else {
645 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
646 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
647 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
648 }
649 }
650
651 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
652 DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
653
654 } else if (s->rx_discard) {
655 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
656 s->rx_discard -= 8 / s->link_state;
657 } else if (fifo8_is_full(&s->rx_fifo)) {
658 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
659 DB_PRINT_L(0, "rx FIFO overflow");
660 } else if (s->snoop_state == SNOOP_STRIPING) {
661 stripe8(tx_rx, num_effective_busses(s), true);
662 for (i = 0; i < num_effective_busses(s); ++i) {
663 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
664 DB_PRINT_L(debug_level, "pushing striped rx byte\n");
665 }
666 } else {
667 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
668 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
669 }
670
671 if (s->link_state_next_when) {
672 s->link_state_next_when--;
673 if (!s->link_state_next_when) {
674 s->link_state = s->link_state_next;
675 }
676 }
677
678 DB_PRINT_L(debug_level, "initial snoop state: %x\n",
679 (unsigned)s->snoop_state);
680 switch (s->snoop_state) {
681 case (SNOOP_CHECKING):
682
683 s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
684 addr_length = get_addr_length(s, tx);
685 if (s->cmd_dummies < 0) {
686 s->snoop_state = SNOOP_NONE;
687 } else {
688 s->snoop_state = SNOOP_ADDR + addr_length - 1;
689 }
690 switch (tx) {
691 case DPP:
692 case DOR:
693 case DOR_4:
694 s->link_state_next = 2;
695 s->link_state_next_when = addr_length + s->cmd_dummies;
696 break;
697 case QPP:
698 case QPP_4:
699 case QOR:
700 case QOR_4:
701 s->link_state_next = 4;
702 s->link_state_next_when = addr_length + s->cmd_dummies;
703 break;
704 case DIOR:
705 case DIOR_4:
706 s->link_state = 2;
707 break;
708 case QIOR:
709 case QIOR_4:
710 s->link_state = 4;
711 break;
712 }
713 break;
714 case (SNOOP_ADDR):
715
716
717 if (s->cmd_dummies < 0) {
718 s->snoop_state = SNOOP_NONE;
719 } else {
720 s->snoop_state = s->cmd_dummies;
721 }
722 break;
723 case (SNOOP_STRIPING):
724 case (SNOOP_NONE):
725
726 if (!debug_level) {
727 DB_PRINT_L(0, "squelching debug info ....\n");
728 debug_level = 1;
729 }
730 break;
731 default:
732 s->snoop_state--;
733 }
734 DB_PRINT_L(debug_level, "final snoop state: %x\n",
735 (unsigned)s->snoop_state);
736 }
737}
738
739static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be)
740{
741 int i;
742 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) {
743 if (be) {
744 fifo8_push(fifo, (uint8_t)(value >> 24));
745 value <<= 8;
746 } else {
747 fifo8_push(fifo, (uint8_t)value);
748 value >>= 8;
749 }
750 }
751}
752
753static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
754{
755 if (!s->regs[R_TRANSFER_SIZE]) {
756 return;
757 }
758 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
759 return;
760 }
761
762
763
764
765 while (s->regs[R_TRANSFER_SIZE] &&
766 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
767
768 tx_data_bytes(&s->tx_fifo, 0, 4, false);
769 s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
770 s->regs[R_TRANSFER_SIZE] -= 4;
771 }
772}
773
774static void xilinx_spips_check_flush(XilinxSPIPS *s)
775{
776 if (s->man_start_com ||
777 (!fifo8_is_empty(&s->tx_fifo) &&
778 !(s->regs[R_CONFIG] & MAN_START_EN))) {
779 xilinx_spips_check_zero_pump(s);
780 xilinx_spips_flush_txfifo(s);
781 }
782 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
783 s->man_start_com = false;
784 }
785 xilinx_spips_update_ixr(s);
786}
787
788static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s)
789{
790 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] ||
791 !fifo32_is_empty(&s->fifo_g);
792
793 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
794 if (s->man_start_com_g || (gqspi_has_work &&
795 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) {
796 xlnx_zynqmp_qspips_flush_fifo_g(s);
797 }
798 } else {
799 xilinx_spips_check_flush(XILINX_SPIPS(s));
800 }
801 if (!gqspi_has_work) {
802 s->man_start_com_g = false;
803 }
804 xlnx_zynqmp_qspips_update_ixr(s);
805}
806
807static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
808{
809 int i;
810
811 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) {
812 value[i] = fifo8_pop(fifo);
813 }
814 return max - i;
815}
816
817static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
818{
819 void *ret;
820
821 if (max == 0 || max > fifo->num) {
822 abort();
823 }
824 *num = MIN(fifo->capacity - fifo->head, max);
825 ret = &fifo->data[fifo->head];
826 fifo->head += *num;
827 fifo->head %= fifo->capacity;
828 fifo->num -= *num;
829 return ret;
830}
831
832static void xlnx_zynqmp_qspips_notify(void *opaque)
833{
834 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque);
835 XilinxSPIPS *s = XILINX_SPIPS(rq);
836 Fifo8 *recv_fifo;
837
838 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
839 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) {
840 return;
841 }
842 recv_fifo = &rq->rx_fifo_g;
843 } else {
844 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) {
845 return;
846 }
847 recv_fifo = &s->rx_fifo;
848 }
849 while (recv_fifo->num >= 4
850 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq))
851 {
852 size_t ret;
853 uint32_t num;
854 const void *rxd;
855 int len;
856
857 len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size :
858 recv_fifo->num;
859 rxd = pop_buf(recv_fifo, len, &num);
860
861 memcpy(rq->dma_buf, rxd, num);
862
863 ret = stream_push(rq->dma, rq->dma_buf, num);
864 assert(ret == num);
865 xlnx_zynqmp_qspips_check_flush(rq);
866 }
867}
868
869static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
870 unsigned size)
871{
872 XilinxSPIPS *s = opaque;
873 uint32_t mask = ~0;
874 uint32_t ret;
875 uint8_t rx_buf[4];
876 int shortfall;
877
878 addr >>= 2;
879 switch (addr) {
880 case R_CONFIG:
881 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
882 break;
883 case R_INTR_STATUS:
884 ret = s->regs[addr] & IXR_ALL;
885 s->regs[addr] = 0;
886 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
887 xilinx_spips_update_ixr(s);
888 return ret;
889 case R_INTR_MASK:
890 mask = IXR_ALL;
891 break;
892 case R_EN:
893 mask = 0x1;
894 break;
895 case R_SLAVE_IDLE_COUNT:
896 mask = 0xFF;
897 break;
898 case R_MOD_ID:
899 mask = 0x01FFFFFF;
900 break;
901 case R_INTR_EN:
902 case R_INTR_DIS:
903 case R_TX_DATA:
904 mask = 0;
905 break;
906 case R_RX_DATA:
907 memset(rx_buf, 0, sizeof(rx_buf));
908 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes);
909 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ?
910 cpu_to_be32(*(uint32_t *)rx_buf) :
911 cpu_to_le32(*(uint32_t *)rx_buf);
912 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
913 ret <<= 8 * shortfall;
914 }
915 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
916 xilinx_spips_check_flush(s);
917 xilinx_spips_update_ixr(s);
918 return ret;
919 }
920 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
921 s->regs[addr] & mask);
922 return s->regs[addr] & mask;
923
924}
925
926static uint64_t xlnx_zynqmp_qspips_read(void *opaque,
927 hwaddr addr, unsigned size)
928{
929 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
930 uint32_t reg = addr / 4;
931 uint32_t ret;
932 uint8_t rx_buf[4];
933 int shortfall;
934
935 if (reg <= R_MOD_ID) {
936 return xilinx_spips_read(opaque, addr, size);
937 } else {
938 switch (reg) {
939 case R_GQSPI_RXD:
940 if (fifo8_is_empty(&s->rx_fifo_g)) {
941 qemu_log_mask(LOG_GUEST_ERROR,
942 "Read from empty GQSPI RX FIFO\n");
943 return 0;
944 }
945 memset(rx_buf, 0, sizeof(rx_buf));
946 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf,
947 XILINX_SPIPS(s)->num_txrx_bytes);
948 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ?
949 cpu_to_be32(*(uint32_t *)rx_buf) :
950 cpu_to_le32(*(uint32_t *)rx_buf);
951 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) {
952 ret <<= 8 * shortfall;
953 }
954 xlnx_zynqmp_qspips_check_flush(s);
955 xlnx_zynqmp_qspips_update_ixr(s);
956 return ret;
957 default:
958 return s->regs[reg];
959 }
960 }
961}
962
963static void xilinx_spips_write(void *opaque, hwaddr addr,
964 uint64_t value, unsigned size)
965{
966 int mask = ~0;
967 XilinxSPIPS *s = opaque;
968
969 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
970 addr >>= 2;
971 switch (addr) {
972 case R_CONFIG:
973 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
974 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
975 s->man_start_com = true;
976 }
977 break;
978 case R_INTR_STATUS:
979 mask = IXR_ALL;
980 s->regs[R_INTR_STATUS] &= ~(mask & value);
981 goto no_reg_update;
982 case R_INTR_DIS:
983 mask = IXR_ALL;
984 s->regs[R_INTR_MASK] &= ~(mask & value);
985 goto no_reg_update;
986 case R_INTR_EN:
987 mask = IXR_ALL;
988 s->regs[R_INTR_MASK] |= mask & value;
989 goto no_reg_update;
990 case R_EN:
991 mask = 0x1;
992 break;
993 case R_SLAVE_IDLE_COUNT:
994 mask = 0xFF;
995 break;
996 case R_RX_DATA:
997 case R_INTR_MASK:
998 case R_MOD_ID:
999 mask = 0;
1000 break;
1001 case R_TX_DATA:
1002 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
1003 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1004 goto no_reg_update;
1005 case R_TXD1:
1006 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,
1007 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1008 goto no_reg_update;
1009 case R_TXD2:
1010 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,
1011 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1012 goto no_reg_update;
1013 case R_TXD3:
1014 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
1015 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1016 goto no_reg_update;
1017 }
1018 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
1019no_reg_update:
1020 xilinx_spips_update_cs_lines(s);
1021 xilinx_spips_check_flush(s);
1022 xilinx_spips_update_cs_lines(s);
1023 xilinx_spips_update_ixr(s);
1024}
1025
1026static const MemoryRegionOps spips_ops = {
1027 .read = xilinx_spips_read,
1028 .write = xilinx_spips_write,
1029 .endianness = DEVICE_LITTLE_ENDIAN,
1030};
1031
1032static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
1033{
1034 XilinxSPIPS *s = &q->parent_obj;
1035
1036 if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) {
1037
1038 memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr,
1039 LQSPI_CACHE_SIZE);
1040 }
1041
1042 q->lqspi_cached_addr = ~0ULL;
1043}
1044
1045static void xilinx_qspips_write(void *opaque, hwaddr addr,
1046 uint64_t value, unsigned size)
1047{
1048 XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1049 XilinxSPIPS *s = XILINX_SPIPS(opaque);
1050
1051 xilinx_spips_write(opaque, addr, value, size);
1052 addr >>= 2;
1053
1054 if (addr == R_LQSPI_CFG) {
1055 xilinx_qspips_invalidate_mmio_ptr(q);
1056 }
1057 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1058 fifo8_reset(&s->rx_fifo);
1059 }
1060}
1061
1062static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr,
1063 uint64_t value, unsigned size)
1064{
1065 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
1066 uint32_t reg = addr / 4;
1067
1068 if (reg <= R_MOD_ID) {
1069 xilinx_qspips_write(opaque, addr, value, size);
1070 } else {
1071 switch (reg) {
1072 case R_GQSPI_CNFG:
1073 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) &&
1074 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) {
1075 s->man_start_com_g = true;
1076 }
1077 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK);
1078 break;
1079 case R_GQSPI_GEN_FIFO:
1080 if (!fifo32_is_full(&s->fifo_g)) {
1081 fifo32_push(&s->fifo_g, value);
1082 }
1083 break;
1084 case R_GQSPI_TXD:
1085 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4,
1086 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN));
1087 break;
1088 case R_GQSPI_FIFO_CTRL:
1089 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) {
1090 fifo32_reset(&s->fifo_g);
1091 }
1092 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) {
1093 fifo8_reset(&s->tx_fifo_g);
1094 }
1095 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) {
1096 fifo8_reset(&s->rx_fifo_g);
1097 }
1098 break;
1099 case R_GQSPI_IDR:
1100 s->regs[R_GQSPI_IMR] |= value;
1101 break;
1102 case R_GQSPI_IER:
1103 s->regs[R_GQSPI_IMR] &= ~value;
1104 break;
1105 case R_GQSPI_ISR:
1106 s->regs[R_GQSPI_ISR] &= ~value;
1107 break;
1108 case R_GQSPI_IMR:
1109 case R_GQSPI_RXD:
1110 case R_GQSPI_GF_SNAPSHOT:
1111 case R_GQSPI_MOD_ID:
1112 break;
1113 default:
1114 s->regs[reg] = value;
1115 break;
1116 }
1117 xlnx_zynqmp_qspips_update_cs_lines(s);
1118 xlnx_zynqmp_qspips_check_flush(s);
1119 xlnx_zynqmp_qspips_update_cs_lines(s);
1120 xlnx_zynqmp_qspips_update_ixr(s);
1121 }
1122 xlnx_zynqmp_qspips_notify(s);
1123}
1124
1125static const MemoryRegionOps qspips_ops = {
1126 .read = xilinx_spips_read,
1127 .write = xilinx_qspips_write,
1128 .endianness = DEVICE_LITTLE_ENDIAN,
1129};
1130
1131static const MemoryRegionOps xlnx_zynqmp_qspips_ops = {
1132 .read = xlnx_zynqmp_qspips_read,
1133 .write = xlnx_zynqmp_qspips_write,
1134 .endianness = DEVICE_LITTLE_ENDIAN,
1135};
1136
1137#define LQSPI_CACHE_SIZE 1024
1138
1139static void lqspi_load_cache(void *opaque, hwaddr addr)
1140{
1141 XilinxQSPIPS *q = opaque;
1142 XilinxSPIPS *s = opaque;
1143 int i;
1144 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
1145 / num_effective_busses(s));
1146 int slave = flash_addr >> LQSPI_ADDRESS_BITS;
1147 int cache_entry = 0;
1148 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
1149
1150 if (addr < q->lqspi_cached_addr ||
1151 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1152 xilinx_qspips_invalidate_mmio_ptr(q);
1153 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1154 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
1155
1156 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
1157
1158 fifo8_reset(&s->tx_fifo);
1159 fifo8_reset(&s->rx_fifo);
1160
1161
1162 DB_PRINT_L(0, "pushing read instruction: %02x\n",
1163 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
1164 LQSPI_CFG_INST_CODE));
1165 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
1166
1167 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
1168 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
1169 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
1170 }
1171 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
1172 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
1173 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
1174
1175 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
1176 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
1177 LQSPI_CFG_MODE_SHIFT,
1178 LQSPI_CFG_MODE_WIDTH));
1179 }
1180
1181 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
1182 LQSPI_CFG_DUMMY_WIDTH)); ++i) {
1183 DB_PRINT_L(0, "pushing dummy byte\n");
1184 fifo8_push(&s->tx_fifo, 0);
1185 }
1186 xilinx_spips_update_cs_lines(s);
1187 xilinx_spips_flush_txfifo(s);
1188 fifo8_reset(&s->rx_fifo);
1189
1190 DB_PRINT_L(0, "starting QSPI data read\n");
1191
1192 while (cache_entry < LQSPI_CACHE_SIZE) {
1193 for (i = 0; i < 64; ++i) {
1194 tx_data_bytes(&s->tx_fifo, 0, 1, false);
1195 }
1196 xilinx_spips_flush_txfifo(s);
1197 for (i = 0; i < 64; ++i) {
1198 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1);
1199 }
1200 }
1201
1202 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1203 s->regs[R_LQSPI_STS] |= u_page_save;
1204 xilinx_spips_update_cs_lines(s);
1205
1206 q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
1207 }
1208}
1209
1210static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size,
1211 unsigned *offset)
1212{
1213 XilinxQSPIPS *q = opaque;
1214 hwaddr offset_within_the_region;
1215
1216 if (!q->mmio_execution_enabled) {
1217 return NULL;
1218 }
1219
1220 offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1);
1221 lqspi_load_cache(opaque, offset_within_the_region);
1222 *size = LQSPI_CACHE_SIZE;
1223 *offset = offset_within_the_region;
1224 return q->lqspi_buf;
1225}
1226
1227static uint64_t
1228lqspi_read(void *opaque, hwaddr addr, unsigned int size)
1229{
1230 XilinxQSPIPS *q = opaque;
1231 uint32_t ret;
1232
1233 if (addr >= q->lqspi_cached_addr &&
1234 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1235 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
1236 ret = cpu_to_le32(*(uint32_t *)retp);
1237 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
1238 (unsigned)ret);
1239 return ret;
1240 } else {
1241 lqspi_load_cache(opaque, addr);
1242 return lqspi_read(opaque, addr, size);
1243 }
1244}
1245
1246static const MemoryRegionOps lqspi_ops = {
1247 .read = lqspi_read,
1248 .request_ptr = lqspi_request_mmio_ptr,
1249 .endianness = DEVICE_NATIVE_ENDIAN,
1250 .valid = {
1251 .min_access_size = 1,
1252 .max_access_size = 4
1253 }
1254};
1255
1256static void xilinx_spips_realize(DeviceState *dev, Error **errp)
1257{
1258 XilinxSPIPS *s = XILINX_SPIPS(dev);
1259 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1260 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1261 qemu_irq *cs;
1262 int i;
1263
1264 DB_PRINT_L(0, "realized spips\n");
1265
1266 if (s->num_busses > MAX_NUM_BUSSES) {
1267 error_setg(errp,
1268 "requested number of SPI busses %u exceeds maximum %d",
1269 s->num_busses, MAX_NUM_BUSSES);
1270 return;
1271 }
1272 if (s->num_busses < MIN_NUM_BUSSES) {
1273 error_setg(errp,
1274 "requested number of SPI busses %u is below minimum %d",
1275 s->num_busses, MIN_NUM_BUSSES);
1276 return;
1277 }
1278
1279 s->spi = g_new(SSIBus *, s->num_busses);
1280 for (i = 0; i < s->num_busses; ++i) {
1281 char bus_name[16];
1282 snprintf(bus_name, 16, "spi%d", i);
1283 s->spi[i] = ssi_create_bus(dev, bus_name);
1284 }
1285
1286 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
1287 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
1288 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
1289 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
1290 }
1291
1292 sysbus_init_irq(sbd, &s->irq);
1293 for (i = 0; i < s->num_cs * s->num_busses; ++i) {
1294 sysbus_init_irq(sbd, &s->cs_lines[i]);
1295 }
1296
1297 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
1298 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4);
1299 sysbus_init_mmio(sbd, &s->iomem);
1300
1301 s->irqline = -1;
1302
1303 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
1304 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
1305}
1306
1307static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
1308{
1309 XilinxSPIPS *s = XILINX_SPIPS(dev);
1310 XilinxQSPIPS *q = XILINX_QSPIPS(dev);
1311 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1312
1313 DB_PRINT_L(0, "realized qspips\n");
1314
1315 s->num_busses = 2;
1316 s->num_cs = 2;
1317 s->num_txrx_bytes = 4;
1318
1319 xilinx_spips_realize(dev, errp);
1320 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
1321 (1 << LQSPI_ADDRESS_BITS) * 2);
1322 sysbus_init_mmio(sbd, &s->mmlqspi);
1323
1324 q->lqspi_cached_addr = ~0ULL;
1325
1326
1327
1328
1329 if (q->mmio_execution_enabled) {
1330 error_setg(&q->migration_blocker,
1331 "enabling mmio_execution breaks migration");
1332 migrate_add_blocker(q->migration_blocker, &error_fatal);
1333 }
1334}
1335
1336static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp)
1337{
1338 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev);
1339 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1340
1341 if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) {
1342 error_setg(errp,
1343 "qspi dma burst size %u exceeds maximum limit %d",
1344 s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE);
1345 return;
1346 }
1347 xilinx_qspips_realize(dev, errp);
1348 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size);
1349 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size);
1350 fifo32_create(&s->fifo_g, 32);
1351}
1352
1353static void xlnx_zynqmp_qspips_init(Object *obj)
1354{
1355 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
1356
1357 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
1358 (Object **)&rq->dma,
1359 object_property_allow_set_link,
1360 OBJ_PROP_LINK_STRONG,
1361 NULL);
1362}
1363
1364static int xilinx_spips_post_load(void *opaque, int version_id)
1365{
1366 xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
1367 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
1368 return 0;
1369}
1370
1371static const VMStateDescription vmstate_xilinx_spips = {
1372 .name = "xilinx_spips",
1373 .version_id = 2,
1374 .minimum_version_id = 2,
1375 .post_load = xilinx_spips_post_load,
1376 .fields = (VMStateField[]) {
1377 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
1378 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
1379 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
1380 VMSTATE_UINT8(snoop_state, XilinxSPIPS),
1381 VMSTATE_END_OF_LIST()
1382 }
1383};
1384
1385static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id)
1386{
1387 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque;
1388 XilinxSPIPS *qs = XILINX_SPIPS(s);
1389
1390 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) &&
1391 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) {
1392 xlnx_zynqmp_qspips_update_ixr(s);
1393 xlnx_zynqmp_qspips_update_cs_lines(s);
1394 }
1395 return 0;
1396}
1397
1398static const VMStateDescription vmstate_xilinx_qspips = {
1399 .name = "xilinx_qspips",
1400 .version_id = 1,
1401 .minimum_version_id = 1,
1402 .fields = (VMStateField[]) {
1403 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0,
1404 vmstate_xilinx_spips, XilinxSPIPS),
1405 VMSTATE_END_OF_LIST()
1406 }
1407};
1408
1409static const VMStateDescription vmstate_xlnx_zynqmp_qspips = {
1410 .name = "xlnx_zynqmp_qspips",
1411 .version_id = 1,
1412 .minimum_version_id = 1,
1413 .post_load = xlnx_zynqmp_qspips_post_load,
1414 .fields = (VMStateField[]) {
1415 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0,
1416 vmstate_xilinx_qspips, XilinxQSPIPS),
1417 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS),
1418 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS),
1419 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS),
1420 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX),
1421 VMSTATE_END_OF_LIST()
1422 }
1423};
1424
1425static Property xilinx_zynqmp_qspips_properties[] = {
1426 DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64),
1427 DEFINE_PROP_END_OF_LIST(),
1428};
1429
1430static Property xilinx_qspips_properties[] = {
1431
1432
1433
1434
1435 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled,
1436 false),
1437 DEFINE_PROP_END_OF_LIST(),
1438};
1439
1440static Property xilinx_spips_properties[] = {
1441 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
1442 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
1443 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
1444 DEFINE_PROP_END_OF_LIST(),
1445};
1446
1447static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
1448{
1449 DeviceClass *dc = DEVICE_CLASS(klass);
1450 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1451
1452 dc->realize = xilinx_qspips_realize;
1453 dc->props = xilinx_qspips_properties;
1454 xsc->reg_ops = &qspips_ops;
1455 xsc->rx_fifo_size = RXFF_A_Q;
1456 xsc->tx_fifo_size = TXFF_A_Q;
1457}
1458
1459static void xilinx_spips_class_init(ObjectClass *klass, void *data)
1460{
1461 DeviceClass *dc = DEVICE_CLASS(klass);
1462 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1463
1464 dc->realize = xilinx_spips_realize;
1465 dc->reset = xilinx_spips_reset;
1466 dc->props = xilinx_spips_properties;
1467 dc->vmsd = &vmstate_xilinx_spips;
1468
1469 xsc->reg_ops = &spips_ops;
1470 xsc->rx_fifo_size = RXFF_A;
1471 xsc->tx_fifo_size = TXFF_A;
1472}
1473
1474static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data)
1475{
1476 DeviceClass *dc = DEVICE_CLASS(klass);
1477 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1478
1479 dc->realize = xlnx_zynqmp_qspips_realize;
1480 dc->reset = xlnx_zynqmp_qspips_reset;
1481 dc->vmsd = &vmstate_xlnx_zynqmp_qspips;
1482 dc->props = xilinx_zynqmp_qspips_properties;
1483 xsc->reg_ops = &xlnx_zynqmp_qspips_ops;
1484 xsc->rx_fifo_size = RXFF_A_Q;
1485 xsc->tx_fifo_size = TXFF_A_Q;
1486}
1487
1488static const TypeInfo xilinx_spips_info = {
1489 .name = TYPE_XILINX_SPIPS,
1490 .parent = TYPE_SYS_BUS_DEVICE,
1491 .instance_size = sizeof(XilinxSPIPS),
1492 .class_init = xilinx_spips_class_init,
1493 .class_size = sizeof(XilinxSPIPSClass),
1494};
1495
1496static const TypeInfo xilinx_qspips_info = {
1497 .name = TYPE_XILINX_QSPIPS,
1498 .parent = TYPE_XILINX_SPIPS,
1499 .instance_size = sizeof(XilinxQSPIPS),
1500 .class_init = xilinx_qspips_class_init,
1501};
1502
1503static const TypeInfo xlnx_zynqmp_qspips_info = {
1504 .name = TYPE_XLNX_ZYNQMP_QSPIPS,
1505 .parent = TYPE_XILINX_QSPIPS,
1506 .instance_size = sizeof(XlnxZynqMPQSPIPS),
1507 .instance_init = xlnx_zynqmp_qspips_init,
1508 .class_init = xlnx_zynqmp_qspips_class_init,
1509};
1510
1511static void xilinx_spips_register_types(void)
1512{
1513 type_register_static(&xilinx_spips_info);
1514 type_register_static(&xilinx_qspips_info);
1515 type_register_static(&xlnx_zynqmp_qspips_info);
1516}
1517
1518type_init(xilinx_spips_register_types)
1519
