1/* 2 * Emulation of Allwinner EMAC Fast Ethernet controller and 3 * Realtek RTL8201CP PHY 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * 7 * Allwinner EMAC register definitions from Linux kernel are: 8 * Copyright 2012 Stefan Roese <sr@denx.de> 9 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 10 * Copyright 1997 Sten Wang 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * version 2 as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 */ 22 23#ifndef ALLWINNER_EMAC_H 24#define ALLWINNER_EMAC_H 25 26#include "qemu/units.h" 27#include "net/net.h" 28#include "qemu/fifo8.h" 29#include "hw/net/mii.h" 30 31#define TYPE_AW_EMAC "allwinner-emac" 32#define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) 33 34/* 35 * Allwinner EMAC register list 36 */ 37#define EMAC_CTL_REG 0x00 38 39#define EMAC_TX_MODE_REG 0x04 40#define EMAC_TX_FLOW_REG 0x08 41#define EMAC_TX_CTL0_REG 0x0C 42#define EMAC_TX_CTL1_REG 0x10 43#define EMAC_TX_INS_REG 0x14 44#define EMAC_TX_PL0_REG 0x18 45#define EMAC_TX_PL1_REG 0x1C 46#define EMAC_TX_STA_REG 0x20 47#define EMAC_TX_IO_DATA_REG 0x24 48#define EMAC_TX_IO_DATA1_REG 0x28 49#define EMAC_TX_TSVL0_REG 0x2C 50#define EMAC_TX_TSVH0_REG 0x30 51#define EMAC_TX_TSVL1_REG 0x34 52#define EMAC_TX_TSVH1_REG 0x38 53 54#define EMAC_RX_CTL_REG 0x3C 55#define EMAC_RX_HASH0_REG 0x40 56#define EMAC_RX_HASH1_REG 0x44 57#define EMAC_RX_STA_REG 0x48 58#define EMAC_RX_IO_DATA_REG 0x4C 59#define EMAC_RX_FBC_REG 0x50 60 61#define EMAC_INT_CTL_REG 0x54 62#define EMAC_INT_STA_REG 0x58 63 64#define EMAC_MAC_CTL0_REG 0x5C 65#define EMAC_MAC_CTL1_REG 0x60 66#define EMAC_MAC_IPGT_REG 0x64 67#define EMAC_MAC_IPGR_REG 0x68 68#define EMAC_MAC_CLRT_REG 0x6C 69#define EMAC_MAC_MAXF_REG 0x70 70#define EMAC_MAC_SUPP_REG 0x74 71#define EMAC_MAC_TEST_REG 0x78 72#define EMAC_MAC_MCFG_REG 0x7C 73#define EMAC_MAC_MCMD_REG 0x80 74#define EMAC_MAC_MADR_REG 0x84 75#define EMAC_MAC_MWTD_REG 0x88 76#define EMAC_MAC_MRDD_REG 0x8C 77#define EMAC_MAC_MIND_REG 0x90 78#define EMAC_MAC_SSRR_REG 0x94 79#define EMAC_MAC_A0_REG 0x98 80#define EMAC_MAC_A1_REG 0x9C 81#define EMAC_MAC_A2_REG 0xA0 82 83#define EMAC_SAFX_L_REG0 0xA4 84#define EMAC_SAFX_H_REG0 0xA8 85#define EMAC_SAFX_L_REG1 0xAC 86#define EMAC_SAFX_H_REG1 0xB0 87#define EMAC_SAFX_L_REG2 0xB4 88#define EMAC_SAFX_H_REG2 0xB8 89#define EMAC_SAFX_L_REG3 0xBC 90#define EMAC_SAFX_H_REG3 0xC0 91 92/* CTL register fields */ 93#define EMAC_CTL_RESET (1 << 0) 94#define EMAC_CTL_TX_EN (1 << 1) 95#define EMAC_CTL_RX_EN (1 << 2) 96 97/* TX MODE register fields */ 98#define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0) 99#define EMAC_TX_MODE_DMA_EN (1 << 1) 100 101/* RX CTL register fields */ 102#define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) 103#define EMAC_RX_CTL_DMA_EN (1 << 2) 104#define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) 105#define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) 106#define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) 107#define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7) 108#define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8) 109#define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16) 110#define EMAC_RX_CTL_DA_FILTER_EN (1 << 17) 111#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20) 112#define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21) 113#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22) 114#define EMAC_RX_CTL_SA_FILTER_EN (1 << 24) 115#define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25) 116 117/* RX IO DATA register fields */ 118#define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16)) 119#define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4) 120#define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5) 121#define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) 122#define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ 123 124/* INT CTL and INT STA registers fields */ 125#define EMAC_INT_TX_CHAN(x) (1 << (x)) 126#define EMAC_INT_RX (1 << 8) 127 128/* Due to lack of specifications, size of fifos is chosen arbitrarily */ 129#define TX_FIFO_SIZE (4 * KiB) 130#define RX_FIFO_SIZE (32 * KiB) 131 132#define NUM_TX_FIFOS 2 133#define RX_HDR_SIZE 8 134#define CRC_SIZE 4 135 136#define PHY_REG_SHIFT 0 137#define PHY_ADDR_SHIFT 8 138 139typedef struct RTL8201CPState { 140 uint16_t bmcr; 141 uint16_t bmsr; 142 uint16_t anar; 143 uint16_t anlpar; 144} RTL8201CPState; 145 146typedef struct AwEmacState { 147 /*< private >*/ 148 SysBusDevice parent_obj; 149 /*< public >*/ 150 151 MemoryRegion iomem; 152 qemu_irq irq; 153 NICState *nic; 154 NICConf conf; 155 RTL8201CPState mii; 156 uint8_t phy_addr; 157 158 uint32_t ctl; 159 uint32_t tx_mode; 160 uint32_t rx_ctl; 161 uint32_t int_ctl; 162 uint32_t int_sta; 163 uint32_t phy_target; 164 165 Fifo8 rx_fifo; 166 uint32_t rx_num_packets; 167 uint32_t rx_packet_size; 168 uint32_t rx_packet_pos; 169 170 Fifo8 tx_fifo[NUM_TX_FIFOS]; 171 uint32_t tx_length[NUM_TX_FIFOS]; 172 uint32_t tx_channel; 173} AwEmacState; 174 175#endif 176