1#ifndef QEMU_HW_ESP_H
2#define QEMU_HW_ESP_H
3
4#include "hw/scsi/scsi.h"
5#include "hw/sysbus.h"
6
7
8#define ESP_MAX_DEVS 7
9typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
10
11#define ESP_REGS 16
12#define TI_BUFSZ 16
13#define ESP_CMDBUF_SZ 32
14
15typedef struct ESPState ESPState;
16
17struct ESPState {
18 uint8_t rregs[ESP_REGS];
19 uint8_t wregs[ESP_REGS];
20 qemu_irq irq;
21 uint8_t chip_id;
22 bool tchi_written;
23 int32_t ti_size;
24 uint32_t ti_rptr, ti_wptr;
25 uint32_t status;
26 uint32_t dma;
27 uint8_t ti_buf[TI_BUFSZ];
28 SCSIBus bus;
29 SCSIDevice *current_dev;
30 SCSIRequest *current_req;
31 uint8_t cmdbuf[ESP_CMDBUF_SZ];
32 uint32_t cmdlen;
33 uint32_t do_cmd;
34
35
36 uint32_t dma_left;
37
38
39 uint32_t dma_counter;
40 int dma_enabled;
41
42 uint32_t async_len;
43 uint8_t *async_buf;
44
45 ESPDMAMemoryReadWriteFunc dma_memory_read;
46 ESPDMAMemoryReadWriteFunc dma_memory_write;
47 void *dma_opaque;
48 void (*dma_cb)(ESPState *s);
49};
50
51#define TYPE_ESP "esp"
52#define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
53
54typedef struct {
55
56 SysBusDevice parent_obj;
57
58
59 MemoryRegion iomem;
60 uint32_t it_shift;
61 ESPState esp;
62} SysBusESPState;
63
64#define ESP_TCLO 0x0
65#define ESP_TCMID 0x1
66#define ESP_FIFO 0x2
67#define ESP_CMD 0x3
68#define ESP_RSTAT 0x4
69#define ESP_WBUSID 0x4
70#define ESP_RINTR 0x5
71#define ESP_WSEL 0x5
72#define ESP_RSEQ 0x6
73#define ESP_WSYNTP 0x6
74#define ESP_RFLAGS 0x7
75#define ESP_WSYNO 0x7
76#define ESP_CFG1 0x8
77#define ESP_RRES1 0x9
78#define ESP_WCCF 0x9
79#define ESP_RRES2 0xa
80#define ESP_WTEST 0xa
81#define ESP_CFG2 0xb
82#define ESP_CFG3 0xc
83#define ESP_RES3 0xd
84#define ESP_TCHI 0xe
85#define ESP_RES4 0xf
86
87#define CMD_DMA 0x80
88#define CMD_CMD 0x7f
89
90#define CMD_NOP 0x00
91#define CMD_FLUSH 0x01
92#define CMD_RESET 0x02
93#define CMD_BUSRESET 0x03
94#define CMD_TI 0x10
95#define CMD_ICCS 0x11
96#define CMD_MSGACC 0x12
97#define CMD_PAD 0x18
98#define CMD_SATN 0x1a
99#define CMD_RSTATN 0x1b
100#define CMD_SEL 0x41
101#define CMD_SELATN 0x42
102#define CMD_SELATNS 0x43
103#define CMD_ENSEL 0x44
104#define CMD_DISSEL 0x45
105
106#define STAT_DO 0x00
107#define STAT_DI 0x01
108#define STAT_CD 0x02
109#define STAT_ST 0x03
110#define STAT_MO 0x06
111#define STAT_MI 0x07
112#define STAT_PIO_MASK 0x06
113
114#define STAT_TC 0x10
115#define STAT_PE 0x20
116#define STAT_GE 0x40
117#define STAT_INT 0x80
118
119#define BUSID_DID 0x07
120
121#define INTR_FC 0x08
122#define INTR_BS 0x10
123#define INTR_DC 0x20
124#define INTR_RST 0x80
125
126#define SEQ_0 0x0
127#define SEQ_CD 0x4
128
129#define CFG1_RESREPT 0x40
130
131#define TCHI_FAS100A 0x4
132#define TCHI_AM53C974 0x12
133
134void esp_dma_enable(ESPState *s, int irq, int level);
135void esp_request_cancelled(SCSIRequest *req);
136void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
137void esp_transfer_data(SCSIRequest *req, uint32_t len);
138void esp_hard_reset(ESPState *s);
139uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
140void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
141extern const VMStateDescription vmstate_esp;
142
143#endif
144