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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "hw/sysbus.h"
23#include "hw/arm/arm.h"
24#include "hw/devices.h"
25#include "hw/loader.h"
26#include "net/net.h"
27#include "sysemu/kvm.h"
28#include "sysemu/sysemu.h"
29#include "hw/boards.h"
30#include "exec/address-spaces.h"
31#include "qemu/error-report.h"
32#include "hw/char/pl011.h"
33#include "hw/ide/ahci.h"
34#include "hw/cpu/a9mpcore.h"
35#include "hw/cpu/a15mpcore.h"
36#include "qemu/log.h"
37
38#define SMP_BOOT_ADDR 0x100
39#define SMP_BOOT_REG 0x40
40#define MPCORE_PERIPHBASE 0xfff10000
41
42#define MVBAR_ADDR 0x200
43#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
44
45#define NIRQ_GIC 160
46
47
48
49static void hb_write_board_setup(ARMCPU *cpu,
50 const struct arm_boot_info *info)
51{
52 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
53}
54
55static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
56{
57 int n;
58 uint32_t smpboot[] = {
59 0xee100fb0,
60 0xe210000f,
61 0xe3a03040,
62 0xe0830200,
63 0xe59f2024,
64 0xe3a01001,
65 0xe5821100,
66 0xe3a010ff,
67 0xe5821104,
68 0xf57ff04f,
69 0xe320f003,
70 0xe5901000,
71 0xe1110001,
72 0x0afffffb,
73 0xe12fff11,
74 MPCORE_PERIPHBASE
75 };
76 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
77 smpboot[n] = tswap32(smpboot[n]);
78 }
79 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
80}
81
82static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
83{
84 CPUARMState *env = &cpu->env;
85
86 switch (info->nb_cpus) {
87 case 4:
88 address_space_stl_notdirty(&address_space_memory,
89 SMP_BOOT_REG + 0x30, 0,
90 MEMTXATTRS_UNSPECIFIED, NULL);
91 case 3:
92 address_space_stl_notdirty(&address_space_memory,
93 SMP_BOOT_REG + 0x20, 0,
94 MEMTXATTRS_UNSPECIFIED, NULL);
95 case 2:
96 address_space_stl_notdirty(&address_space_memory,
97 SMP_BOOT_REG + 0x10, 0,
98 MEMTXATTRS_UNSPECIFIED, NULL);
99 env->regs[15] = SMP_BOOT_ADDR;
100 break;
101 default:
102 break;
103 }
104}
105
106#define NUM_REGS 0x200
107static void hb_regs_write(void *opaque, hwaddr offset,
108 uint64_t value, unsigned size)
109{
110 uint32_t *regs = opaque;
111
112 if (offset == 0xf00) {
113 if (value == 1 || value == 2) {
114 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
115 } else if (value == 3) {
116 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
117 }
118 }
119
120 if (offset / 4 >= NUM_REGS) {
121 qemu_log_mask(LOG_GUEST_ERROR,
122 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
123 return;
124 }
125 regs[offset / 4] = value;
126}
127
128static uint64_t hb_regs_read(void *opaque, hwaddr offset,
129 unsigned size)
130{
131 uint32_t value;
132 uint32_t *regs = opaque;
133
134 if (offset / 4 >= NUM_REGS) {
135 qemu_log_mask(LOG_GUEST_ERROR,
136 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
137 return 0;
138 }
139 value = regs[offset / 4];
140
141 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
142 value |= 0x30000000;
143 }
144
145 return value;
146}
147
148static const MemoryRegionOps hb_mem_ops = {
149 .read = hb_regs_read,
150 .write = hb_regs_write,
151 .endianness = DEVICE_NATIVE_ENDIAN,
152};
153
154#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
155#define HIGHBANK_REGISTERS(obj) \
156 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
157
158typedef struct {
159
160 SysBusDevice parent_obj;
161
162
163 MemoryRegion iomem;
164 uint32_t regs[NUM_REGS];
165} HighbankRegsState;
166
167static VMStateDescription vmstate_highbank_regs = {
168 .name = "highbank-regs",
169 .version_id = 0,
170 .minimum_version_id = 0,
171 .fields = (VMStateField[]) {
172 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
173 VMSTATE_END_OF_LIST(),
174 },
175};
176
177static void highbank_regs_reset(DeviceState *dev)
178{
179 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
180
181 s->regs[0x40] = 0x05F20121;
182 s->regs[0x41] = 0x2;
183 s->regs[0x42] = 0x05F30121;
184 s->regs[0x43] = 0x05F40121;
185}
186
187static void highbank_regs_init(Object *obj)
188{
189 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
190 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
191
192 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
193 "highbank_regs", 0x1000);
194 sysbus_init_mmio(dev, &s->iomem);
195}
196
197static void highbank_regs_class_init(ObjectClass *klass, void *data)
198{
199 DeviceClass *dc = DEVICE_CLASS(klass);
200
201 dc->desc = "Calxeda Highbank registers";
202 dc->vmsd = &vmstate_highbank_regs;
203 dc->reset = highbank_regs_reset;
204}
205
206static const TypeInfo highbank_regs_info = {
207 .name = TYPE_HIGHBANK_REGISTERS,
208 .parent = TYPE_SYS_BUS_DEVICE,
209 .instance_size = sizeof(HighbankRegsState),
210 .instance_init = highbank_regs_init,
211 .class_init = highbank_regs_class_init,
212};
213
214static void highbank_regs_register_types(void)
215{
216 type_register_static(&highbank_regs_info);
217}
218
219type_init(highbank_regs_register_types)
220
221static struct arm_boot_info highbank_binfo;
222
223enum cxmachines {
224 CALXEDA_HIGHBANK,
225 CALXEDA_MIDWAY,
226};
227
228
229
230
231
232
233
234static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
235{
236 ram_addr_t ram_size = machine->ram_size;
237 const char *kernel_filename = machine->kernel_filename;
238 const char *kernel_cmdline = machine->kernel_cmdline;
239 const char *initrd_filename = machine->initrd_filename;
240 DeviceState *dev = NULL;
241 SysBusDevice *busdev;
242 qemu_irq pic[128];
243 int n;
244 qemu_irq cpu_irq[4];
245 qemu_irq cpu_fiq[4];
246 qemu_irq cpu_virq[4];
247 qemu_irq cpu_vfiq[4];
248 MemoryRegion *sysram;
249 MemoryRegion *dram;
250 MemoryRegion *sysmem;
251 char *sysboot_filename;
252
253 switch (machine_id) {
254 case CALXEDA_HIGHBANK:
255 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
256 break;
257 case CALXEDA_MIDWAY:
258 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
259 break;
260 default:
261 assert(0);
262 }
263
264 for (n = 0; n < smp_cpus; n++) {
265 Object *cpuobj;
266 ARMCPU *cpu;
267
268 cpuobj = object_new(machine->cpu_type);
269 cpu = ARM_CPU(cpuobj);
270
271 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
272 "psci-conduit", &error_abort);
273
274 if (n) {
275
276 object_property_set_bool(cpuobj, true,
277 "start-powered-off", &error_abort);
278 }
279
280 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
281 object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
282 "reset-cbar", &error_abort);
283 }
284 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
285 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
286 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
287 cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ);
288 cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ);
289 }
290
291 sysmem = get_system_memory();
292 dram = g_new(MemoryRegion, 1);
293 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
294
295 memory_region_add_subregion(sysmem, 0, dram);
296
297 sysram = g_new(MemoryRegion, 1);
298 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
299 &error_fatal);
300 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
301 if (bios_name != NULL) {
302 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
303 if (sysboot_filename != NULL) {
304 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
305 error_report("Unable to load %s", bios_name);
306 exit(1);
307 }
308 g_free(sysboot_filename);
309 } else {
310 error_report("Unable to find %s", bios_name);
311 exit(1);
312 }
313 }
314
315 switch (machine_id) {
316 case CALXEDA_HIGHBANK:
317 dev = qdev_create(NULL, "l2x0");
318 qdev_init_nofail(dev);
319 busdev = SYS_BUS_DEVICE(dev);
320 sysbus_mmio_map(busdev, 0, 0xfff12000);
321
322 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
323 break;
324 case CALXEDA_MIDWAY:
325 dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
326 break;
327 }
328 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
329 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
330 qdev_init_nofail(dev);
331 busdev = SYS_BUS_DEVICE(dev);
332 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
333 for (n = 0; n < smp_cpus; n++) {
334 sysbus_connect_irq(busdev, n, cpu_irq[n]);
335 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
336 sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]);
337 sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
338 }
339
340 for (n = 0; n < 128; n++) {
341 pic[n] = qdev_get_gpio_in(dev, n);
342 }
343
344 dev = qdev_create(NULL, "sp804");
345 qdev_prop_set_uint32(dev, "freq0", 150000000);
346 qdev_prop_set_uint32(dev, "freq1", 150000000);
347 qdev_init_nofail(dev);
348 busdev = SYS_BUS_DEVICE(dev);
349 sysbus_mmio_map(busdev, 0, 0xfff34000);
350 sysbus_connect_irq(busdev, 0, pic[18]);
351 pl011_create(0xfff36000, pic[20], serial_hd(0));
352
353 dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
354 qdev_init_nofail(dev);
355 busdev = SYS_BUS_DEVICE(dev);
356 sysbus_mmio_map(busdev, 0, 0xfff3c000);
357
358 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
359 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
360 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
361 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
362 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
363 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
364
365 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
366
367 if (nd_table[0].used) {
368 qemu_check_nic_model(&nd_table[0], "xgmac");
369 dev = qdev_create(NULL, "xgmac");
370 qdev_set_nic_properties(dev, &nd_table[0]);
371 qdev_init_nofail(dev);
372 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
373 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
374 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
376
377 qemu_check_nic_model(&nd_table[1], "xgmac");
378 dev = qdev_create(NULL, "xgmac");
379 qdev_set_nic_properties(dev, &nd_table[1]);
380 qdev_init_nofail(dev);
381 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
382 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
385 }
386
387
388
389 highbank_binfo.ram_size = ram_size;
390 highbank_binfo.kernel_filename = kernel_filename;
391 highbank_binfo.kernel_cmdline = kernel_cmdline;
392 highbank_binfo.initrd_filename = initrd_filename;
393
394
395
396
397 highbank_binfo.board_id = -1;
398 highbank_binfo.nb_cpus = smp_cpus;
399 highbank_binfo.loader_start = 0;
400 highbank_binfo.write_secondary_boot = hb_write_secondary;
401 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
402 if (!kvm_enabled()) {
403 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
404 highbank_binfo.write_board_setup = hb_write_board_setup;
405 highbank_binfo.secure_board_setup = true;
406 } else {
407 warn_report("cannot load built-in Monitor support "
408 "if KVM is enabled. Some guests (such as Linux) "
409 "may not boot.");
410 }
411
412 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
413}
414
415static void highbank_init(MachineState *machine)
416{
417 calxeda_init(machine, CALXEDA_HIGHBANK);
418}
419
420static void midway_init(MachineState *machine)
421{
422 calxeda_init(machine, CALXEDA_MIDWAY);
423}
424
425static void highbank_class_init(ObjectClass *oc, void *data)
426{
427 MachineClass *mc = MACHINE_CLASS(oc);
428
429 mc->desc = "Calxeda Highbank (ECX-1000)";
430 mc->init = highbank_init;
431 mc->block_default_type = IF_IDE;
432 mc->units_per_default_bus = 1;
433 mc->max_cpus = 4;
434 mc->ignore_memory_transaction_failures = true;
435}
436
437static const TypeInfo highbank_type = {
438 .name = MACHINE_TYPE_NAME("highbank"),
439 .parent = TYPE_MACHINE,
440 .class_init = highbank_class_init,
441};
442
443static void midway_class_init(ObjectClass *oc, void *data)
444{
445 MachineClass *mc = MACHINE_CLASS(oc);
446
447 mc->desc = "Calxeda Midway (ECX-2000)";
448 mc->init = midway_init;
449 mc->block_default_type = IF_IDE;
450 mc->units_per_default_bus = 1;
451 mc->max_cpus = 4;
452 mc->ignore_memory_transaction_failures = true;
453}
454
455static const TypeInfo midway_type = {
456 .name = MACHINE_TYPE_NAME("midway"),
457 .parent = TYPE_MACHINE,
458 .class_init = midway_class_init,
459};
460
461static void calxeda_machines_init(void)
462{
463 type_register_static(&highbank_type);
464 type_register_static(&midway_type);
465}
466
467type_init(calxeda_machines_init)
468