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28#include "qemu/osdep.h"
29#include "hw/hw.h"
30#include "hw/sparc/sparc32_dma.h"
31#include "hw/sparc/sun4m_iommu.h"
32#include "hw/sysbus.h"
33#include "sysemu/dma.h"
34#include "qapi/error.h"
35#include "trace.h"
36
37
38
39
40
41
42
43
44
45#define DMA_SIZE (4 * sizeof(uint32_t))
46
47
48#define DMA_MASK (DMA_SIZE - 1)
49
50#define DMA_ETH_SIZE (8 * sizeof(uint32_t))
51#define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
52
53#define DMA_VER 0xa0000000
54#define DMA_INTR 1
55#define DMA_INTREN 0x10
56#define DMA_WRITE_MEM 0x100
57#define DMA_EN 0x200
58#define DMA_LOADED 0x04000000
59#define DMA_DRAIN_FIFO 0x40
60#define DMA_RESET 0x80
61
62
63#define DMA_CSR_RO_MASK 0xfe000007
64
65enum {
66 GPIO_RESET = 0,
67 GPIO_DMA,
68};
69
70
71void ledma_memory_read(void *opaque, hwaddr addr,
72 uint8_t *buf, int len, int do_bswap)
73{
74 DMADeviceState *s = opaque;
75 IOMMUState *is = (IOMMUState *)s->iommu;
76 int i;
77
78 addr |= s->dmaregs[3];
79 trace_ledma_memory_read(addr, len);
80 if (do_bswap) {
81 dma_memory_read(&is->iommu_as, addr, buf, len);
82 } else {
83 addr &= ~1;
84 len &= ~1;
85 dma_memory_read(&is->iommu_as, addr, buf, len);
86 for(i = 0; i < len; i += 2) {
87 bswap16s((uint16_t *)(buf + i));
88 }
89 }
90}
91
92void ledma_memory_write(void *opaque, hwaddr addr,
93 uint8_t *buf, int len, int do_bswap)
94{
95 DMADeviceState *s = opaque;
96 IOMMUState *is = (IOMMUState *)s->iommu;
97 int l, i;
98 uint16_t tmp_buf[32];
99
100 addr |= s->dmaregs[3];
101 trace_ledma_memory_write(addr, len);
102 if (do_bswap) {
103 dma_memory_write(&is->iommu_as, addr, buf, len);
104 } else {
105 addr &= ~1;
106 len &= ~1;
107 while (len > 0) {
108 l = len;
109 if (l > sizeof(tmp_buf))
110 l = sizeof(tmp_buf);
111 for(i = 0; i < l; i += 2) {
112 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
113 }
114 dma_memory_write(&is->iommu_as, addr, tmp_buf, l);
115 len -= l;
116 buf += l;
117 addr += l;
118 }
119 }
120}
121
122static void dma_set_irq(void *opaque, int irq, int level)
123{
124 DMADeviceState *s = opaque;
125 if (level) {
126 s->dmaregs[0] |= DMA_INTR;
127 if (s->dmaregs[0] & DMA_INTREN) {
128 trace_sparc32_dma_set_irq_raise();
129 qemu_irq_raise(s->irq);
130 }
131 } else {
132 if (s->dmaregs[0] & DMA_INTR) {
133 s->dmaregs[0] &= ~DMA_INTR;
134 if (s->dmaregs[0] & DMA_INTREN) {
135 trace_sparc32_dma_set_irq_lower();
136 qemu_irq_lower(s->irq);
137 }
138 }
139 }
140}
141
142void espdma_memory_read(void *opaque, uint8_t *buf, int len)
143{
144 DMADeviceState *s = opaque;
145 IOMMUState *is = (IOMMUState *)s->iommu;
146
147 trace_espdma_memory_read(s->dmaregs[1], len);
148 dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len);
149 s->dmaregs[1] += len;
150}
151
152void espdma_memory_write(void *opaque, uint8_t *buf, int len)
153{
154 DMADeviceState *s = opaque;
155 IOMMUState *is = (IOMMUState *)s->iommu;
156
157 trace_espdma_memory_write(s->dmaregs[1], len);
158 dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len);
159 s->dmaregs[1] += len;
160}
161
162static uint64_t dma_mem_read(void *opaque, hwaddr addr,
163 unsigned size)
164{
165 DMADeviceState *s = opaque;
166 uint32_t saddr;
167
168 saddr = (addr & DMA_MASK) >> 2;
169 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
170 return s->dmaregs[saddr];
171}
172
173static void dma_mem_write(void *opaque, hwaddr addr,
174 uint64_t val, unsigned size)
175{
176 DMADeviceState *s = opaque;
177 uint32_t saddr;
178
179 saddr = (addr & DMA_MASK) >> 2;
180 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
181 switch (saddr) {
182 case 0:
183 if (val & DMA_INTREN) {
184 if (s->dmaregs[0] & DMA_INTR) {
185 trace_sparc32_dma_set_irq_raise();
186 qemu_irq_raise(s->irq);
187 }
188 } else {
189 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
190 trace_sparc32_dma_set_irq_lower();
191 qemu_irq_lower(s->irq);
192 }
193 }
194 if (val & DMA_RESET) {
195 qemu_irq_raise(s->gpio[GPIO_RESET]);
196 qemu_irq_lower(s->gpio[GPIO_RESET]);
197 } else if (val & DMA_DRAIN_FIFO) {
198 val &= ~DMA_DRAIN_FIFO;
199 } else if (val == 0)
200 val = DMA_DRAIN_FIFO;
201
202 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
203 trace_sparc32_dma_enable_raise();
204 qemu_irq_raise(s->gpio[GPIO_DMA]);
205 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
206 trace_sparc32_dma_enable_lower();
207 qemu_irq_lower(s->gpio[GPIO_DMA]);
208 }
209
210 val &= ~DMA_CSR_RO_MASK;
211 val |= DMA_VER;
212 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
213 break;
214 case 1:
215 s->dmaregs[0] |= DMA_LOADED;
216
217 default:
218 s->dmaregs[saddr] = val;
219 break;
220 }
221}
222
223static const MemoryRegionOps dma_mem_ops = {
224 .read = dma_mem_read,
225 .write = dma_mem_write,
226 .endianness = DEVICE_NATIVE_ENDIAN,
227 .valid = {
228 .min_access_size = 4,
229 .max_access_size = 4,
230 },
231};
232
233static void sparc32_dma_device_reset(DeviceState *d)
234{
235 DMADeviceState *s = SPARC32_DMA_DEVICE(d);
236
237 memset(s->dmaregs, 0, DMA_SIZE);
238 s->dmaregs[0] = DMA_VER;
239}
240
241static const VMStateDescription vmstate_sparc32_dma_device = {
242 .name ="sparc32_dma",
243 .version_id = 2,
244 .minimum_version_id = 2,
245 .fields = (VMStateField[]) {
246 VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),
247 VMSTATE_END_OF_LIST()
248 }
249};
250
251static void sparc32_dma_device_init(Object *obj)
252{
253 DeviceState *dev = DEVICE(obj);
254 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
255 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
256
257 sysbus_init_irq(sbd, &s->irq);
258
259 sysbus_init_mmio(sbd, &s->iomem);
260
261 object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,
262 (Object **) &s->iommu,
263 qdev_prop_allow_set_link_before_realize,
264 0, NULL);
265
266 qdev_init_gpio_in(dev, dma_set_irq, 1);
267 qdev_init_gpio_out(dev, s->gpio, 2);
268}
269
270static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
271{
272 DeviceClass *dc = DEVICE_CLASS(klass);
273
274 dc->reset = sparc32_dma_device_reset;
275 dc->vmsd = &vmstate_sparc32_dma_device;
276}
277
278static const TypeInfo sparc32_dma_device_info = {
279 .name = TYPE_SPARC32_DMA_DEVICE,
280 .parent = TYPE_SYS_BUS_DEVICE,
281 .abstract = true,
282 .instance_size = sizeof(DMADeviceState),
283 .instance_init = sparc32_dma_device_init,
284 .class_init = sparc32_dma_device_class_init,
285};
286
287static void sparc32_espdma_device_init(Object *obj)
288{
289 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
290
291 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
292 "espdma-mmio", DMA_SIZE);
293}
294
295static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
296{
297 DeviceState *d;
298 SysBusESPState *sysbus;
299 ESPState *esp;
300
301 d = qdev_create(NULL, TYPE_ESP);
302 object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);
303 sysbus = ESP_STATE(d);
304 esp = &sysbus->esp;
305 esp->dma_memory_read = espdma_memory_read;
306 esp->dma_memory_write = espdma_memory_write;
307 esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
308 sysbus->it_shift = 2;
309 esp->dma_enabled = 1;
310 qdev_init_nofail(d);
311}
312
313static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
314{
315 DeviceClass *dc = DEVICE_CLASS(klass);
316
317 dc->realize = sparc32_espdma_device_realize;
318}
319
320static const TypeInfo sparc32_espdma_device_info = {
321 .name = TYPE_SPARC32_ESPDMA_DEVICE,
322 .parent = TYPE_SPARC32_DMA_DEVICE,
323 .instance_size = sizeof(ESPDMADeviceState),
324 .instance_init = sparc32_espdma_device_init,
325 .class_init = sparc32_espdma_device_class_init,
326};
327
328static void sparc32_ledma_device_init(Object *obj)
329{
330 DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
331
332 memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
333 "ledma-mmio", DMA_SIZE);
334}
335
336static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
337{
338 DeviceState *d;
339 NICInfo *nd = &nd_table[0];
340
341 qemu_check_nic_model(nd, TYPE_LANCE);
342
343 d = qdev_create(NULL, TYPE_LANCE);
344 object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
345 qdev_set_nic_properties(d, nd);
346 qdev_prop_set_ptr(d, "dma", dev);
347 qdev_init_nofail(d);
348}
349
350static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
351{
352 DeviceClass *dc = DEVICE_CLASS(klass);
353
354 dc->realize = sparc32_ledma_device_realize;
355}
356
357static const TypeInfo sparc32_ledma_device_info = {
358 .name = TYPE_SPARC32_LEDMA_DEVICE,
359 .parent = TYPE_SPARC32_DMA_DEVICE,
360 .instance_size = sizeof(LEDMADeviceState),
361 .instance_init = sparc32_ledma_device_init,
362 .class_init = sparc32_ledma_device_class_init,
363};
364
365static void sparc32_dma_realize(DeviceState *dev, Error **errp)
366{
367 SPARC32DMAState *s = SPARC32_DMA(dev);
368 DeviceState *espdma, *esp, *ledma, *lance;
369 SysBusDevice *sbd;
370 Object *iommu;
371
372 iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);
373 if (!iommu) {
374 error_setg(errp, "unable to locate sun4m IOMMU device");
375 return;
376 }
377
378 espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);
379 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);
380 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);
381 qdev_init_nofail(espdma);
382
383 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
384 sbd = SYS_BUS_DEVICE(esp);
385 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));
386 qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));
387 qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));
388
389 sbd = SYS_BUS_DEVICE(espdma);
390 memory_region_add_subregion(&s->dmamem, 0x0,
391 sysbus_mmio_get_region(sbd, 0));
392
393 ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);
394 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);
395 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);
396 qdev_init_nofail(ledma);
397
398 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
399 sbd = SYS_BUS_DEVICE(lance);
400 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));
401 qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));
402
403 sbd = SYS_BUS_DEVICE(ledma);
404 memory_region_add_subregion(&s->dmamem, 0x10,
405 sysbus_mmio_get_region(sbd, 0));
406
407
408 memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",
409 sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);
410 memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);
411}
412
413static void sparc32_dma_init(Object *obj)
414{
415 SPARC32DMAState *s = SPARC32_DMA(obj);
416 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
417
418 memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
419 sysbus_init_mmio(sbd, &s->dmamem);
420}
421
422static void sparc32_dma_class_init(ObjectClass *klass, void *data)
423{
424 DeviceClass *dc = DEVICE_CLASS(klass);
425
426 dc->realize = sparc32_dma_realize;
427}
428
429static const TypeInfo sparc32_dma_info = {
430 .name = TYPE_SPARC32_DMA,
431 .parent = TYPE_SYS_BUS_DEVICE,
432 .instance_size = sizeof(SPARC32DMAState),
433 .instance_init = sparc32_dma_init,
434 .class_init = sparc32_dma_class_init,
435};
436
437
438static void sparc32_dma_register_types(void)
439{
440 type_register_static(&sparc32_dma_device_info);
441 type_register_static(&sparc32_espdma_device_info);
442 type_register_static(&sparc32_ledma_device_info);
443 type_register_static(&sparc32_dma_info);
444}
445
446type_init(sparc32_dma_register_types)
447
