qemu/hw/i386/pc_q35.c
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   1/*
   2 * Q35 chipset based pc system emulator
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2009, 2010
   6 *               Isaku Yamahata <yamahata at valinux co jp>
   7 *               VA Linux Systems Japan K.K.
   8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9 *
  10 * This is based on pc.c, but heavily modified.
  11 *
  12 * Permission is hereby granted, free of charge, to any person obtaining a copy
  13 * of this software and associated documentation files (the "Software"), to deal
  14 * in the Software without restriction, including without limitation the rights
  15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16 * copies of the Software, and to permit persons to whom the Software is
  17 * furnished to do so, subject to the following conditions:
  18 *
  19 * The above copyright notice and this permission notice shall be included in
  20 * all copies or substantial portions of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28 * THE SOFTWARE.
  29 */
  30
  31#include "qemu/osdep.h"
  32#include "qemu/units.h"
  33#include "hw/hw.h"
  34#include "hw/loader.h"
  35#include "sysemu/arch_init.h"
  36#include "hw/i2c/smbus.h"
  37#include "hw/boards.h"
  38#include "hw/timer/mc146818rtc.h"
  39#include "hw/xen/xen.h"
  40#include "sysemu/kvm.h"
  41#include "kvm_i386.h"
  42#include "hw/kvm/clock.h"
  43#include "hw/pci-host/q35.h"
  44#include "exec/address-spaces.h"
  45#include "hw/i386/pc.h"
  46#include "hw/i386/ich9.h"
  47#include "hw/i386/amd_iommu.h"
  48#include "hw/i386/intel_iommu.h"
  49#include "hw/display/ramfb.h"
  50#include "hw/smbios/smbios.h"
  51#include "hw/ide/pci.h"
  52#include "hw/ide/ahci.h"
  53#include "hw/usb.h"
  54#include "qapi/error.h"
  55#include "qemu/error-report.h"
  56#include "sysemu/numa.h"
  57
  58/* ICH9 AHCI has 6 ports */
  59#define MAX_SATA_PORTS     6
  60
  61/* PC hardware initialisation */
  62static void pc_q35_init(MachineState *machine)
  63{
  64    PCMachineState *pcms = PC_MACHINE(machine);
  65    PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  66    Q35PCIHost *q35_host;
  67    PCIHostState *phb;
  68    PCIBus *host_bus;
  69    PCIDevice *lpc;
  70    DeviceState *lpc_dev;
  71    BusState *idebus[MAX_SATA_PORTS];
  72    ISADevice *rtc_state;
  73    MemoryRegion *system_io = get_system_io();
  74    MemoryRegion *pci_memory;
  75    MemoryRegion *rom_memory;
  76    MemoryRegion *ram_memory;
  77    GSIState *gsi_state;
  78    ISABus *isa_bus;
  79    qemu_irq *i8259;
  80    int i;
  81    ICH9LPCState *ich9_lpc;
  82    PCIDevice *ahci;
  83    ram_addr_t lowmem;
  84    DriveInfo *hd[MAX_SATA_PORTS];
  85    MachineClass *mc = MACHINE_GET_CLASS(machine);
  86
  87    /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  88     * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  89     * also known as MMCFG).
  90     * If it doesn't, we need to split it in chunks below and above 4G.
  91     * In any case, try to make sure that guest addresses aligned at
  92     * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  93     */
  94    if (machine->ram_size >= 0xb0000000) {
  95        lowmem = 0x80000000;
  96    } else {
  97        lowmem = 0xb0000000;
  98    }
  99
 100    /* Handle the machine opt max-ram-below-4g.  It is basically doing
 101     * min(qemu limit, user limit).
 102     */
 103    if (!pcms->max_ram_below_4g) {
 104        pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
 105    }
 106    if (lowmem > pcms->max_ram_below_4g) {
 107        lowmem = pcms->max_ram_below_4g;
 108        if (machine->ram_size - lowmem > lowmem &&
 109            lowmem & (1 * GiB - 1)) {
 110            warn_report("There is possibly poor performance as the ram size "
 111                        " (0x%" PRIx64 ") is more then twice the size of"
 112                        " max-ram-below-4g (%"PRIu64") and"
 113                        " max-ram-below-4g is not a multiple of 1G.",
 114                        (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 115        }
 116    }
 117
 118    if (machine->ram_size >= lowmem) {
 119        pcms->above_4g_mem_size = machine->ram_size - lowmem;
 120        pcms->below_4g_mem_size = lowmem;
 121    } else {
 122        pcms->above_4g_mem_size = 0;
 123        pcms->below_4g_mem_size = machine->ram_size;
 124    }
 125
 126    if (xen_enabled()) {
 127        xen_hvm_init(pcms, &ram_memory);
 128    }
 129
 130    pc_cpus_init(pcms);
 131
 132    kvmclock_create();
 133
 134    /* pci enabled */
 135    if (pcmc->pci_enabled) {
 136        pci_memory = g_new(MemoryRegion, 1);
 137        memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 138        rom_memory = pci_memory;
 139    } else {
 140        pci_memory = NULL;
 141        rom_memory = get_system_memory();
 142    }
 143
 144    pc_guest_info_init(pcms);
 145
 146    if (pcmc->smbios_defaults) {
 147        /* These values are guest ABI, do not change */
 148        smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 149                            mc->name, pcmc->smbios_legacy_mode,
 150                            pcmc->smbios_uuid_encoded,
 151                            SMBIOS_ENTRY_POINT_21);
 152    }
 153
 154    /* allocate ram and load rom/bios */
 155    if (!xen_enabled()) {
 156        pc_memory_init(pcms, get_system_memory(),
 157                       rom_memory, &ram_memory);
 158    }
 159
 160    /* irq lines */
 161    gsi_state = g_malloc0(sizeof(*gsi_state));
 162    if (kvm_ioapic_in_kernel()) {
 163        kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 164        pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 165                                       GSI_NUM_PINS);
 166    } else {
 167        pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 168    }
 169
 170    /* create pci host bus */
 171    q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 172
 173    object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 174    object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 175                             MCH_HOST_PROP_RAM_MEM, NULL);
 176    object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 177                             MCH_HOST_PROP_PCI_MEM, NULL);
 178    object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 179                             MCH_HOST_PROP_SYSTEM_MEM, NULL);
 180    object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 181                             MCH_HOST_PROP_IO_MEM, NULL);
 182    object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
 183                            PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 184    object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
 185                            PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 186    /* pci */
 187    qdev_init_nofail(DEVICE(q35_host));
 188    phb = PCI_HOST_BRIDGE(q35_host);
 189    host_bus = phb->bus;
 190    /* create ISA bus */
 191    lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 192                                          ICH9_LPC_FUNC), true,
 193                                          TYPE_ICH9_LPC_DEVICE);
 194
 195    object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 196                             TYPE_HOTPLUG_HANDLER,
 197                             (Object **)&pcms->acpi_dev,
 198                             object_property_allow_set_link,
 199                             OBJ_PROP_LINK_STRONG, &error_abort);
 200    object_property_set_link(OBJECT(machine), OBJECT(lpc),
 201                             PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 202
 203    ich9_lpc = ICH9_LPC_DEVICE(lpc);
 204    lpc_dev = DEVICE(lpc);
 205    for (i = 0; i < GSI_NUM_PINS; i++) {
 206        qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
 207    }
 208    pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 209                 ICH9_LPC_NB_PIRQS);
 210    pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 211    isa_bus = ich9_lpc->isa_bus;
 212
 213    if (kvm_pic_in_kernel()) {
 214        i8259 = kvm_i8259_init(isa_bus);
 215    } else if (xen_enabled()) {
 216        i8259 = xen_interrupt_controller_init();
 217    } else {
 218        i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 219    }
 220
 221    for (i = 0; i < ISA_NUM_IRQS; i++) {
 222        gsi_state->i8259_irq[i] = i8259[i];
 223    }
 224    g_free(i8259);
 225
 226    if (pcmc->pci_enabled) {
 227        ioapic_init_gsi(gsi_state, "q35");
 228    }
 229
 230    pc_register_ferr_irq(pcms->gsi[13]);
 231
 232    assert(pcms->vmport != ON_OFF_AUTO__MAX);
 233    if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 234        pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 235    }
 236
 237    /* init basic PC hardware */
 238    pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
 239                         (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit,
 240                         0xff0104);
 241
 242    /* connect pm stuff to lpc */
 243    ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 244
 245    if (pcms->sata) {
 246        /* ahci and SATA device, for q35 1 ahci controller is built-in */
 247        ahci = pci_create_simple_multifunction(host_bus,
 248                                               PCI_DEVFN(ICH9_SATA1_DEV,
 249                                                         ICH9_SATA1_FUNC),
 250                                               true, "ich9-ahci");
 251        idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 252        idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 253        g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 254        ide_drive_get(hd, ahci_get_num_ports(ahci));
 255        ahci_ide_create_devs(ahci, hd);
 256    } else {
 257        idebus[0] = idebus[1] = NULL;
 258    }
 259
 260    if (machine_usb(machine)) {
 261        /* Should we create 6 UHCI according to ich9 spec? */
 262        ehci_create_ich9_with_companions(host_bus, 0x1d);
 263    }
 264
 265    if (pcms->smbus) {
 266        /* TODO: Populate SPD eeprom data.  */
 267        smbus_eeprom_init(ich9_smb_init(host_bus,
 268                                        PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 269                                        0xb100),
 270                          8, NULL, 0);
 271    }
 272
 273    pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 274
 275    /* the rest devices to which pci devfn is automatically assigned */
 276    pc_vga_init(isa_bus, host_bus);
 277    pc_nic_init(pcmc, isa_bus, host_bus);
 278
 279    if (pcms->acpi_nvdimm_state.is_enabled) {
 280        nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 281                               pcms->fw_cfg, OBJECT(pcms));
 282    }
 283}
 284
 285#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 286    static void pc_init_##suffix(MachineState *machine) \
 287    { \
 288        void (*compat)(MachineState *m) = (compatfn); \
 289        if (compat) { \
 290            compat(machine); \
 291        } \
 292        pc_q35_init(machine); \
 293    } \
 294    DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 295
 296
 297static void pc_q35_machine_options(MachineClass *m)
 298{
 299    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 300    pcmc->default_nic_model = "e1000e";
 301
 302    m->family = "pc_q35";
 303    m->desc = "Standard PC (Q35 + ICH9, 2009)";
 304    m->units_per_default_bus = 1;
 305    m->default_machine_opts = "firmware=bios-256k.bin";
 306    m->default_display = "std";
 307    m->no_floppy = 1;
 308    machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 309    machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 310    machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 311    m->max_cpus = 288;
 312}
 313
 314static void pc_q35_3_1_machine_options(MachineClass *m)
 315{
 316    pc_q35_machine_options(m);
 317    m->alias = "q35";
 318}
 319
 320DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 321                   pc_q35_3_1_machine_options);
 322
 323static void pc_q35_3_0_machine_options(MachineClass *m)
 324{
 325    pc_q35_3_1_machine_options(m);
 326    m->alias = NULL;
 327    SET_MACHINE_COMPAT(m, PC_COMPAT_3_0);
 328}
 329
 330DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 331                    pc_q35_3_0_machine_options);
 332
 333static void pc_q35_2_12_machine_options(MachineClass *m)
 334{
 335    pc_q35_3_0_machine_options(m);
 336    SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
 337}
 338
 339DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 340                   pc_q35_2_12_machine_options);
 341
 342static void pc_q35_2_11_machine_options(MachineClass *m)
 343{
 344    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 345
 346    pc_q35_2_12_machine_options(m);
 347    pcmc->default_nic_model = "e1000";
 348    SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);
 349}
 350
 351DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 352                   pc_q35_2_11_machine_options);
 353
 354static void pc_q35_2_10_machine_options(MachineClass *m)
 355{
 356    pc_q35_2_11_machine_options(m);
 357    SET_MACHINE_COMPAT(m, PC_COMPAT_2_10);
 358    m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 359    m->auto_enable_numa_with_memhp = false;
 360}
 361
 362DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 363                   pc_q35_2_10_machine_options);
 364
 365static void pc_q35_2_9_machine_options(MachineClass *m)
 366{
 367    pc_q35_2_10_machine_options(m);
 368    SET_MACHINE_COMPAT(m, PC_COMPAT_2_9);
 369}
 370
 371DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 372                   pc_q35_2_9_machine_options);
 373
 374static void pc_q35_2_8_machine_options(MachineClass *m)
 375{
 376    pc_q35_2_9_machine_options(m);
 377    SET_MACHINE_COMPAT(m, PC_COMPAT_2_8);
 378}
 379
 380DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 381                   pc_q35_2_8_machine_options);
 382
 383static void pc_q35_2_7_machine_options(MachineClass *m)
 384{
 385    pc_q35_2_8_machine_options(m);
 386    m->max_cpus = 255;
 387    SET_MACHINE_COMPAT(m, PC_COMPAT_2_7);
 388}
 389
 390DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 391                   pc_q35_2_7_machine_options);
 392
 393static void pc_q35_2_6_machine_options(MachineClass *m)
 394{
 395    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 396    pc_q35_2_7_machine_options(m);
 397    pcmc->legacy_cpu_hotplug = true;
 398    pcmc->linuxboot_dma_enabled = false;
 399    SET_MACHINE_COMPAT(m, PC_COMPAT_2_6);
 400}
 401
 402DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 403                   pc_q35_2_6_machine_options);
 404
 405static void pc_q35_2_5_machine_options(MachineClass *m)
 406{
 407    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 408    pc_q35_2_6_machine_options(m);
 409    pcmc->save_tsc_khz = false;
 410    m->legacy_fw_cfg_order = 1;
 411    SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 412}
 413
 414DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 415                   pc_q35_2_5_machine_options);
 416
 417static void pc_q35_2_4_machine_options(MachineClass *m)
 418{
 419    PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 420    pc_q35_2_5_machine_options(m);
 421    m->hw_version = "2.4.0";
 422    pcmc->broken_reserved_end = true;
 423    SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 424}
 425
 426DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 427                   pc_q35_2_4_machine_options);
 428