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20#include "qemu/osdep.h"
21#include "hw/sysbus.h"
22#include "hw/boards.h"
23#include "hw/i386/x86-iommu.h"
24#include "hw/i386/pc.h"
25#include "qapi/error.h"
26#include "qemu/error-report.h"
27#include "trace.h"
28#include "sysemu/kvm.h"
29
30void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
31 iec_notify_fn fn, void *data)
32{
33 IEC_Notifier *notifier = g_new0(IEC_Notifier, 1);
34
35 notifier->iec_notify = fn;
36 notifier->private = data;
37
38 QLIST_INSERT_HEAD(&iommu->iec_notifiers, notifier, list);
39}
40
41void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
42 uint32_t index, uint32_t mask)
43{
44 IEC_Notifier *notifier;
45
46 trace_x86_iommu_iec_notify(global, index, mask);
47
48 QLIST_FOREACH(notifier, &iommu->iec_notifiers, list) {
49 if (notifier->iec_notify) {
50 notifier->iec_notify(notifier->private, global,
51 index, mask);
52 }
53 }
54}
55
56
57void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *msg_out)
58{
59 X86IOMMU_MSIMessage msg = {};
60
61
62 msg.dest_mode = irq->dest_mode;
63 msg.redir_hint = irq->redir_hint;
64 msg.dest = irq->dest;
65 msg.__addr_hi = irq->dest & 0xffffff00;
66 msg.__addr_head = cpu_to_le32(0xfee);
67
68 msg.__not_used = irq->msi_addr_last_bits;
69
70
71 msg.vector = irq->vector;
72 msg.delivery_mode = irq->delivery_mode;
73 msg.level = 1;
74 msg.trigger_mode = irq->trigger_mode;
75
76 msg_out->address = msg.msi_addr;
77 msg_out->data = msg.msi_data;
78}
79
80
81static X86IOMMUState *x86_iommu_default = NULL;
82
83static void x86_iommu_set_default(X86IOMMUState *x86_iommu)
84{
85 assert(x86_iommu);
86
87 if (x86_iommu_default) {
88 error_report("QEMU does not support multiple vIOMMUs "
89 "for x86 yet.");
90 exit(1);
91 }
92
93 x86_iommu_default = x86_iommu;
94}
95
96X86IOMMUState *x86_iommu_get_default(void)
97{
98 return x86_iommu_default;
99}
100
101IommuType x86_iommu_get_type(void)
102{
103 return x86_iommu_default->type;
104}
105
106static void x86_iommu_realize(DeviceState *dev, Error **errp)
107{
108 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
109 X86IOMMUClass *x86_class = X86_IOMMU_GET_CLASS(dev);
110 MachineState *ms = MACHINE(qdev_get_machine());
111 MachineClass *mc = MACHINE_GET_CLASS(ms);
112 PCMachineState *pcms =
113 PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE));
114 QLIST_INIT(&x86_iommu->iec_notifiers);
115
116 if (!pcms || !pcms->bus) {
117 error_setg(errp, "Machine-type '%s' not supported by IOMMU",
118 mc->name);
119 return;
120 }
121
122
123 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
124 !kvm_irqchip_is_split()) {
125 error_setg(errp, "Interrupt Remapping cannot work with "
126 "kernel-irqchip=on, please use 'split|off'.");
127 return;
128 }
129
130 if (x86_class->realize) {
131 x86_class->realize(dev, errp);
132 }
133
134 x86_iommu_set_default(X86_IOMMU_DEVICE(dev));
135}
136
137static Property x86_iommu_properties[] = {
138 DEFINE_PROP_BOOL("intremap", X86IOMMUState, intr_supported, false),
139 DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false),
140 DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true),
141 DEFINE_PROP_END_OF_LIST(),
142};
143
144static void x86_iommu_class_init(ObjectClass *klass, void *data)
145{
146 DeviceClass *dc = DEVICE_CLASS(klass);
147 dc->realize = x86_iommu_realize;
148 dc->props = x86_iommu_properties;
149}
150
151static const TypeInfo x86_iommu_info = {
152 .name = TYPE_X86_IOMMU_DEVICE,
153 .parent = TYPE_SYS_BUS_DEVICE,
154 .instance_size = sizeof(X86IOMMUState),
155 .class_init = x86_iommu_class_init,
156 .class_size = sizeof(X86IOMMUClass),
157 .abstract = true,
158};
159
160static void x86_iommu_register_types(void)
161{
162 type_register_static(&x86_iommu_info);
163}
164
165type_init(x86_iommu_register_types)
166