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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "hw/intc/xlnx-pmu-iomod-intc.h"
33
34#ifndef XLNX_PMU_IO_INTC_ERR_DEBUG
35#define XLNX_PMU_IO_INTC_ERR_DEBUG 0
36#endif
37
38#define DB_PRINT_L(lvl, fmt, args...) do {\
39 if (XLNX_PMU_IO_INTC_ERR_DEBUG >= lvl) {\
40 qemu_log(TYPE_XLNX_PMU_IO_INTC ": %s:" fmt, __func__, ## args);\
41 } \
42} while (0)
43
44#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
45
46REG32(IRQ_MODE, 0xc)
47REG32(GPO0, 0x10)
48 FIELD(GPO0, MAGIC_WORD_1, 24, 8)
49 FIELD(GPO0, MAGIC_WORD_2, 16, 8)
50 FIELD(GPO0, FT_INJECT_FAILURE, 13, 3)
51 FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)
52 FIELD(GPO0, RST_FTSM, 11, 1)
53 FIELD(GPO0, CLR_FTSTS, 10, 1)
54 FIELD(GPO0, RST_ON_SLEEP, 9, 1)
55 FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)
56 FIELD(GPO0, PIT3_PRESCALE, 7, 1)
57 FIELD(GPO0, PIT2_PRESCALE, 5, 2)
58 FIELD(GPO0, PIT1_PRESCALE, 3, 2)
59 FIELD(GPO0, PIT0_PRESCALE, 1, 2)
60 FIELD(GPO0, DEBUG_REMAP, 0, 1)
61REG32(GPO1, 0x14)
62 FIELD(GPO1, MIO_5, 5, 1)
63 FIELD(GPO1, MIO_4, 4, 1)
64 FIELD(GPO1, MIO_3, 3, 1)
65 FIELD(GPO1, MIO_2, 2, 1)
66 FIELD(GPO1, MIO_1, 1, 1)
67 FIELD(GPO1, MIO_0, 0, 1)
68REG32(GPO2, 0x18)
69 FIELD(GPO2, DAP_RPU_WAKE_ACK, 9, 1)
70 FIELD(GPO2, DAP_FP_WAKE_ACK, 8, 1)
71 FIELD(GPO2, PS_STATUS, 7, 1)
72 FIELD(GPO2, PCAP_EN, 6, 1)
73REG32(GPO3, 0x1c)
74 FIELD(GPO3, PL_GPO_31, 31, 1)
75 FIELD(GPO3, PL_GPO_30, 30, 1)
76 FIELD(GPO3, PL_GPO_29, 29, 1)
77 FIELD(GPO3, PL_GPO_28, 28, 1)
78 FIELD(GPO3, PL_GPO_27, 27, 1)
79 FIELD(GPO3, PL_GPO_26, 26, 1)
80 FIELD(GPO3, PL_GPO_25, 25, 1)
81 FIELD(GPO3, PL_GPO_24, 24, 1)
82 FIELD(GPO3, PL_GPO_23, 23, 1)
83 FIELD(GPO3, PL_GPO_22, 22, 1)
84 FIELD(GPO3, PL_GPO_21, 21, 1)
85 FIELD(GPO3, PL_GPO_20, 20, 1)
86 FIELD(GPO3, PL_GPO_19, 19, 1)
87 FIELD(GPO3, PL_GPO_18, 18, 1)
88 FIELD(GPO3, PL_GPO_17, 17, 1)
89 FIELD(GPO3, PL_GPO_16, 16, 1)
90 FIELD(GPO3, PL_GPO_15, 15, 1)
91 FIELD(GPO3, PL_GPO_14, 14, 1)
92 FIELD(GPO3, PL_GPO_13, 13, 1)
93 FIELD(GPO3, PL_GPO_12, 12, 1)
94 FIELD(GPO3, PL_GPO_11, 11, 1)
95 FIELD(GPO3, PL_GPO_10, 10, 1)
96 FIELD(GPO3, PL_GPO_9, 9, 1)
97 FIELD(GPO3, PL_GPO_8, 8, 1)
98 FIELD(GPO3, PL_GPO_7, 7, 1)
99 FIELD(GPO3, PL_GPO_6, 6, 1)
100 FIELD(GPO3, PL_GPO_5, 5, 1)
101 FIELD(GPO3, PL_GPO_4, 4, 1)
102 FIELD(GPO3, PL_GPO_3, 3, 1)
103 FIELD(GPO3, PL_GPO_2, 2, 1)
104 FIELD(GPO3, PL_GPO_1, 1, 1)
105 FIELD(GPO3, PL_GPO_0, 0, 1)
106REG32(GPI0, 0x20)
107 FIELD(GPI0, RFT_ECC_FATAL_ERR, 31, 1)
108 FIELD(GPI0, RFT_VOTER_ERR, 30, 1)
109 FIELD(GPI0, RFT_COMPARE_ERR_23, 29, 1)
110 FIELD(GPI0, RFT_COMPARE_ERR_13, 28, 1)
111 FIELD(GPI0, RFT_COMPARE_ERR_12, 27, 1)
112 FIELD(GPI0, RFT_LS_MISMATCH_23_B, 26, 1)
113 FIELD(GPI0, RFT_LS_MISMATCH_13_B, 25, 1)
114 FIELD(GPI0, RFT_LS_MISMATCH_12_B, 24, 1)
115 FIELD(GPI0, RFT_MISMATCH_STATE, 23, 1)
116 FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1)
117 FIELD(GPI0, RFT_SLEEP_RESET, 19, 1)
118 FIELD(GPI0, RFT_LS_MISMATCH_23_A, 18, 1)
119 FIELD(GPI0, RFT_LS_MISMATCH_13_A, 17, 1)
120 FIELD(GPI0, RFT_LS_MISMATCH_12_A, 16, 1)
121 FIELD(GPI0, NFT_ECC_FATAL_ERR, 15, 1)
122 FIELD(GPI0, NFT_VOTER_ERR, 14, 1)
123 FIELD(GPI0, NFT_COMPARE_ERR_23, 13, 1)
124 FIELD(GPI0, NFT_COMPARE_ERR_13, 12, 1)
125 FIELD(GPI0, NFT_COMPARE_ERR_12, 11, 1)
126 FIELD(GPI0, NFT_LS_MISMATCH_23_B, 10, 1)
127 FIELD(GPI0, NFT_LS_MISMATCH_13_B, 9, 1)
128 FIELD(GPI0, NFT_LS_MISMATCH_12_B, 8, 1)
129 FIELD(GPI0, NFT_MISMATCH_STATE, 7, 1)
130 FIELD(GPI0, NFT_MISMATCH_CPU, 6, 1)
131 FIELD(GPI0, NFT_SLEEP_RESET, 3, 1)
132 FIELD(GPI0, NFT_LS_MISMATCH_23_A, 2, 1)
133 FIELD(GPI0, NFT_LS_MISMATCH_13_A, 1, 1)
134 FIELD(GPI0, NFT_LS_MISMATCH_12_A, 0, 1)
135REG32(GPI1, 0x24)
136 FIELD(GPI1, APB_AIB_ERROR, 31, 1)
137 FIELD(GPI1, AXI_AIB_ERROR, 30, 1)
138 FIELD(GPI1, ERROR_2, 29, 1)
139 FIELD(GPI1, ERROR_1, 28, 1)
140 FIELD(GPI1, ACPU_3_DBG_PWRUP, 23, 1)
141 FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1)
142 FIELD(GPI1, ACPU_1_DBG_PWRUP, 21, 1)
143 FIELD(GPI1, ACPU_0_DBG_PWRUP, 20, 1)
144 FIELD(GPI1, FPD_WAKE_GIC_PROXY, 16, 1)
145 FIELD(GPI1, MIO_WAKE_5, 15, 1)
146 FIELD(GPI1, MIO_WAKE_4, 14, 1)
147 FIELD(GPI1, MIO_WAKE_3, 13, 1)
148 FIELD(GPI1, MIO_WAKE_2, 12, 1)
149 FIELD(GPI1, MIO_WAKE_1, 11, 1)
150 FIELD(GPI1, MIO_WAKE_0, 10, 1)
151 FIELD(GPI1, DAP_RPU_WAKE, 9, 1)
152 FIELD(GPI1, DAP_FPD_WAKE, 8, 1)
153 FIELD(GPI1, USB_1_WAKE, 7, 1)
154 FIELD(GPI1, USB_0_WAKE, 6, 1)
155 FIELD(GPI1, R5_1_WAKE, 5, 1)
156 FIELD(GPI1, R5_0_WAKE, 4, 1)
157 FIELD(GPI1, ACPU_3_WAKE, 3, 1)
158 FIELD(GPI1, ACPU_2_WAKE, 2, 1)
159 FIELD(GPI1, ACPU_1_WAKE, 1, 1)
160 FIELD(GPI1, ACPU_0_WAKE, 0, 1)
161REG32(GPI2, 0x28)
162 FIELD(GPI2, VCC_INT_FP_DISCONNECT, 31, 1)
163 FIELD(GPI2, VCC_INT_DISCONNECT, 30, 1)
164 FIELD(GPI2, VCC_AUX_DISCONNECT, 29, 1)
165 FIELD(GPI2, DBG_ACPU3_RST_REQ, 23, 1)
166 FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1)
167 FIELD(GPI2, DBG_ACPU1_RST_REQ, 21, 1)
168 FIELD(GPI2, DBG_ACPU0_RST_REQ, 20, 1)
169 FIELD(GPI2, CP_ACPU3_RST_REQ, 19, 1)
170 FIELD(GPI2, CP_ACPU2_RST_REQ, 18, 1)
171 FIELD(GPI2, CP_ACPU1_RST_REQ, 17, 1)
172 FIELD(GPI2, CP_ACPU0_RST_REQ, 16, 1)
173 FIELD(GPI2, DBG_RCPU1_RST_REQ, 9, 1)
174 FIELD(GPI2, DBG_RCPU0_RST_REQ, 8, 1)
175 FIELD(GPI2, R5_1_SLEEP, 5, 1)
176 FIELD(GPI2, R5_0_SLEEP, 4, 1)
177 FIELD(GPI2, ACPU_3_SLEEP, 3, 1)
178 FIELD(GPI2, ACPU_2_SLEEP, 2, 1)
179 FIELD(GPI2, ACPU_1_SLEEP, 1, 1)
180 FIELD(GPI2, ACPU_0_SLEEP, 0, 1)
181REG32(GPI3, 0x2c)
182 FIELD(GPI3, PL_GPI_31, 31, 1)
183 FIELD(GPI3, PL_GPI_30, 30, 1)
184 FIELD(GPI3, PL_GPI_29, 29, 1)
185 FIELD(GPI3, PL_GPI_28, 28, 1)
186 FIELD(GPI3, PL_GPI_27, 27, 1)
187 FIELD(GPI3, PL_GPI_26, 26, 1)
188 FIELD(GPI3, PL_GPI_25, 25, 1)
189 FIELD(GPI3, PL_GPI_24, 24, 1)
190 FIELD(GPI3, PL_GPI_23, 23, 1)
191 FIELD(GPI3, PL_GPI_22, 22, 1)
192 FIELD(GPI3, PL_GPI_21, 21, 1)
193 FIELD(GPI3, PL_GPI_20, 20, 1)
194 FIELD(GPI3, PL_GPI_19, 19, 1)
195 FIELD(GPI3, PL_GPI_18, 18, 1)
196 FIELD(GPI3, PL_GPI_17, 17, 1)
197 FIELD(GPI3, PL_GPI_16, 16, 1)
198 FIELD(GPI3, PL_GPI_15, 15, 1)
199 FIELD(GPI3, PL_GPI_14, 14, 1)
200 FIELD(GPI3, PL_GPI_13, 13, 1)
201 FIELD(GPI3, PL_GPI_12, 12, 1)
202 FIELD(GPI3, PL_GPI_11, 11, 1)
203 FIELD(GPI3, PL_GPI_10, 10, 1)
204 FIELD(GPI3, PL_GPI_9, 9, 1)
205 FIELD(GPI3, PL_GPI_8, 8, 1)
206 FIELD(GPI3, PL_GPI_7, 7, 1)
207 FIELD(GPI3, PL_GPI_6, 6, 1)
208 FIELD(GPI3, PL_GPI_5, 5, 1)
209 FIELD(GPI3, PL_GPI_4, 4, 1)
210 FIELD(GPI3, PL_GPI_3, 3, 1)
211 FIELD(GPI3, PL_GPI_2, 2, 1)
212 FIELD(GPI3, PL_GPI_1, 1, 1)
213 FIELD(GPI3, PL_GPI_0, 0, 1)
214REG32(IRQ_STATUS, 0x30)
215 FIELD(IRQ_STATUS, CSU_PMU_SEC_LOCK, 31, 1)
216 FIELD(IRQ_STATUS, INV_ADDR, 29, 1)
217 FIELD(IRQ_STATUS, PWR_DN_REQ, 28, 1)
218 FIELD(IRQ_STATUS, PWR_UP_REQ, 27, 1)
219 FIELD(IRQ_STATUS, SW_RST_REQ, 26, 1)
220 FIELD(IRQ_STATUS, HW_RST_REQ, 25, 1)
221 FIELD(IRQ_STATUS, ISO_REQ, 24, 1)
222 FIELD(IRQ_STATUS, FW_REQ, 23, 1)
223 FIELD(IRQ_STATUS, IPI3, 22, 1)
224 FIELD(IRQ_STATUS, IPI2, 21, 1)
225 FIELD(IRQ_STATUS, IPI1, 20, 1)
226 FIELD(IRQ_STATUS, IPI0, 19, 1)
227 FIELD(IRQ_STATUS, RTC_ALARM, 18, 1)
228 FIELD(IRQ_STATUS, RTC_EVERY_SECOND, 17, 1)
229 FIELD(IRQ_STATUS, CORRECTABLE_ECC, 16, 1)
230 FIELD(IRQ_STATUS, GPI3, 14, 1)
231 FIELD(IRQ_STATUS, GPI2, 13, 1)
232 FIELD(IRQ_STATUS, GPI1, 12, 1)
233 FIELD(IRQ_STATUS, GPI0, 11, 1)
234 FIELD(IRQ_STATUS, PIT3, 6, 1)
235 FIELD(IRQ_STATUS, PIT2, 5, 1)
236 FIELD(IRQ_STATUS, PIT1, 4, 1)
237 FIELD(IRQ_STATUS, PIT0, 3, 1)
238REG32(IRQ_PENDING, 0x34)
239 FIELD(IRQ_PENDING, CSU_PMU_SEC_LOCK, 31, 1)
240 FIELD(IRQ_PENDING, INV_ADDR, 29, 1)
241 FIELD(IRQ_PENDING, PWR_DN_REQ, 28, 1)
242 FIELD(IRQ_PENDING, PWR_UP_REQ, 27, 1)
243 FIELD(IRQ_PENDING, SW_RST_REQ, 26, 1)
244 FIELD(IRQ_PENDING, HW_RST_REQ, 25, 1)
245 FIELD(IRQ_PENDING, ISO_REQ, 24, 1)
246 FIELD(IRQ_PENDING, FW_REQ, 23, 1)
247 FIELD(IRQ_PENDING, IPI3, 22, 1)
248 FIELD(IRQ_PENDING, IPI2, 21, 1)
249 FIELD(IRQ_PENDING, IPI1, 20, 1)
250 FIELD(IRQ_PENDING, IPI0, 19, 1)
251 FIELD(IRQ_PENDING, RTC_ALARM, 18, 1)
252 FIELD(IRQ_PENDING, RTC_EVERY_SECOND, 17, 1)
253 FIELD(IRQ_PENDING, CORRECTABLE_ECC, 16, 1)
254 FIELD(IRQ_PENDING, GPI3, 14, 1)
255 FIELD(IRQ_PENDING, GPI2, 13, 1)
256 FIELD(IRQ_PENDING, GPI1, 12, 1)
257 FIELD(IRQ_PENDING, GPI0, 11, 1)
258 FIELD(IRQ_PENDING, PIT3, 6, 1)
259 FIELD(IRQ_PENDING, PIT2, 5, 1)
260 FIELD(IRQ_PENDING, PIT1, 4, 1)
261 FIELD(IRQ_PENDING, PIT0, 3, 1)
262REG32(IRQ_ENABLE, 0x38)
263 FIELD(IRQ_ENABLE, CSU_PMU_SEC_LOCK, 31, 1)
264 FIELD(IRQ_ENABLE, INV_ADDR, 29, 1)
265 FIELD(IRQ_ENABLE, PWR_DN_REQ, 28, 1)
266 FIELD(IRQ_ENABLE, PWR_UP_REQ, 27, 1)
267 FIELD(IRQ_ENABLE, SW_RST_REQ, 26, 1)
268 FIELD(IRQ_ENABLE, HW_RST_REQ, 25, 1)
269 FIELD(IRQ_ENABLE, ISO_REQ, 24, 1)
270 FIELD(IRQ_ENABLE, FW_REQ, 23, 1)
271 FIELD(IRQ_ENABLE, IPI3, 22, 1)
272 FIELD(IRQ_ENABLE, IPI2, 21, 1)
273 FIELD(IRQ_ENABLE, IPI1, 20, 1)
274 FIELD(IRQ_ENABLE, IPI0, 19, 1)
275 FIELD(IRQ_ENABLE, RTC_ALARM, 18, 1)
276 FIELD(IRQ_ENABLE, RTC_EVERY_SECOND, 17, 1)
277 FIELD(IRQ_ENABLE, CORRECTABLE_ECC, 16, 1)
278 FIELD(IRQ_ENABLE, GPI3, 14, 1)
279 FIELD(IRQ_ENABLE, GPI2, 13, 1)
280 FIELD(IRQ_ENABLE, GPI1, 12, 1)
281 FIELD(IRQ_ENABLE, GPI0, 11, 1)
282 FIELD(IRQ_ENABLE, PIT3, 6, 1)
283 FIELD(IRQ_ENABLE, PIT2, 5, 1)
284 FIELD(IRQ_ENABLE, PIT1, 4, 1)
285 FIELD(IRQ_ENABLE, PIT0, 3, 1)
286REG32(IRQ_ACK, 0x3c)
287 FIELD(IRQ_ACK, CSU_PMU_SEC_LOCK, 31, 1)
288 FIELD(IRQ_ACK, INV_ADDR, 29, 1)
289 FIELD(IRQ_ACK, PWR_DN_REQ, 28, 1)
290 FIELD(IRQ_ACK, PWR_UP_REQ, 27, 1)
291 FIELD(IRQ_ACK, SW_RST_REQ, 26, 1)
292 FIELD(IRQ_ACK, HW_RST_REQ, 25, 1)
293 FIELD(IRQ_ACK, ISO_REQ, 24, 1)
294 FIELD(IRQ_ACK, FW_REQ, 23, 1)
295 FIELD(IRQ_ACK, IPI3, 22, 1)
296 FIELD(IRQ_ACK, IPI2, 21, 1)
297 FIELD(IRQ_ACK, IPI1, 20, 1)
298 FIELD(IRQ_ACK, IPI0, 19, 1)
299 FIELD(IRQ_ACK, RTC_ALARM, 18, 1)
300 FIELD(IRQ_ACK, RTC_EVERY_SECOND, 17, 1)
301 FIELD(IRQ_ACK, CORRECTABLE_ECC, 16, 1)
302 FIELD(IRQ_ACK, GPI3, 14, 1)
303 FIELD(IRQ_ACK, GPI2, 13, 1)
304 FIELD(IRQ_ACK, GPI1, 12, 1)
305 FIELD(IRQ_ACK, GPI0, 11, 1)
306 FIELD(IRQ_ACK, PIT3, 6, 1)
307 FIELD(IRQ_ACK, PIT2, 5, 1)
308 FIELD(IRQ_ACK, PIT1, 4, 1)
309 FIELD(IRQ_ACK, PIT0, 3, 1)
310REG32(PIT0_PRELOAD, 0x40)
311REG32(PIT0_COUNTER, 0x44)
312REG32(PIT0_CONTROL, 0x48)
313 FIELD(PIT0_CONTROL, PRELOAD, 1, 1)
314 FIELD(PIT0_CONTROL, EN, 0, 1)
315REG32(PIT1_PRELOAD, 0x50)
316REG32(PIT1_COUNTER, 0x54)
317REG32(PIT1_CONTROL, 0x58)
318 FIELD(PIT1_CONTROL, PRELOAD, 1, 1)
319 FIELD(PIT1_CONTROL, EN, 0, 1)
320REG32(PIT2_PRELOAD, 0x60)
321REG32(PIT2_COUNTER, 0x64)
322REG32(PIT2_CONTROL, 0x68)
323 FIELD(PIT2_CONTROL, PRELOAD, 1, 1)
324 FIELD(PIT2_CONTROL, EN, 0, 1)
325REG32(PIT3_PRELOAD, 0x70)
326REG32(PIT3_COUNTER, 0x74)
327REG32(PIT3_CONTROL, 0x78)
328 FIELD(PIT3_CONTROL, PRELOAD, 1, 1)
329 FIELD(PIT3_CONTROL, EN, 0, 1)
330
331static void xlnx_pmu_io_irq_update(XlnxPMUIOIntc *s)
332{
333 bool irq_out;
334
335 s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE];
336 irq_out = !!s->regs[R_IRQ_PENDING];
337
338 DB_PRINT("Setting IRQ output = %d\n", irq_out);
339
340 qemu_set_irq(s->parent_irq, irq_out);
341}
342
343static void xlnx_pmu_io_irq_enable_postw(RegisterInfo *reg, uint64_t val64)
344{
345 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);
346
347 xlnx_pmu_io_irq_update(s);
348}
349
350static void xlnx_pmu_io_irq_ack_postw(RegisterInfo *reg, uint64_t val64)
351{
352 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);
353 uint32_t val = val64;
354
355
356 val &= s->regs[R_IRQ_STATUS];
357 s->regs[R_IRQ_STATUS] ^= val;
358
359
360 s->regs[R_IRQ_STATUS] |= s->irq_raw & ~s->cfg.level_edge;
361
362 xlnx_pmu_io_irq_update(s);
363}
364
365static const RegisterAccessInfo xlnx_pmu_io_intc_regs_info[] = {
366 { .name = "IRQ_MODE", .addr = A_IRQ_MODE,
367 .rsvd = 0xffffffff,
368 },{ .name = "GPO0", .addr = A_GPO0,
369 },{ .name = "GPO1", .addr = A_GPO1,
370 .rsvd = 0xffffffc0,
371 },{ .name = "GPO2", .addr = A_GPO2,
372 .rsvd = 0xfffffc3f,
373 },{ .name = "GPO3", .addr = A_GPO3,
374 },{ .name = "GPI0", .addr = A_GPI0,
375 .rsvd = 0x300030,
376 .ro = 0xffcfffcf,
377 },{ .name = "GPI1", .addr = A_GPI1,
378 .rsvd = 0xf0e0000,
379 .ro = 0xf0f1ffff,
380 },{ .name = "GPI2", .addr = A_GPI2,
381 .rsvd = 0x1f00fcc0,
382 .ro = 0xe0ff033f,
383 },{ .name = "GPI3", .addr = A_GPI3,
384 .ro = 0xffffffff,
385 },{ .name = "IRQ_STATUS", .addr = A_IRQ_STATUS,
386 .rsvd = 0x40008787,
387 .ro = 0xbfff7878,
388 },{ .name = "IRQ_PENDING", .addr = A_IRQ_PENDING,
389 .rsvd = 0x40008787,
390 .ro = 0xdfff7ff8,
391 },{ .name = "IRQ_ENABLE", .addr = A_IRQ_ENABLE,
392 .rsvd = 0x40008787,
393 .ro = 0x7800,
394 .post_write = xlnx_pmu_io_irq_enable_postw,
395 },{ .name = "IRQ_ACK", .addr = A_IRQ_ACK,
396 .rsvd = 0x40008787,
397 .post_write = xlnx_pmu_io_irq_ack_postw,
398 },{ .name = "PIT0_PRELOAD", .addr = A_PIT0_PRELOAD,
399 .ro = 0xffffffff,
400 },{ .name = "PIT0_COUNTER", .addr = A_PIT0_COUNTER,
401 .ro = 0xffffffff,
402 },{ .name = "PIT0_CONTROL", .addr = A_PIT0_CONTROL,
403 .rsvd = 0xfffffffc,
404 },{ .name = "PIT1_PRELOAD", .addr = A_PIT1_PRELOAD,
405 .ro = 0xffffffff,
406 },{ .name = "PIT1_COUNTER", .addr = A_PIT1_COUNTER,
407 .ro = 0xffffffff,
408 },{ .name = "PIT1_CONTROL", .addr = A_PIT1_CONTROL,
409 .rsvd = 0xfffffffc,
410 },{ .name = "PIT2_PRELOAD", .addr = A_PIT2_PRELOAD,
411 .ro = 0xffffffff,
412 },{ .name = "PIT2_COUNTER", .addr = A_PIT2_COUNTER,
413 .ro = 0xffffffff,
414 },{ .name = "PIT2_CONTROL", .addr = A_PIT2_CONTROL,
415 .rsvd = 0xfffffffc,
416 },{ .name = "PIT3_PRELOAD", .addr = A_PIT3_PRELOAD,
417 .ro = 0xffffffff,
418 },{ .name = "PIT3_COUNTER", .addr = A_PIT3_COUNTER,
419 .ro = 0xffffffff,
420 },{ .name = "PIT3_CONTROL", .addr = A_PIT3_CONTROL,
421 .rsvd = 0xfffffffc,
422 }
423};
424
425static void irq_handler(void *opaque, int irq, int level)
426{
427 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(opaque);
428 uint32_t mask = 1 << irq;
429 uint32_t prev = s->irq_raw;
430 uint32_t temp;
431
432 s->irq_raw &= ~mask;
433 s->irq_raw |= (!!level) << irq;
434
435
436 s->irq_raw ^= (~s->cfg.positive);
437 s->irq_raw &= mask;
438
439 if (s->cfg.level_edge & mask) {
440
441 temp = (prev ^ s->irq_raw) & s->irq_raw;
442 } else {
443
444 temp = s->irq_raw;
445 }
446 s->regs[R_IRQ_STATUS] |= temp;
447
448 xlnx_pmu_io_irq_update(s);
449}
450
451static void xlnx_pmu_io_intc_reset(DeviceState *dev)
452{
453 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);
454 unsigned int i;
455
456 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
457 register_reset(&s->regs_info[i]);
458 }
459
460 xlnx_pmu_io_irq_update(s);
461}
462
463static const MemoryRegionOps xlnx_pmu_io_intc_ops = {
464 .read = register_read_memory,
465 .write = register_write_memory,
466 .endianness = DEVICE_LITTLE_ENDIAN,
467 .valid = {
468 .min_access_size = 4,
469 .max_access_size = 4,
470 },
471};
472
473static Property xlnx_pmu_io_intc_properties[] = {
474 DEFINE_PROP_UINT32("intc-intr-size", XlnxPMUIOIntc, cfg.intr_size, 0),
475 DEFINE_PROP_UINT32("intc-level-edge", XlnxPMUIOIntc, cfg.level_edge, 0),
476 DEFINE_PROP_UINT32("intc-positive", XlnxPMUIOIntc, cfg.positive, 0),
477 DEFINE_PROP_END_OF_LIST(),
478};
479
480static void xlnx_pmu_io_intc_realize(DeviceState *dev, Error **errp)
481{
482 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(dev);
483
484
485 s->cfg.level_edge <<= 16;
486 s->cfg.level_edge |= 0xffff;
487
488
489 s->cfg.positive <<= 16;
490 s->cfg.positive |= 0xffff;
491
492
493 assert(s->cfg.intr_size <= 16);
494
495 qdev_init_gpio_in(dev, irq_handler, 16 + s->cfg.intr_size);
496}
497
498static void xlnx_pmu_io_intc_init(Object *obj)
499{
500 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(obj);
501 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
502 RegisterInfoArray *reg_array;
503
504 memory_region_init(&s->iomem, obj, TYPE_XLNX_PMU_IO_INTC,
505 XLNXPMUIOINTC_R_MAX * 4);
506 reg_array =
507 register_init_block32(DEVICE(obj), xlnx_pmu_io_intc_regs_info,
508 ARRAY_SIZE(xlnx_pmu_io_intc_regs_info),
509 s->regs_info, s->regs,
510 &xlnx_pmu_io_intc_ops,
511 XLNX_PMU_IO_INTC_ERR_DEBUG,
512 XLNXPMUIOINTC_R_MAX * 4);
513 memory_region_add_subregion(&s->iomem,
514 0x0,
515 ®_array->mem);
516 sysbus_init_mmio(sbd, &s->iomem);
517
518 sysbus_init_irq(sbd, &s->parent_irq);
519}
520
521static const VMStateDescription vmstate_xlnx_pmu_io_intc = {
522 .name = TYPE_XLNX_PMU_IO_INTC,
523 .version_id = 1,
524 .minimum_version_id = 1,
525 .fields = (VMStateField[]) {
526 VMSTATE_UINT32_ARRAY(regs, XlnxPMUIOIntc, XLNXPMUIOINTC_R_MAX),
527 VMSTATE_END_OF_LIST(),
528 }
529};
530
531static void xlnx_pmu_io_intc_class_init(ObjectClass *klass, void *data)
532{
533 DeviceClass *dc = DEVICE_CLASS(klass);
534
535 dc->reset = xlnx_pmu_io_intc_reset;
536 dc->realize = xlnx_pmu_io_intc_realize;
537 dc->vmsd = &vmstate_xlnx_pmu_io_intc;
538 dc->props = xlnx_pmu_io_intc_properties;
539}
540
541static const TypeInfo xlnx_pmu_io_intc_info = {
542 .name = TYPE_XLNX_PMU_IO_INTC,
543 .parent = TYPE_SYS_BUS_DEVICE,
544 .instance_size = sizeof(XlnxPMUIOIntc),
545 .class_init = xlnx_pmu_io_intc_class_init,
546 .instance_init = xlnx_pmu_io_intc_init,
547};
548
549static void xlnx_pmu_io_intc_register_types(void)
550{
551 type_register_static(&xlnx_pmu_io_intc_info);
552}
553
554type_init(xlnx_pmu_io_intc_register_types)
555
