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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "hw/intc/xlnx-zynqmp-ipi.h"
34
35#ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG
36#define XLNX_ZYNQMP_IPI_ERR_DEBUG 0
37#endif
38
39#define DB_PRINT_L(lvl, fmt, args...) do {\
40 if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\
41 qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\
42 } \
43} while (0)
44
45#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
46
47REG32(IPI_TRIG, 0x0)
48 FIELD(IPI_TRIG, PL_3, 27, 1)
49 FIELD(IPI_TRIG, PL_2, 26, 1)
50 FIELD(IPI_TRIG, PL_1, 25, 1)
51 FIELD(IPI_TRIG, PL_0, 24, 1)
52 FIELD(IPI_TRIG, PMU_3, 19, 1)
53 FIELD(IPI_TRIG, PMU_2, 18, 1)
54 FIELD(IPI_TRIG, PMU_1, 17, 1)
55 FIELD(IPI_TRIG, PMU_0, 16, 1)
56 FIELD(IPI_TRIG, RPU_1, 9, 1)
57 FIELD(IPI_TRIG, RPU_0, 8, 1)
58 FIELD(IPI_TRIG, APU, 0, 1)
59REG32(IPI_OBS, 0x4)
60 FIELD(IPI_OBS, PL_3, 27, 1)
61 FIELD(IPI_OBS, PL_2, 26, 1)
62 FIELD(IPI_OBS, PL_1, 25, 1)
63 FIELD(IPI_OBS, PL_0, 24, 1)
64 FIELD(IPI_OBS, PMU_3, 19, 1)
65 FIELD(IPI_OBS, PMU_2, 18, 1)
66 FIELD(IPI_OBS, PMU_1, 17, 1)
67 FIELD(IPI_OBS, PMU_0, 16, 1)
68 FIELD(IPI_OBS, RPU_1, 9, 1)
69 FIELD(IPI_OBS, RPU_0, 8, 1)
70 FIELD(IPI_OBS, APU, 0, 1)
71REG32(IPI_ISR, 0x10)
72 FIELD(IPI_ISR, PL_3, 27, 1)
73 FIELD(IPI_ISR, PL_2, 26, 1)
74 FIELD(IPI_ISR, PL_1, 25, 1)
75 FIELD(IPI_ISR, PL_0, 24, 1)
76 FIELD(IPI_ISR, PMU_3, 19, 1)
77 FIELD(IPI_ISR, PMU_2, 18, 1)
78 FIELD(IPI_ISR, PMU_1, 17, 1)
79 FIELD(IPI_ISR, PMU_0, 16, 1)
80 FIELD(IPI_ISR, RPU_1, 9, 1)
81 FIELD(IPI_ISR, RPU_0, 8, 1)
82 FIELD(IPI_ISR, APU, 0, 1)
83REG32(IPI_IMR, 0x14)
84 FIELD(IPI_IMR, PL_3, 27, 1)
85 FIELD(IPI_IMR, PL_2, 26, 1)
86 FIELD(IPI_IMR, PL_1, 25, 1)
87 FIELD(IPI_IMR, PL_0, 24, 1)
88 FIELD(IPI_IMR, PMU_3, 19, 1)
89 FIELD(IPI_IMR, PMU_2, 18, 1)
90 FIELD(IPI_IMR, PMU_1, 17, 1)
91 FIELD(IPI_IMR, PMU_0, 16, 1)
92 FIELD(IPI_IMR, RPU_1, 9, 1)
93 FIELD(IPI_IMR, RPU_0, 8, 1)
94 FIELD(IPI_IMR, APU, 0, 1)
95REG32(IPI_IER, 0x18)
96 FIELD(IPI_IER, PL_3, 27, 1)
97 FIELD(IPI_IER, PL_2, 26, 1)
98 FIELD(IPI_IER, PL_1, 25, 1)
99 FIELD(IPI_IER, PL_0, 24, 1)
100 FIELD(IPI_IER, PMU_3, 19, 1)
101 FIELD(IPI_IER, PMU_2, 18, 1)
102 FIELD(IPI_IER, PMU_1, 17, 1)
103 FIELD(IPI_IER, PMU_0, 16, 1)
104 FIELD(IPI_IER, RPU_1, 9, 1)
105 FIELD(IPI_IER, RPU_0, 8, 1)
106 FIELD(IPI_IER, APU, 0, 1)
107REG32(IPI_IDR, 0x1c)
108 FIELD(IPI_IDR, PL_3, 27, 1)
109 FIELD(IPI_IDR, PL_2, 26, 1)
110 FIELD(IPI_IDR, PL_1, 25, 1)
111 FIELD(IPI_IDR, PL_0, 24, 1)
112 FIELD(IPI_IDR, PMU_3, 19, 1)
113 FIELD(IPI_IDR, PMU_2, 18, 1)
114 FIELD(IPI_IDR, PMU_1, 17, 1)
115 FIELD(IPI_IDR, PMU_0, 16, 1)
116 FIELD(IPI_IDR, RPU_1, 9, 1)
117 FIELD(IPI_IDR, RPU_0, 8, 1)
118 FIELD(IPI_IDR, APU, 0, 1)
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131
132int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};
133static const char *index_array_names[NUM_IPIS] = {"APU", "RPU_0", "RPU_1",
134 "PMU_0", "PMU_1", "PMU_2",
135 "PMU_3", "PL_0", "PL_1",
136 "PL_2", "PL_3"};
137
138static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val)
139{
140 int i, ipi_index, ipi_mask;
141
142 for (i = 0; i < NUM_IPIS; i++) {
143 ipi_index = index_array[i];
144 ipi_mask = (1 << ipi_index);
145 DB_PRINT("Setting %s=%d\n", index_array_names[i],
146 !!(val & ipi_mask));
147 qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask));
148 }
149}
150
151static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val)
152{
153 int i, ipi_index, ipi_mask;
154
155 for (i = 0; i < NUM_IPIS; i++) {
156 ipi_index = index_array[i];
157 ipi_mask = (1 << ipi_index);
158 DB_PRINT("Setting %s=%d\n", index_array_names[i],
159 !!(val & ipi_mask));
160 qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask));
161 }
162}
163
164static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s)
165{
166 bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR];
167
168 DB_PRINT("irq=%d isr=%x mask=%x\n",
169 pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]);
170 qemu_set_irq(s->irq, pending);
171}
172
173static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64)
174{
175 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
176
177 xlnx_zynqmp_ipi_set_trig(s, val64);
178
179 return val64;
180}
181
182static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64)
183{
184 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
185
186
187
188
189 s->regs[R_IPI_TRIG] = 0;
190
191 xlnx_zynqmp_ipi_set_trig(s, 0);
192}
193
194static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64)
195{
196 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
197
198 xlnx_zynqmp_ipi_set_obs(s, val64);
199
200 return val64;
201}
202
203static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64)
204{
205 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
206
207 xlnx_zynqmp_ipi_update_irq(s);
208}
209
210static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64)
211{
212 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
213 uint32_t val = val64;
214
215 s->regs[R_IPI_IMR] &= ~val;
216 xlnx_zynqmp_ipi_update_irq(s);
217 return 0;
218}
219
220static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64)
221{
222 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
223 uint32_t val = val64;
224
225 s->regs[R_IPI_IMR] |= val;
226 xlnx_zynqmp_ipi_update_irq(s);
227 return 0;
228}
229
230static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = {
231 { .name = "IPI_TRIG", .addr = A_IPI_TRIG,
232 .rsvd = 0xf0f0fcfe,
233 .ro = 0xf0f0fcfe,
234 .pre_write = xlnx_zynqmp_ipi_trig_prew,
235 .post_write = xlnx_zynqmp_ipi_trig_postw,
236 },{ .name = "IPI_OBS", .addr = A_IPI_OBS,
237 .rsvd = 0xf0f0fcfe,
238 .ro = 0xffffffff,
239 },{ .name = "IPI_ISR", .addr = A_IPI_ISR,
240 .rsvd = 0xf0f0fcfe,
241 .ro = 0xf0f0fcfe,
242 .w1c = 0xf0f0301,
243 .pre_write = xlnx_zynqmp_ipi_isr_prew,
244 .post_write = xlnx_zynqmp_ipi_isr_postw,
245 },{ .name = "IPI_IMR", .addr = A_IPI_IMR,
246 .reset = 0xf0f0301,
247 .rsvd = 0xf0f0fcfe,
248 .ro = 0xffffffff,
249 },{ .name = "IPI_IER", .addr = A_IPI_IER,
250 .rsvd = 0xf0f0fcfe,
251 .ro = 0xf0f0fcfe,
252 .pre_write = xlnx_zynqmp_ipi_ier_prew,
253 },{ .name = "IPI_IDR", .addr = A_IPI_IDR,
254 .rsvd = 0xf0f0fcfe,
255 .ro = 0xf0f0fcfe,
256 .pre_write = xlnx_zynqmp_ipi_idr_prew,
257 }
258};
259
260static void xlnx_zynqmp_ipi_reset(DeviceState *dev)
261{
262 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev);
263 int i;
264
265 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
266 register_reset(&s->regs_info[i]);
267 }
268
269 xlnx_zynqmp_ipi_update_irq(s);
270}
271
272static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level)
273{
274 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
275 uint32_t val = (!!level) << n;
276
277 DB_PRINT("IPI input irq[%d]=%d\n", n, level);
278
279 s->regs[R_IPI_ISR] |= val;
280 xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]);
281 xlnx_zynqmp_ipi_update_irq(s);
282}
283
284static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level)
285{
286 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
287
288 DB_PRINT("OBS input irq[%d]=%d\n", n, level);
289
290 s->regs[R_IPI_OBS] &= ~(1ULL << n);
291 s->regs[R_IPI_OBS] |= (level << n);
292}
293
294static const MemoryRegionOps xlnx_zynqmp_ipi_ops = {
295 .read = register_read_memory,
296 .write = register_write_memory,
297 .endianness = DEVICE_LITTLE_ENDIAN,
298 .valid = {
299 .min_access_size = 4,
300 .max_access_size = 4,
301 },
302};
303
304static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp)
305{
306 qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32);
307 qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32);
308}
309
310static void xlnx_zynqmp_ipi_init(Object *obj)
311{
312 XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj);
313 DeviceState *dev = DEVICE(obj);
314 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
315 RegisterInfoArray *reg_array;
316 char *irq_name;
317 int i;
318
319 memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI,
320 R_XLNX_ZYNQMP_IPI_MAX * 4);
321 reg_array =
322 register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info,
323 ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info),
324 s->regs_info, s->regs,
325 &xlnx_zynqmp_ipi_ops,
326 XLNX_ZYNQMP_IPI_ERR_DEBUG,
327 R_XLNX_ZYNQMP_IPI_MAX * 4);
328 memory_region_add_subregion(&s->iomem,
329 0x0,
330 ®_array->mem);
331 sysbus_init_mmio(sbd, &s->iomem);
332 sysbus_init_irq(sbd, &s->irq);
333
334 for (i = 0; i < NUM_IPIS; i++) {
335 qdev_init_gpio_out_named(dev, &s->irq_trig_out[i],
336 index_array_names[i], 1);
337
338 irq_name = g_strdup_printf("OBS_%s", index_array_names[i]);
339 qdev_init_gpio_out_named(dev, &s->irq_obs_out[i],
340 irq_name, 1);
341 g_free(irq_name);
342 }
343}
344
345static const VMStateDescription vmstate_zynqmp_pmu_ipi = {
346 .name = TYPE_XLNX_ZYNQMP_IPI,
347 .version_id = 1,
348 .minimum_version_id = 1,
349 .fields = (VMStateField[]) {
350 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX),
351 VMSTATE_END_OF_LIST(),
352 }
353};
354
355static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data)
356{
357 DeviceClass *dc = DEVICE_CLASS(klass);
358
359 dc->reset = xlnx_zynqmp_ipi_reset;
360 dc->realize = xlnx_zynqmp_ipi_realize;
361 dc->vmsd = &vmstate_zynqmp_pmu_ipi;
362}
363
364static const TypeInfo xlnx_zynqmp_ipi_info = {
365 .name = TYPE_XLNX_ZYNQMP_IPI,
366 .parent = TYPE_SYS_BUS_DEVICE,
367 .instance_size = sizeof(XlnxZynqMPIPI),
368 .class_init = xlnx_zynqmp_ipi_class_init,
369 .instance_init = xlnx_zynqmp_ipi_init,
370};
371
372static void xlnx_zynqmp_ipi_register_types(void)
373{
374 type_register_static(&xlnx_zynqmp_ipi_info);
375}
376
377type_init(xlnx_zynqmp_ipi_register_types)
378
