qemu/hw/misc/arm_sysctl.c
<<
>>
Prefs
   1/*
   2 * Status and system control registers for ARM RealView/Versatile boards.
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9
  10#include "qemu/osdep.h"
  11#include "hw/hw.h"
  12#include "qemu/timer.h"
  13#include "qemu/bitops.h"
  14#include "hw/sysbus.h"
  15#include "hw/arm/primecell.h"
  16#include "sysemu/sysemu.h"
  17#include "qemu/log.h"
  18
  19#define LOCK_VALUE 0xa05f
  20
  21#define TYPE_ARM_SYSCTL "realview_sysctl"
  22#define ARM_SYSCTL(obj) \
  23    OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL)
  24
  25typedef struct {
  26    SysBusDevice parent_obj;
  27
  28    MemoryRegion iomem;
  29    qemu_irq pl110_mux_ctrl;
  30
  31    uint32_t sys_id;
  32    uint32_t leds;
  33    uint16_t lockval;
  34    uint32_t cfgdata1;
  35    uint32_t cfgdata2;
  36    uint32_t flags;
  37    uint32_t nvflags;
  38    uint32_t resetlevel;
  39    uint32_t proc_id;
  40    uint32_t sys_mci;
  41    uint32_t sys_cfgdata;
  42    uint32_t sys_cfgctrl;
  43    uint32_t sys_cfgstat;
  44    uint32_t sys_clcd;
  45    uint32_t mb_clock[6];
  46    uint32_t *db_clock;
  47    uint32_t db_num_vsensors;
  48    uint32_t *db_voltage;
  49    uint32_t db_num_clocks;
  50    uint32_t *db_clock_reset;
  51} arm_sysctl_state;
  52
  53static const VMStateDescription vmstate_arm_sysctl = {
  54    .name = "realview_sysctl",
  55    .version_id = 4,
  56    .minimum_version_id = 1,
  57    .fields = (VMStateField[]) {
  58        VMSTATE_UINT32(leds, arm_sysctl_state),
  59        VMSTATE_UINT16(lockval, arm_sysctl_state),
  60        VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  61        VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  62        VMSTATE_UINT32(flags, arm_sysctl_state),
  63        VMSTATE_UINT32(nvflags, arm_sysctl_state),
  64        VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  65        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  66        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  67        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  68        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  69        VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  70        VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
  71        VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
  72                              4, vmstate_info_uint32, uint32_t),
  73        VMSTATE_END_OF_LIST()
  74    }
  75};
  76
  77/* The PB926 actually uses a different format for
  78 * its SYS_ID register. Fortunately the bits which are
  79 * board type on later boards are distinct.
  80 */
  81#define BOARD_ID_PB926 0x100
  82#define BOARD_ID_EB 0x140
  83#define BOARD_ID_PBA8 0x178
  84#define BOARD_ID_PBX 0x182
  85#define BOARD_ID_VEXPRESS 0x190
  86
  87static int board_id(arm_sysctl_state *s)
  88{
  89    /* Extract the board ID field from the SYS_ID register value */
  90    return (s->sys_id >> 16) & 0xfff;
  91}
  92
  93static void arm_sysctl_reset(DeviceState *d)
  94{
  95    arm_sysctl_state *s = ARM_SYSCTL(d);
  96    int i;
  97
  98    s->leds = 0;
  99    s->lockval = 0;
 100    s->cfgdata1 = 0;
 101    s->cfgdata2 = 0;
 102    s->flags = 0;
 103    s->resetlevel = 0;
 104    /* Motherboard oscillators (in Hz) */
 105    s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
 106    s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
 107    s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
 108    s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
 109    s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
 110    s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
 111    /* Daughterboard oscillators: reset from property values */
 112    for (i = 0; i < s->db_num_clocks; i++) {
 113        s->db_clock[i] = s->db_clock_reset[i];
 114    }
 115    if (board_id(s) == BOARD_ID_VEXPRESS) {
 116        /* On VExpress this register will RAZ/WI */
 117        s->sys_clcd = 0;
 118    } else {
 119        /* All others: CLCDID 0x1f, indicating VGA */
 120        s->sys_clcd = 0x1f00;
 121    }
 122}
 123
 124static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
 125                                unsigned size)
 126{
 127    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 128
 129    switch (offset) {
 130    case 0x00: /* ID */
 131        return s->sys_id;
 132    case 0x04: /* SW */
 133        /* General purpose hardware switches.
 134           We don't have a useful way of exposing these to the user.  */
 135        return 0;
 136    case 0x08: /* LED */
 137        return s->leds;
 138    case 0x20: /* LOCK */
 139        return s->lockval;
 140    case 0x0c: /* OSC0 */
 141    case 0x10: /* OSC1 */
 142    case 0x14: /* OSC2 */
 143    case 0x18: /* OSC3 */
 144    case 0x1c: /* OSC4 */
 145    case 0x24: /* 100HZ */
 146        /* ??? Implement these.  */
 147        return 0;
 148    case 0x28: /* CFGDATA1 */
 149        return s->cfgdata1;
 150    case 0x2c: /* CFGDATA2 */
 151        return s->cfgdata2;
 152    case 0x30: /* FLAGS */
 153        return s->flags;
 154    case 0x38: /* NVFLAGS */
 155        return s->nvflags;
 156    case 0x40: /* RESETCTL */
 157        if (board_id(s) == BOARD_ID_VEXPRESS) {
 158            /* reserved: RAZ/WI */
 159            return 0;
 160        }
 161        return s->resetlevel;
 162    case 0x44: /* PCICTL */
 163        return 1;
 164    case 0x48: /* MCI */
 165        return s->sys_mci;
 166    case 0x4c: /* FLASH */
 167        return 0;
 168    case 0x50: /* CLCD */
 169        return s->sys_clcd;
 170    case 0x54: /* CLCDSER */
 171        return 0;
 172    case 0x58: /* BOOTCS */
 173        return 0;
 174    case 0x5c: /* 24MHz */
 175        return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000,
 176                        NANOSECONDS_PER_SECOND);
 177    case 0x60: /* MISC */
 178        return 0;
 179    case 0x84: /* PROCID0 */
 180        return s->proc_id;
 181    case 0x88: /* PROCID1 */
 182        return 0xff000000;
 183    case 0x64: /* DMAPSR0 */
 184    case 0x68: /* DMAPSR1 */
 185    case 0x6c: /* DMAPSR2 */
 186    case 0x70: /* IOSEL */
 187    case 0x74: /* PLDCTL */
 188    case 0x80: /* BUSID */
 189    case 0x8c: /* OSCRESET0 */
 190    case 0x90: /* OSCRESET1 */
 191    case 0x94: /* OSCRESET2 */
 192    case 0x98: /* OSCRESET3 */
 193    case 0x9c: /* OSCRESET4 */
 194    case 0xc0: /* SYS_TEST_OSC0 */
 195    case 0xc4: /* SYS_TEST_OSC1 */
 196    case 0xc8: /* SYS_TEST_OSC2 */
 197    case 0xcc: /* SYS_TEST_OSC3 */
 198    case 0xd0: /* SYS_TEST_OSC4 */
 199        return 0;
 200    case 0xa0: /* SYS_CFGDATA */
 201        if (board_id(s) != BOARD_ID_VEXPRESS) {
 202            goto bad_reg;
 203        }
 204        return s->sys_cfgdata;
 205    case 0xa4: /* SYS_CFGCTRL */
 206        if (board_id(s) != BOARD_ID_VEXPRESS) {
 207            goto bad_reg;
 208        }
 209        return s->sys_cfgctrl;
 210    case 0xa8: /* SYS_CFGSTAT */
 211        if (board_id(s) != BOARD_ID_VEXPRESS) {
 212            goto bad_reg;
 213        }
 214        return s->sys_cfgstat;
 215    default:
 216    bad_reg:
 217        qemu_log_mask(LOG_GUEST_ERROR,
 218                      "arm_sysctl_read: Bad register offset 0x%x\n",
 219                      (int)offset);
 220        return 0;
 221    }
 222}
 223
 224/* SYS_CFGCTRL functions */
 225#define SYS_CFG_OSC 1
 226#define SYS_CFG_VOLT 2
 227#define SYS_CFG_AMP 3
 228#define SYS_CFG_TEMP 4
 229#define SYS_CFG_RESET 5
 230#define SYS_CFG_SCC 6
 231#define SYS_CFG_MUXFPGA 7
 232#define SYS_CFG_SHUTDOWN 8
 233#define SYS_CFG_REBOOT 9
 234#define SYS_CFG_DVIMODE 11
 235#define SYS_CFG_POWER 12
 236#define SYS_CFG_ENERGY 13
 237
 238/* SYS_CFGCTRL site field values */
 239#define SYS_CFG_SITE_MB 0
 240#define SYS_CFG_SITE_DB1 1
 241#define SYS_CFG_SITE_DB2 2
 242
 243/**
 244 * vexpress_cfgctrl_read:
 245 * @s: arm_sysctl_state pointer
 246 * @dcc, @function, @site, @position, @device: split out values from
 247 * SYS_CFGCTRL register
 248 * @val: pointer to where to put the read data on success
 249 *
 250 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and
 251 * write the read value to *val. On failure, return false (and val may
 252 * or may not be written to).
 253 */
 254static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
 255                                  unsigned int function, unsigned int site,
 256                                  unsigned int position, unsigned int device,
 257                                  uint32_t *val)
 258{
 259    /* We don't support anything other than DCC 0, board stack position 0
 260     * or sites other than motherboard/daughterboard:
 261     */
 262    if (dcc != 0 || position != 0 ||
 263        (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 264        goto cfgctrl_unimp;
 265    }
 266
 267    switch (function) {
 268    case SYS_CFG_VOLT:
 269        if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
 270            *val = s->db_voltage[device];
 271            return true;
 272        }
 273        if (site == SYS_CFG_SITE_MB && device == 0) {
 274            /* There is only one motherboard voltage sensor:
 275             * VIO : 3.3V : bus voltage between mother and daughterboard
 276             */
 277            *val = 3300000;
 278            return true;
 279        }
 280        break;
 281    case SYS_CFG_OSC:
 282        if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
 283            /* motherboard clock */
 284            *val = s->mb_clock[device];
 285            return true;
 286        }
 287        if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
 288            /* daughterboard clock */
 289            *val = s->db_clock[device];
 290            return true;
 291        }
 292        break;
 293    default:
 294        break;
 295    }
 296
 297cfgctrl_unimp:
 298    qemu_log_mask(LOG_UNIMP,
 299                  "arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
 300                  "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 301                  function, dcc, site, position, device);
 302    return false;
 303}
 304
 305/**
 306 * vexpress_cfgctrl_write:
 307 * @s: arm_sysctl_state pointer
 308 * @dcc, @function, @site, @position, @device: split out values from
 309 * SYS_CFGCTRL register
 310 * @val: data to write
 311 *
 312 * Handle a VExpress SYS_CFGCTRL register write. On success, return true.
 313 * On failure, return false.
 314 */
 315static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
 316                                   unsigned int function, unsigned int site,
 317                                   unsigned int position, unsigned int device,
 318                                   uint32_t val)
 319{
 320    /* We don't support anything other than DCC 0, board stack position 0
 321     * or sites other than motherboard/daughterboard:
 322     */
 323    if (dcc != 0 || position != 0 ||
 324        (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 325        goto cfgctrl_unimp;
 326    }
 327
 328    switch (function) {
 329    case SYS_CFG_OSC:
 330        if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
 331            /* motherboard clock */
 332            s->mb_clock[device] = val;
 333            return true;
 334        }
 335        if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
 336            /* daughterboard clock */
 337            s->db_clock[device] = val;
 338            return true;
 339        }
 340        break;
 341    case SYS_CFG_MUXFPGA:
 342        if (site == SYS_CFG_SITE_MB && device == 0) {
 343            /* Select whether video output comes from motherboard
 344             * or daughterboard: log and ignore as QEMU doesn't
 345             * support this.
 346             */
 347            qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
 348                          "not supported, ignoring\n");
 349            return true;
 350        }
 351        break;
 352    case SYS_CFG_SHUTDOWN:
 353        if (site == SYS_CFG_SITE_MB && device == 0) {
 354            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 355            return true;
 356        }
 357        break;
 358    case SYS_CFG_REBOOT:
 359        if (site == SYS_CFG_SITE_MB && device == 0) {
 360            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 361            return true;
 362        }
 363        break;
 364    case SYS_CFG_DVIMODE:
 365        if (site == SYS_CFG_SITE_MB && device == 0) {
 366            /* Selecting DVI mode is meaningless for QEMU: we will
 367             * always display the output correctly according to the
 368             * pixel height/width programmed into the CLCD controller.
 369             */
 370            return true;
 371        }
 372    default:
 373        break;
 374    }
 375
 376cfgctrl_unimp:
 377    qemu_log_mask(LOG_UNIMP,
 378                  "arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
 379                  "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 380                  function, dcc, site, position, device);
 381    return false;
 382}
 383
 384static void arm_sysctl_write(void *opaque, hwaddr offset,
 385                             uint64_t val, unsigned size)
 386{
 387    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 388
 389    switch (offset) {
 390    case 0x08: /* LED */
 391        s->leds = val;
 392        break;
 393    case 0x0c: /* OSC0 */
 394    case 0x10: /* OSC1 */
 395    case 0x14: /* OSC2 */
 396    case 0x18: /* OSC3 */
 397    case 0x1c: /* OSC4 */
 398        /* ??? */
 399        break;
 400    case 0x20: /* LOCK */
 401        if (val == LOCK_VALUE)
 402            s->lockval = val;
 403        else
 404            s->lockval = val & 0x7fff;
 405        break;
 406    case 0x28: /* CFGDATA1 */
 407        /* ??? Need to implement this.  */
 408        s->cfgdata1 = val;
 409        break;
 410    case 0x2c: /* CFGDATA2 */
 411        /* ??? Need to implement this.  */
 412        s->cfgdata2 = val;
 413        break;
 414    case 0x30: /* FLAGSSET */
 415        s->flags |= val;
 416        break;
 417    case 0x34: /* FLAGSCLR */
 418        s->flags &= ~val;
 419        break;
 420    case 0x38: /* NVFLAGSSET */
 421        s->nvflags |= val;
 422        break;
 423    case 0x3c: /* NVFLAGSCLR */
 424        s->nvflags &= ~val;
 425        break;
 426    case 0x40: /* RESETCTL */
 427        switch (board_id(s)) {
 428        case BOARD_ID_PB926:
 429            if (s->lockval == LOCK_VALUE) {
 430                s->resetlevel = val;
 431                if (val & 0x100) {
 432                    qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 433                }
 434            }
 435            break;
 436        case BOARD_ID_PBX:
 437        case BOARD_ID_PBA8:
 438            if (s->lockval == LOCK_VALUE) {
 439                s->resetlevel = val;
 440                if (val & 0x04) {
 441                    qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 442                }
 443            }
 444            break;
 445        case BOARD_ID_VEXPRESS:
 446        case BOARD_ID_EB:
 447        default:
 448            /* reserved: RAZ/WI */
 449            break;
 450        }
 451        break;
 452    case 0x44: /* PCICTL */
 453        /* nothing to do.  */
 454        break;
 455    case 0x4c: /* FLASH */
 456        break;
 457    case 0x50: /* CLCD */
 458        switch (board_id(s)) {
 459        case BOARD_ID_PB926:
 460            /* On 926 bits 13:8 are R/O, bits 1:0 control
 461             * the mux that defines how to interpret the PL110
 462             * graphics format, and other bits are r/w but we
 463             * don't implement them to do anything.
 464             */
 465            s->sys_clcd &= 0x3f00;
 466            s->sys_clcd |= val & ~0x3f00;
 467            qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 468            break;
 469        case BOARD_ID_EB:
 470            /* The EB is the same except that there is no mux since
 471             * the EB has a PL111.
 472             */
 473            s->sys_clcd &= 0x3f00;
 474            s->sys_clcd |= val & ~0x3f00;
 475            break;
 476        case BOARD_ID_PBA8:
 477        case BOARD_ID_PBX:
 478            /* On PBA8 and PBX bit 7 is r/w and all other bits
 479             * are either r/o or RAZ/WI.
 480             */
 481            s->sys_clcd &= (1 << 7);
 482            s->sys_clcd |= val & ~(1 << 7);
 483            break;
 484        case BOARD_ID_VEXPRESS:
 485        default:
 486            /* On VExpress this register is unimplemented and will RAZ/WI */
 487            break;
 488        }
 489        break;
 490    case 0x54: /* CLCDSER */
 491    case 0x64: /* DMAPSR0 */
 492    case 0x68: /* DMAPSR1 */
 493    case 0x6c: /* DMAPSR2 */
 494    case 0x70: /* IOSEL */
 495    case 0x74: /* PLDCTL */
 496    case 0x80: /* BUSID */
 497    case 0x84: /* PROCID0 */
 498    case 0x88: /* PROCID1 */
 499    case 0x8c: /* OSCRESET0 */
 500    case 0x90: /* OSCRESET1 */
 501    case 0x94: /* OSCRESET2 */
 502    case 0x98: /* OSCRESET3 */
 503    case 0x9c: /* OSCRESET4 */
 504        break;
 505    case 0xa0: /* SYS_CFGDATA */
 506        if (board_id(s) != BOARD_ID_VEXPRESS) {
 507            goto bad_reg;
 508        }
 509        s->sys_cfgdata = val;
 510        return;
 511    case 0xa4: /* SYS_CFGCTRL */
 512        if (board_id(s) != BOARD_ID_VEXPRESS) {
 513            goto bad_reg;
 514        }
 515        /* Undefined bits [19:18] are RAZ/WI, and writing to
 516         * the start bit just triggers the action; it always reads
 517         * as zero.
 518         */
 519        s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
 520        if (val & (1 << 31)) {
 521            /* Start bit set -- actually do something */
 522            unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
 523            unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
 524            unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
 525            unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
 526            unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
 527            s->sys_cfgstat = 1;            /* complete */
 528            if (s->sys_cfgctrl & (1 << 30)) {
 529                if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
 530                                            device, s->sys_cfgdata)) {
 531                    s->sys_cfgstat |= 2;        /* error */
 532                }
 533            } else {
 534                uint32_t val;
 535                if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
 536                                           device, &val)) {
 537                    s->sys_cfgstat |= 2;        /* error */
 538                } else {
 539                    s->sys_cfgdata = val;
 540                }
 541            }
 542        }
 543        s->sys_cfgctrl &= ~(1 << 31);
 544        return;
 545    case 0xa8: /* SYS_CFGSTAT */
 546        if (board_id(s) != BOARD_ID_VEXPRESS) {
 547            goto bad_reg;
 548        }
 549        s->sys_cfgstat = val & 3;
 550        return;
 551    default:
 552    bad_reg:
 553        qemu_log_mask(LOG_GUEST_ERROR,
 554                      "arm_sysctl_write: Bad register offset 0x%x\n",
 555                      (int)offset);
 556        return;
 557    }
 558}
 559
 560static const MemoryRegionOps arm_sysctl_ops = {
 561    .read = arm_sysctl_read,
 562    .write = arm_sysctl_write,
 563    .endianness = DEVICE_NATIVE_ENDIAN,
 564};
 565
 566static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 567{
 568    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 569    switch (line) {
 570    case ARM_SYSCTL_GPIO_MMC_WPROT:
 571    {
 572        /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 573         * for all later boards it is bit 1.
 574         */
 575        int bit = 2;
 576        if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 577            bit = 4;
 578        }
 579        s->sys_mci &= ~bit;
 580        if (level) {
 581            s->sys_mci |= bit;
 582        }
 583        break;
 584    }
 585    case ARM_SYSCTL_GPIO_MMC_CARDIN:
 586        s->sys_mci &= ~1;
 587        if (level) {
 588            s->sys_mci |= 1;
 589        }
 590        break;
 591    }
 592}
 593
 594static void arm_sysctl_init(Object *obj)
 595{
 596    DeviceState *dev = DEVICE(obj);
 597    SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 598    arm_sysctl_state *s = ARM_SYSCTL(obj);
 599
 600    memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s,
 601                          "arm-sysctl", 0x1000);
 602    sysbus_init_mmio(sd, &s->iomem);
 603    qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
 604    qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
 605}
 606
 607static void arm_sysctl_realize(DeviceState *d, Error **errp)
 608{
 609    arm_sysctl_state *s = ARM_SYSCTL(d);
 610
 611    s->db_clock = g_new0(uint32_t, s->db_num_clocks);
 612}
 613
 614static void arm_sysctl_finalize(Object *obj)
 615{
 616    arm_sysctl_state *s = ARM_SYSCTL(obj);
 617
 618    g_free(s->db_voltage);
 619    g_free(s->db_clock);
 620    g_free(s->db_clock_reset);
 621}
 622
 623static Property arm_sysctl_properties[] = {
 624    DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 625    DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 626    /* Daughterboard power supply voltages (as reported via SYS_CFG) */
 627    DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
 628                      db_voltage, qdev_prop_uint32, uint32_t),
 629    /* Daughterboard clock reset values (as reported via SYS_CFG) */
 630    DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
 631                      db_clock_reset, qdev_prop_uint32, uint32_t),
 632    DEFINE_PROP_END_OF_LIST(),
 633};
 634
 635static void arm_sysctl_class_init(ObjectClass *klass, void *data)
 636{
 637    DeviceClass *dc = DEVICE_CLASS(klass);
 638
 639    dc->realize = arm_sysctl_realize;
 640    dc->reset = arm_sysctl_reset;
 641    dc->vmsd = &vmstate_arm_sysctl;
 642    dc->props = arm_sysctl_properties;
 643}
 644
 645static const TypeInfo arm_sysctl_info = {
 646    .name          = TYPE_ARM_SYSCTL,
 647    .parent        = TYPE_SYS_BUS_DEVICE,
 648    .instance_size = sizeof(arm_sysctl_state),
 649    .instance_init = arm_sysctl_init,
 650    .instance_finalize = arm_sysctl_finalize,
 651    .class_init    = arm_sysctl_class_init,
 652};
 653
 654static void arm_sysctl_register_types(void)
 655{
 656    type_register_static(&arm_sysctl_info);
 657}
 658
 659type_init(arm_sysctl_register_types)
 660