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12#include "qemu/osdep.h"
13#include "hw/misc/aspeed_scu.h"
14#include "hw/qdev-properties.h"
15#include "qapi/error.h"
16#include "qapi/visitor.h"
17#include "qemu/bitops.h"
18#include "qemu/log.h"
19#include "crypto/random.h"
20#include "trace.h"
21
22#define TO_REG(offset) ((offset) >> 2)
23
24#define PROT_KEY TO_REG(0x00)
25#define SYS_RST_CTRL TO_REG(0x04)
26#define CLK_SEL TO_REG(0x08)
27#define CLK_STOP_CTRL TO_REG(0x0C)
28#define FREQ_CNTR_CTRL TO_REG(0x10)
29#define FREQ_CNTR_EVAL TO_REG(0x14)
30#define IRQ_CTRL TO_REG(0x18)
31#define D2PLL_PARAM TO_REG(0x1C)
32#define MPLL_PARAM TO_REG(0x20)
33#define HPLL_PARAM TO_REG(0x24)
34#define FREQ_CNTR_RANGE TO_REG(0x28)
35#define MISC_CTRL1 TO_REG(0x2C)
36#define PCI_CTRL1 TO_REG(0x30)
37#define PCI_CTRL2 TO_REG(0x34)
38#define PCI_CTRL3 TO_REG(0x38)
39#define SYS_RST_STATUS TO_REG(0x3C)
40#define SOC_SCRATCH1 TO_REG(0x40)
41#define SOC_SCRATCH2 TO_REG(0x44)
42#define MAC_CLK_DELAY TO_REG(0x48)
43#define MISC_CTRL2 TO_REG(0x4C)
44#define VGA_SCRATCH1 TO_REG(0x50)
45#define VGA_SCRATCH2 TO_REG(0x54)
46#define VGA_SCRATCH3 TO_REG(0x58)
47#define VGA_SCRATCH4 TO_REG(0x5C)
48#define VGA_SCRATCH5 TO_REG(0x60)
49#define VGA_SCRATCH6 TO_REG(0x64)
50#define VGA_SCRATCH7 TO_REG(0x68)
51#define VGA_SCRATCH8 TO_REG(0x6C)
52#define HW_STRAP1 TO_REG(0x70)
53#define RNG_CTRL TO_REG(0x74)
54#define RNG_DATA TO_REG(0x78)
55#define SILICON_REV TO_REG(0x7C)
56#define PINMUX_CTRL1 TO_REG(0x80)
57#define PINMUX_CTRL2 TO_REG(0x84)
58#define PINMUX_CTRL3 TO_REG(0x88)
59#define PINMUX_CTRL4 TO_REG(0x8C)
60#define PINMUX_CTRL5 TO_REG(0x90)
61#define PINMUX_CTRL6 TO_REG(0x94)
62#define WDT_RST_CTRL TO_REG(0x9C)
63#define PINMUX_CTRL7 TO_REG(0xA0)
64#define PINMUX_CTRL8 TO_REG(0xA4)
65#define PINMUX_CTRL9 TO_REG(0xA8)
66#define WAKEUP_EN TO_REG(0xC0)
67#define WAKEUP_CTRL TO_REG(0xC4)
68#define HW_STRAP2 TO_REG(0xD0)
69#define FREE_CNTR4 TO_REG(0xE0)
70#define FREE_CNTR4_EXT TO_REG(0xE4)
71#define CPU2_CTRL TO_REG(0x100)
72#define CPU2_BASE_SEG1 TO_REG(0x104)
73#define CPU2_BASE_SEG2 TO_REG(0x108)
74#define CPU2_BASE_SEG3 TO_REG(0x10C)
75#define CPU2_BASE_SEG4 TO_REG(0x110)
76#define CPU2_BASE_SEG5 TO_REG(0x114)
77#define CPU2_CACHE_CTRL TO_REG(0x118)
78#define UART_HPLL_CLK TO_REG(0x160)
79#define PCIE_CTRL TO_REG(0x180)
80#define BMC_MMIO_CTRL TO_REG(0x184)
81#define RELOC_DECODE_BASE1 TO_REG(0x188)
82#define RELOC_DECODE_BASE2 TO_REG(0x18C)
83#define MAILBOX_DECODE_BASE TO_REG(0x190)
84#define SRAM_DECODE_BASE1 TO_REG(0x194)
85#define SRAM_DECODE_BASE2 TO_REG(0x198)
86#define BMC_REV TO_REG(0x19C)
87#define BMC_DEV_ID TO_REG(0x1A4)
88
89#define SCU_IO_REGION_SIZE 0x1000
90
91static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
92 [SYS_RST_CTRL] = 0xFFCFFEDCU,
93 [CLK_SEL] = 0xF3F40000U,
94 [CLK_STOP_CTRL] = 0x19FC3E8BU,
95 [D2PLL_PARAM] = 0x00026108U,
96 [MPLL_PARAM] = 0x00030291U,
97 [HPLL_PARAM] = 0x00000291U,
98 [MISC_CTRL1] = 0x00000010U,
99 [PCI_CTRL1] = 0x20001A03U,
100 [PCI_CTRL2] = 0x20001A03U,
101 [PCI_CTRL3] = 0x04000030U,
102 [SYS_RST_STATUS] = 0x00000001U,
103 [SOC_SCRATCH1] = 0x000000C0U,
104 [MISC_CTRL2] = 0x00000023U,
105 [RNG_CTRL] = 0x0000000EU,
106 [PINMUX_CTRL2] = 0x0000F000U,
107 [PINMUX_CTRL3] = 0x01000000U,
108 [PINMUX_CTRL4] = 0x000000FFU,
109 [PINMUX_CTRL5] = 0x0000A000U,
110 [WDT_RST_CTRL] = 0x003FFFF3U,
111 [PINMUX_CTRL8] = 0xFFFF0000U,
112 [PINMUX_CTRL9] = 0x000FFFFFU,
113 [FREE_CNTR4] = 0x000000FFU,
114 [FREE_CNTR4_EXT] = 0x000000FFU,
115 [CPU2_BASE_SEG1] = 0x80000000U,
116 [CPU2_BASE_SEG4] = 0x1E600000U,
117 [CPU2_BASE_SEG5] = 0xC0000000U,
118 [UART_HPLL_CLK] = 0x00001903U,
119 [PCIE_CTRL] = 0x0000007BU,
120 [BMC_DEV_ID] = 0x00002402U
121};
122
123
124
125
126static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
127 [SYS_RST_CTRL] = 0xFFCFFEDCU,
128 [CLK_SEL] = 0xF3F40000U,
129 [CLK_STOP_CTRL] = 0x19FC3E8BU,
130 [D2PLL_PARAM] = 0x00026108U,
131 [MPLL_PARAM] = 0x00030291U,
132 [HPLL_PARAM] = 0x93000400U,
133 [MISC_CTRL1] = 0x00000010U,
134 [PCI_CTRL1] = 0x20001A03U,
135 [PCI_CTRL2] = 0x20001A03U,
136 [PCI_CTRL3] = 0x04000030U,
137 [SYS_RST_STATUS] = 0x00000001U,
138 [SOC_SCRATCH1] = 0x000000C0U,
139 [MISC_CTRL2] = 0x00000023U,
140 [RNG_CTRL] = 0x0000000EU,
141 [PINMUX_CTRL2] = 0x0000F000U,
142 [PINMUX_CTRL3] = 0x03000000U,
143 [PINMUX_CTRL4] = 0x00000000U,
144 [PINMUX_CTRL5] = 0x0000A000U,
145 [WDT_RST_CTRL] = 0x023FFFF3U,
146 [PINMUX_CTRL8] = 0xFFFF0000U,
147 [PINMUX_CTRL9] = 0x000FFFFFU,
148 [FREE_CNTR4] = 0x000000FFU,
149 [FREE_CNTR4_EXT] = 0x000000FFU,
150 [CPU2_BASE_SEG1] = 0x80000000U,
151 [CPU2_BASE_SEG4] = 0x1E600000U,
152 [CPU2_BASE_SEG5] = 0xC0000000U,
153 [UART_HPLL_CLK] = 0x00001903U,
154 [PCIE_CTRL] = 0x0000007BU,
155 [BMC_DEV_ID] = 0x00002402U
156};
157
158static uint32_t aspeed_scu_get_random(void)
159{
160 Error *err = NULL;
161 uint32_t num;
162
163 if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) {
164 error_report_err(err);
165 exit(1);
166 }
167
168 return num;
169}
170
171static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
172{
173 uint32_t apb_divider;
174
175 switch (s->silicon_rev) {
176 case AST2400_A0_SILICON_REV:
177 case AST2400_A1_SILICON_REV:
178 apb_divider = 2;
179 break;
180 case AST2500_A0_SILICON_REV:
181 case AST2500_A1_SILICON_REV:
182 apb_divider = 4;
183 break;
184 default:
185 g_assert_not_reached();
186 }
187
188 s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
189 / apb_divider;
190}
191
192static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
193{
194 AspeedSCUState *s = ASPEED_SCU(opaque);
195 int reg = TO_REG(offset);
196
197 if (reg >= ARRAY_SIZE(s->regs)) {
198 qemu_log_mask(LOG_GUEST_ERROR,
199 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
200 __func__, offset);
201 return 0;
202 }
203
204 switch (reg) {
205 case RNG_DATA:
206
207
208
209 s->regs[RNG_DATA] = aspeed_scu_get_random();
210 break;
211 case WAKEUP_EN:
212 qemu_log_mask(LOG_GUEST_ERROR,
213 "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
214 __func__, offset);
215 break;
216 }
217
218 return s->regs[reg];
219}
220
221static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
222 unsigned size)
223{
224 AspeedSCUState *s = ASPEED_SCU(opaque);
225 int reg = TO_REG(offset);
226
227 if (reg >= ARRAY_SIZE(s->regs)) {
228 qemu_log_mask(LOG_GUEST_ERROR,
229 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
230 __func__, offset);
231 return;
232 }
233
234 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
235 !s->regs[PROT_KEY]) {
236 qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
237 return;
238 }
239
240 trace_aspeed_scu_write(offset, size, data);
241
242 switch (reg) {
243 case PROT_KEY:
244 s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
245 return;
246 case CLK_SEL:
247 s->regs[reg] = data;
248 aspeed_scu_set_apb_freq(s);
249 break;
250 case HW_STRAP1:
251 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
252 s->regs[HW_STRAP1] |= data;
253 return;
254 }
255
256 break;
257 case SILICON_REV:
258 if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
259 s->regs[HW_STRAP1] &= ~data;
260 } else {
261 qemu_log_mask(LOG_GUEST_ERROR,
262 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
263 __func__, offset);
264 }
265
266 return;
267 case FREQ_CNTR_EVAL:
268 case VGA_SCRATCH1 ... VGA_SCRATCH8:
269 case RNG_DATA:
270 case FREE_CNTR4:
271 case FREE_CNTR4_EXT:
272 qemu_log_mask(LOG_GUEST_ERROR,
273 "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
274 __func__, offset);
275 return;
276 }
277
278 s->regs[reg] = data;
279}
280
281static const MemoryRegionOps aspeed_scu_ops = {
282 .read = aspeed_scu_read,
283 .write = aspeed_scu_write,
284 .endianness = DEVICE_LITTLE_ENDIAN,
285 .valid.min_access_size = 4,
286 .valid.max_access_size = 4,
287 .valid.unaligned = false,
288};
289
290static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
291{
292 if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
293 return 25000000;
294 } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
295 return 48000000;
296 } else {
297 return 24000000;
298 }
299}
300
301
302
303
304
305static const uint32_t hpll_ast2400_freqs[][4] = {
306 { 384, 360, 336, 408 },
307 { 400, 375, 350, 425 },
308};
309
310static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
311{
312 uint32_t hpll_reg = s->regs[HPLL_PARAM];
313 uint8_t freq_select;
314 bool clk_25m_in;
315
316 if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
317 return 0;
318 }
319
320 if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
321 uint32_t multiplier = 1;
322
323 if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
324 uint32_t n = (hpll_reg >> 5) & 0x3f;
325 uint32_t od = (hpll_reg >> 4) & 0x1;
326 uint32_t d = hpll_reg & 0xf;
327
328 multiplier = (2 - od) * ((n + 2) / (d + 1));
329 }
330
331 return s->clkin * multiplier;
332 }
333
334
335 clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
336 freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
337
338 return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
339}
340
341static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
342{
343 uint32_t hpll_reg = s->regs[HPLL_PARAM];
344 uint32_t multiplier = 1;
345
346 if (hpll_reg & SCU_H_PLL_OFF) {
347 return 0;
348 }
349
350 if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
351 uint32_t p = (hpll_reg >> 13) & 0x3f;
352 uint32_t m = (hpll_reg >> 5) & 0xff;
353 uint32_t n = hpll_reg & 0x1f;
354
355 multiplier = ((m + 1) / (n + 1)) / (p + 1);
356 }
357
358 return s->clkin * multiplier;
359}
360
361static void aspeed_scu_reset(DeviceState *dev)
362{
363 AspeedSCUState *s = ASPEED_SCU(dev);
364 const uint32_t *reset;
365 uint32_t (*calc_hpll)(AspeedSCUState *s);
366
367 switch (s->silicon_rev) {
368 case AST2400_A0_SILICON_REV:
369 case AST2400_A1_SILICON_REV:
370 reset = ast2400_a0_resets;
371 calc_hpll = aspeed_scu_calc_hpll_ast2400;
372 break;
373 case AST2500_A0_SILICON_REV:
374 case AST2500_A1_SILICON_REV:
375 reset = ast2500_a1_resets;
376 calc_hpll = aspeed_scu_calc_hpll_ast2500;
377 break;
378 default:
379 g_assert_not_reached();
380 }
381
382 memcpy(s->regs, reset, sizeof(s->regs));
383 s->regs[SILICON_REV] = s->silicon_rev;
384 s->regs[HW_STRAP1] = s->hw_strap1;
385 s->regs[HW_STRAP2] = s->hw_strap2;
386 s->regs[PROT_KEY] = s->hw_prot_key;
387
388
389
390
391 s->clkin = aspeed_scu_get_clkin(s);
392 s->hpll = calc_hpll(s);
393 aspeed_scu_set_apb_freq(s);
394}
395
396static uint32_t aspeed_silicon_revs[] = {
397 AST2400_A0_SILICON_REV,
398 AST2400_A1_SILICON_REV,
399 AST2500_A0_SILICON_REV,
400 AST2500_A1_SILICON_REV,
401};
402
403bool is_supported_silicon_rev(uint32_t silicon_rev)
404{
405 int i;
406
407 for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
408 if (silicon_rev == aspeed_silicon_revs[i]) {
409 return true;
410 }
411 }
412
413 return false;
414}
415
416static void aspeed_scu_realize(DeviceState *dev, Error **errp)
417{
418 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
419 AspeedSCUState *s = ASPEED_SCU(dev);
420
421 if (!is_supported_silicon_rev(s->silicon_rev)) {
422 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
423 s->silicon_rev);
424 return;
425 }
426
427 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
428 TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
429
430 sysbus_init_mmio(sbd, &s->iomem);
431}
432
433static const VMStateDescription vmstate_aspeed_scu = {
434 .name = "aspeed.scu",
435 .version_id = 1,
436 .minimum_version_id = 1,
437 .fields = (VMStateField[]) {
438 VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
439 VMSTATE_END_OF_LIST()
440 }
441};
442
443static Property aspeed_scu_properties[] = {
444 DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
445 DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
446 DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
447 DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
448 DEFINE_PROP_END_OF_LIST(),
449};
450
451static void aspeed_scu_class_init(ObjectClass *klass, void *data)
452{
453 DeviceClass *dc = DEVICE_CLASS(klass);
454 dc->realize = aspeed_scu_realize;
455 dc->reset = aspeed_scu_reset;
456 dc->desc = "ASPEED System Control Unit";
457 dc->vmsd = &vmstate_aspeed_scu;
458 dc->props = aspeed_scu_properties;
459}
460
461static const TypeInfo aspeed_scu_info = {
462 .name = TYPE_ASPEED_SCU,
463 .parent = TYPE_SYS_BUS_DEVICE,
464 .instance_size = sizeof(AspeedSCUState),
465 .class_init = aspeed_scu_class_init,
466};
467
468static void aspeed_scu_register_types(void)
469{
470 type_register_static(&aspeed_scu_info);
471}
472
473type_init(aspeed_scu_register_types);
474
