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14#include "qemu/osdep.h"
15#include "hw/net/ftgmac100.h"
16#include "sysemu/dma.h"
17#include "qemu/log.h"
18#include "net/checksum.h"
19#include "net/eth.h"
20#include "hw/net/mii.h"
21
22
23#include <zlib.h>
24
25
26
27
28#define FTGMAC100_ISR 0x00
29#define FTGMAC100_IER 0x04
30#define FTGMAC100_MAC_MADR 0x08
31#define FTGMAC100_MAC_LADR 0x0c
32#define FTGMAC100_MATH0 0x10
33#define FTGMAC100_MATH1 0x14
34#define FTGMAC100_NPTXPD 0x18
35#define FTGMAC100_RXPD 0x1C
36#define FTGMAC100_NPTXR_BADR 0x20
37#define FTGMAC100_RXR_BADR 0x24
38#define FTGMAC100_HPTXPD 0x28
39#define FTGMAC100_HPTXR_BADR 0x2c
40#define FTGMAC100_ITC 0x30
41#define FTGMAC100_APTC 0x34
42#define FTGMAC100_DBLAC 0x38
43#define FTGMAC100_REVR 0x40
44#define FTGMAC100_FEAR1 0x44
45#define FTGMAC100_RBSR 0x4c
46#define FTGMAC100_TPAFCR 0x48
47
48#define FTGMAC100_MACCR 0x50
49#define FTGMAC100_MACSR 0x54
50#define FTGMAC100_PHYCR 0x60
51#define FTGMAC100_PHYDATA 0x64
52#define FTGMAC100_FCR 0x68
53
54
55
56
57#define FTGMAC100_INT_RPKT_BUF (1 << 0)
58#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
59#define FTGMAC100_INT_NO_RXBUF (1 << 2)
60#define FTGMAC100_INT_RPKT_LOST (1 << 3)
61#define FTGMAC100_INT_XPKT_ETH (1 << 4)
62#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
63#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
64#define FTGMAC100_INT_XPKT_LOST (1 << 7)
65#define FTGMAC100_INT_AHB_ERR (1 << 8)
66#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
67#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
68
69
70
71
72#define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf)
73#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
74#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf)
75#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
76
77
78
79
80#define FTGMAC100_PHYCR_MIIRD (1 << 26)
81#define FTGMAC100_PHYCR_MIIWR (1 << 27)
82
83#define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f)
84#define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f)
85
86
87
88
89#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
90#define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
91
92
93
94
95#define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31)
96
97
98
99
100#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
101#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
102#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
103#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
104#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
105#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
106#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
107#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
108#define FTGMAC100_MACCR_FULLDUP (1 << 8)
109#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
110#define FTGMAC100_MACCR_CRC_APD (1 << 10)
111#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
112#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
113#define FTGMAC100_MACCR_RX_ALL (1 << 14)
114#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
115#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
116#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
117#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
118#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
119#define FTGMAC100_MACCR_SW_RST (1 << 31)
120
121
122
123
124#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
125#define FTGMAC100_TXDES0_EDOTR (1 << 15)
126#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
127#define FTGMAC100_TXDES0_LTS (1 << 28)
128#define FTGMAC100_TXDES0_FTS (1 << 29)
129#define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
130#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
131
132#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
133#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
134#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
135#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
136#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
137#define FTGMAC100_TXDES1_LLC (1 << 22)
138#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
139#define FTGMAC100_TXDES1_TXIC (1 << 31)
140
141
142
143
144#define FTGMAC100_RXDES0_VDBC 0x3fff
145#define FTGMAC100_RXDES0_EDORR (1 << 15)
146#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
147#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
148#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
149#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
150#define FTGMAC100_RXDES0_FTL (1 << 20)
151#define FTGMAC100_RXDES0_RUNT (1 << 21)
152#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
153#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
154#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
155#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
156#define FTGMAC100_RXDES0_LRS (1 << 28)
157#define FTGMAC100_RXDES0_FRS (1 << 29)
158#define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
159#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
160
161#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
162#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
163#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
164#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
165#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
166#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
167#define FTGMAC100_RXDES1_LLC (1 << 22)
168#define FTGMAC100_RXDES1_DF (1 << 23)
169#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
170#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
171#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
172#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
173
174
175
176
177typedef struct {
178 uint32_t des0;
179 uint32_t des1;
180 uint32_t des2;
181 uint32_t des3;
182} FTGMAC100Desc;
183
184
185
186
187#define RTL8211E_MII_PHYCR 16
188#define RTL8211E_MII_PHYSR 17
189#define RTL8211E_MII_INER 18
190#define RTL8211E_MII_INSR 19
191#define RTL8211E_MII_RXERC 24
192#define RTL8211E_MII_LDPSR 27
193#define RTL8211E_MII_EPAGSR 30
194#define RTL8211E_MII_PAGSEL 31
195
196
197
198
199#define PHY_INT_AUTONEG_ERROR (1 << 15)
200#define PHY_INT_PAGE_RECV (1 << 12)
201#define PHY_INT_AUTONEG_COMPLETE (1 << 11)
202#define PHY_INT_LINK_STATUS (1 << 10)
203#define PHY_INT_ERROR (1 << 9)
204#define PHY_INT_DOWN (1 << 8)
205#define PHY_INT_JABBER (1 << 0)
206
207
208
209
210#define FTGMAC100_MAX_FRAME_SIZE 9220
211
212
213
214
215
216
217static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
218{
219 int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
220
221 return max + (proto == ETH_P_VLAN ? 4 : 0);
222}
223
224static void ftgmac100_update_irq(FTGMAC100State *s)
225{
226 qemu_set_irq(s->irq, s->isr & s->ier);
227}
228
229
230
231
232
233
234
235static void phy_update_irq(FTGMAC100State *s)
236{
237 ftgmac100_update_irq(s);
238}
239
240static void phy_update_link(FTGMAC100State *s)
241{
242
243 if (qemu_get_queue(s->nic)->link_down) {
244 s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
245 s->phy_int |= PHY_INT_DOWN;
246 } else {
247 s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
248 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
249 }
250 phy_update_irq(s);
251}
252
253static void ftgmac100_set_link(NetClientState *nc)
254{
255 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
256}
257
258static void phy_reset(FTGMAC100State *s)
259{
260 s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
261 MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
262 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
263 MII_BMSR_EXTCAP);
264 s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
265 s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
266 MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
267 MII_ANAR_CSMACD);
268 s->phy_int_mask = 0;
269 s->phy_int = 0;
270}
271
272static uint32_t do_phy_read(FTGMAC100State *s, int reg)
273{
274 uint32_t val;
275
276 switch (reg) {
277 case MII_BMCR:
278 val = s->phy_control;
279 break;
280 case MII_BMSR:
281 val = s->phy_status;
282 break;
283 case MII_PHYID1:
284 val = RTL8211E_PHYID1;
285 break;
286 case MII_PHYID2:
287 val = RTL8211E_PHYID2;
288 break;
289 case MII_ANAR:
290 val = s->phy_advertise;
291 break;
292 case MII_ANLPAR:
293 val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
294 MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
295 MII_ANLPAR_CSMACD);
296 break;
297 case MII_ANER:
298 val = MII_ANER_NWAY;
299 break;
300 case MII_CTRL1000:
301 val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
302 break;
303 case MII_STAT1000:
304 val = MII_STAT1000_FULL;
305 break;
306 case RTL8211E_MII_INSR:
307 val = s->phy_int;
308 s->phy_int = 0;
309 phy_update_irq(s);
310 break;
311 case RTL8211E_MII_INER:
312 val = s->phy_int_mask;
313 break;
314 case RTL8211E_MII_PHYCR:
315 case RTL8211E_MII_PHYSR:
316 case RTL8211E_MII_RXERC:
317 case RTL8211E_MII_LDPSR:
318 case RTL8211E_MII_EPAGSR:
319 case RTL8211E_MII_PAGSEL:
320 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
321 __func__, reg);
322 val = 0;
323 break;
324 default:
325 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
326 __func__, reg);
327 val = 0;
328 break;
329 }
330
331 return val;
332}
333
334#define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \
335 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
336 MII_BMCR_FD | MII_BMCR_CTST)
337#define MII_ANAR_MASK 0x2d7f
338
339static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val)
340{
341 switch (reg) {
342 case MII_BMCR:
343 if (val & MII_BMCR_RESET) {
344 phy_reset(s);
345 } else {
346 s->phy_control = val & MII_BMCR_MASK;
347
348 if (val & MII_BMCR_AUTOEN) {
349 s->phy_status |= MII_BMSR_AN_COMP;
350 }
351 }
352 break;
353 case MII_ANAR:
354 s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
355 break;
356 case RTL8211E_MII_INER:
357 s->phy_int_mask = val & 0xff;
358 phy_update_irq(s);
359 break;
360 case RTL8211E_MII_PHYCR:
361 case RTL8211E_MII_PHYSR:
362 case RTL8211E_MII_RXERC:
363 case RTL8211E_MII_LDPSR:
364 case RTL8211E_MII_EPAGSR:
365 case RTL8211E_MII_PAGSEL:
366 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
367 __func__, reg);
368 break;
369 default:
370 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
371 __func__, reg);
372 break;
373 }
374}
375
376static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
377{
378 if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
379 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
380 HWADDR_PRIx "\n", __func__, addr);
381 return -1;
382 }
383 bd->des0 = le32_to_cpu(bd->des0);
384 bd->des1 = le32_to_cpu(bd->des1);
385 bd->des2 = le32_to_cpu(bd->des2);
386 bd->des3 = le32_to_cpu(bd->des3);
387 return 0;
388}
389
390static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
391{
392 FTGMAC100Desc lebd;
393
394 lebd.des0 = cpu_to_le32(bd->des0);
395 lebd.des1 = cpu_to_le32(bd->des1);
396 lebd.des2 = cpu_to_le32(bd->des2);
397 lebd.des3 = cpu_to_le32(bd->des3);
398 if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
399 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
400 HWADDR_PRIx "\n", __func__, addr);
401 return -1;
402 }
403 return 0;
404}
405
406static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
407 uint32_t tx_descriptor)
408{
409 int frame_size = 0;
410 uint8_t *ptr = s->frame;
411 uint32_t addr = tx_descriptor;
412 uint32_t flags = 0;
413
414 while (1) {
415 FTGMAC100Desc bd;
416 int len;
417
418 if (ftgmac100_read_bd(&bd, addr) ||
419 ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
420
421 s->isr |= FTGMAC100_INT_NO_NPTXBUF;
422 break;
423 }
424
425
426
427 if (bd.des0 & FTGMAC100_TXDES0_FTS) {
428 flags = bd.des1;
429 }
430
431 len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
432 if (frame_size + len > sizeof(s->frame)) {
433 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
434 __func__, len);
435 s->isr |= FTGMAC100_INT_XPKT_LOST;
436 len = sizeof(s->frame) - frame_size;
437 }
438
439 if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
440 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
441 __func__, bd.des3);
442 s->isr |= FTGMAC100_INT_NO_NPTXBUF;
443 break;
444 }
445
446
447 if (bd.des0 & FTGMAC100_TXDES0_FTS &&
448 bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
449 be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
450 if (frame_size + len + 4 > sizeof(s->frame)) {
451 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
452 __func__, len);
453 s->isr |= FTGMAC100_INT_XPKT_LOST;
454 len = sizeof(s->frame) - frame_size - 4;
455 }
456 memmove(ptr + 16, ptr + 12, len - 12);
457 stw_be_p(ptr + 12, ETH_P_VLAN);
458 stw_be_p(ptr + 14, bd.des1);
459 len += 4;
460 }
461
462 ptr += len;
463 frame_size += len;
464 if (bd.des0 & FTGMAC100_TXDES0_LTS) {
465 if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
466 net_checksum_calculate(s->frame, frame_size);
467 }
468
469 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
470 ptr = s->frame;
471 frame_size = 0;
472 if (flags & FTGMAC100_TXDES1_TXIC) {
473 s->isr |= FTGMAC100_INT_XPKT_ETH;
474 }
475 }
476
477 if (flags & FTGMAC100_TXDES1_TX2FIC) {
478 s->isr |= FTGMAC100_INT_XPKT_FIFO;
479 }
480 bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
481
482
483 ftgmac100_write_bd(&bd, addr);
484
485 if (bd.des0 & s->txdes0_edotr) {
486 addr = tx_ring;
487 } else {
488 addr += sizeof(FTGMAC100Desc);
489 }
490 }
491
492 s->tx_descriptor = addr;
493
494 ftgmac100_update_irq(s);
495}
496
497static int ftgmac100_can_receive(NetClientState *nc)
498{
499 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
500 FTGMAC100Desc bd;
501
502 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
503 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
504 return 0;
505 }
506
507 if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
508 return 0;
509 }
510 return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
511}
512
513
514
515
516
517
518static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
519{
520
521
522
523
524
525
526
527
528 static const int div[] = { 20, 200, 1000 };
529
530 uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
531 uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
532
533 if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
534 cnt <<= 4;
535 }
536
537 if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
538 speed = 2;
539 }
540
541 return cnt / div[speed];
542}
543
544static void ftgmac100_reset(DeviceState *d)
545{
546 FTGMAC100State *s = FTGMAC100(d);
547
548
549 s->isr = 0;
550 s->ier = 0;
551 s->rx_enabled = 0;
552 s->rx_ring = 0;
553 s->rbsr = 0x640;
554 s->rx_descriptor = 0;
555 s->tx_ring = 0;
556 s->tx_descriptor = 0;
557 s->math[0] = 0;
558 s->math[1] = 0;
559 s->itc = 0;
560 s->aptcr = 1;
561 s->dblac = 0x00022f00;
562 s->revr = 0;
563 s->fear1 = 0;
564 s->tpafcr = 0xf1;
565
566 s->maccr = 0;
567 s->phycr = 0;
568 s->phydata = 0;
569 s->fcr = 0x400;
570
571
572 phy_reset(s);
573}
574
575static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
576{
577 FTGMAC100State *s = FTGMAC100(opaque);
578
579 switch (addr & 0xff) {
580 case FTGMAC100_ISR:
581 return s->isr;
582 case FTGMAC100_IER:
583 return s->ier;
584 case FTGMAC100_MAC_MADR:
585 return (s->conf.macaddr.a[0] << 8) | s->conf.macaddr.a[1];
586 case FTGMAC100_MAC_LADR:
587 return ((uint32_t) s->conf.macaddr.a[2] << 24) |
588 (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
589 s->conf.macaddr.a[5];
590 case FTGMAC100_MATH0:
591 return s->math[0];
592 case FTGMAC100_MATH1:
593 return s->math[1];
594 case FTGMAC100_ITC:
595 return s->itc;
596 case FTGMAC100_DBLAC:
597 return s->dblac;
598 case FTGMAC100_REVR:
599 return s->revr;
600 case FTGMAC100_FEAR1:
601 return s->fear1;
602 case FTGMAC100_TPAFCR:
603 return s->tpafcr;
604 case FTGMAC100_FCR:
605 return s->fcr;
606 case FTGMAC100_MACCR:
607 return s->maccr;
608 case FTGMAC100_PHYCR:
609 return s->phycr;
610 case FTGMAC100_PHYDATA:
611 return s->phydata;
612
613
614 case FTGMAC100_HPTXPD:
615 case FTGMAC100_HPTXR_BADR:
616 case FTGMAC100_MACSR:
617 qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
618 HWADDR_PRIx "\n", __func__, addr);
619 return 0;
620 default:
621 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
622 HWADDR_PRIx "\n", __func__, addr);
623 return 0;
624 }
625}
626
627static void ftgmac100_write(void *opaque, hwaddr addr,
628 uint64_t value, unsigned size)
629{
630 FTGMAC100State *s = FTGMAC100(opaque);
631 int reg;
632
633 switch (addr & 0xff) {
634 case FTGMAC100_ISR:
635 s->isr &= ~value;
636 break;
637 case FTGMAC100_IER:
638 s->ier = value;
639 break;
640 case FTGMAC100_MAC_MADR:
641 s->conf.macaddr.a[0] = value >> 8;
642 s->conf.macaddr.a[1] = value;
643 break;
644 case FTGMAC100_MAC_LADR:
645 s->conf.macaddr.a[2] = value >> 24;
646 s->conf.macaddr.a[3] = value >> 16;
647 s->conf.macaddr.a[4] = value >> 8;
648 s->conf.macaddr.a[5] = value;
649 break;
650 case FTGMAC100_MATH0:
651 s->math[0] = value;
652 break;
653 case FTGMAC100_MATH1:
654 s->math[1] = value;
655 break;
656 case FTGMAC100_ITC:
657 s->itc = value;
658 break;
659 case FTGMAC100_RXR_BADR:
660 s->rx_ring = value;
661 s->rx_descriptor = s->rx_ring;
662 break;
663
664 case FTGMAC100_RBSR:
665 s->rbsr = value;
666 break;
667
668 case FTGMAC100_NPTXR_BADR:
669 s->tx_ring = value;
670 s->tx_descriptor = s->tx_ring;
671 break;
672
673 case FTGMAC100_NPTXPD:
674 if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
675 == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
676
677 ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
678 }
679 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
680 qemu_flush_queued_packets(qemu_get_queue(s->nic));
681 }
682 break;
683
684 case FTGMAC100_RXPD:
685 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
686 qemu_flush_queued_packets(qemu_get_queue(s->nic));
687 }
688 break;
689
690 case FTGMAC100_APTC:
691 s->aptcr = value;
692
693 if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
694 ftgmac100_rxpoll(s);
695 }
696
697 if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
698 qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
699 }
700 break;
701
702 case FTGMAC100_MACCR:
703 s->maccr = value;
704 if (value & FTGMAC100_MACCR_SW_RST) {
705 ftgmac100_reset(DEVICE(s));
706 }
707
708 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
709 qemu_flush_queued_packets(qemu_get_queue(s->nic));
710 }
711 break;
712
713 case FTGMAC100_PHYCR:
714 reg = FTGMAC100_PHYCR_REG(value);
715 s->phycr = value;
716 if (value & FTGMAC100_PHYCR_MIIWR) {
717 do_phy_write(s, reg, s->phydata & 0xffff);
718 s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
719 } else {
720 s->phydata = do_phy_read(s, reg) << 16;
721 s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
722 }
723 break;
724 case FTGMAC100_PHYDATA:
725 s->phydata = value & 0xffff;
726 break;
727 case FTGMAC100_DBLAC:
728 s->dblac = value;
729 break;
730 case FTGMAC100_REVR:
731
732 s->revr = value & ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
733 break;
734 case FTGMAC100_FEAR1:
735 s->fear1 = value;
736 break;
737 case FTGMAC100_TPAFCR:
738 s->tpafcr = value;
739 break;
740 case FTGMAC100_FCR:
741 s->fcr = value;
742 break;
743
744 case FTGMAC100_HPTXPD:
745 case FTGMAC100_HPTXR_BADR:
746 case FTGMAC100_MACSR:
747 qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
748 HWADDR_PRIx "\n", __func__, addr);
749 break;
750 default:
751 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
752 HWADDR_PRIx "\n", __func__, addr);
753 break;
754 }
755
756 ftgmac100_update_irq(s);
757}
758
759static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
760{
761 unsigned mcast_idx;
762
763 if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
764 return 1;
765 }
766
767 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
768 case ETH_PKT_BCAST:
769 if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
770 return 0;
771 }
772 break;
773 case ETH_PKT_MCAST:
774 if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
775 if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
776 return 0;
777 }
778
779 mcast_idx = net_crc32_le(buf, ETH_ALEN);
780 mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
781 if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
782 return 0;
783 }
784 }
785 break;
786 case ETH_PKT_UCAST:
787 if (memcmp(s->conf.macaddr.a, buf, 6)) {
788 return 0;
789 }
790 break;
791 }
792
793 return 1;
794}
795
796static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
797 size_t len)
798{
799 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
800 FTGMAC100Desc bd;
801 uint32_t flags = 0;
802 uint32_t addr;
803 uint32_t crc;
804 uint32_t buf_addr;
805 uint8_t *crc_ptr;
806 uint32_t buf_len;
807 size_t size = len;
808 uint32_t first = FTGMAC100_RXDES0_FRS;
809 uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
810 int max_frame_size = ftgmac100_max_frame_size(s, proto);
811
812 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
813 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
814 return -1;
815 }
816
817
818
819 if (size < 10) {
820 qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
821 __func__, size);
822 return size;
823 }
824
825 if (!ftgmac100_filter(s, buf, size)) {
826 return size;
827 }
828
829
830 size += 4;
831 crc = cpu_to_be32(crc32(~0, buf, size));
832 crc_ptr = (uint8_t *) &crc;
833
834
835 if (size > max_frame_size) {
836 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
837 __func__, size);
838 size = max_frame_size;
839 flags |= FTGMAC100_RXDES0_FTL;
840 }
841
842 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
843 case ETH_PKT_BCAST:
844 flags |= FTGMAC100_RXDES0_BROADCAST;
845 break;
846 case ETH_PKT_MCAST:
847 flags |= FTGMAC100_RXDES0_MULTICAST;
848 break;
849 case ETH_PKT_UCAST:
850 break;
851 }
852
853 addr = s->rx_descriptor;
854 while (size > 0) {
855 if (!ftgmac100_can_receive(nc)) {
856 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
857 return -1;
858 }
859
860 if (ftgmac100_read_bd(&bd, addr) ||
861 (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
862
863 qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
864 __func__);
865 s->isr |= FTGMAC100_INT_NO_RXBUF;
866 break;
867 }
868 buf_len = (size <= s->rbsr) ? size : s->rbsr;
869 bd.des0 |= buf_len & 0x3fff;
870 size -= buf_len;
871
872
873 if (size < 4) {
874 buf_len += size - 4;
875 }
876 buf_addr = bd.des3;
877 if (first && proto == ETH_P_VLAN && buf_len >= 18) {
878 bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
879
880 if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
881 dma_memory_write(&address_space_memory, buf_addr, buf, 12);
882 dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
883 buf_len - 16);
884 } else {
885 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
886 }
887 } else {
888 bd.des1 = 0;
889 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
890 }
891 buf += buf_len;
892 if (size < 4) {
893 dma_memory_write(&address_space_memory, buf_addr + buf_len,
894 crc_ptr, 4 - size);
895 crc_ptr += 4 - size;
896 }
897
898 bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
899 first = 0;
900 if (size == 0) {
901
902 bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
903 s->isr |= FTGMAC100_INT_RPKT_BUF;
904 } else {
905 s->isr |= FTGMAC100_INT_RPKT_FIFO;
906 }
907 ftgmac100_write_bd(&bd, addr);
908 if (bd.des0 & s->rxdes0_edorr) {
909 addr = s->rx_ring;
910 } else {
911 addr += sizeof(FTGMAC100Desc);
912 }
913 }
914 s->rx_descriptor = addr;
915
916 ftgmac100_update_irq(s);
917 return len;
918}
919
920static const MemoryRegionOps ftgmac100_ops = {
921 .read = ftgmac100_read,
922 .write = ftgmac100_write,
923 .valid.min_access_size = 4,
924 .valid.max_access_size = 4,
925 .endianness = DEVICE_LITTLE_ENDIAN,
926};
927
928static void ftgmac100_cleanup(NetClientState *nc)
929{
930 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
931
932 s->nic = NULL;
933}
934
935static NetClientInfo net_ftgmac100_info = {
936 .type = NET_CLIENT_DRIVER_NIC,
937 .size = sizeof(NICState),
938 .can_receive = ftgmac100_can_receive,
939 .receive = ftgmac100_receive,
940 .cleanup = ftgmac100_cleanup,
941 .link_status_changed = ftgmac100_set_link,
942};
943
944static void ftgmac100_realize(DeviceState *dev, Error **errp)
945{
946 FTGMAC100State *s = FTGMAC100(dev);
947 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
948
949 if (s->aspeed) {
950 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
951 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
952 } else {
953 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
954 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
955 }
956
957 memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
958 TYPE_FTGMAC100, 0x2000);
959 sysbus_init_mmio(sbd, &s->iomem);
960 sysbus_init_irq(sbd, &s->irq);
961 qemu_macaddr_default_if_unset(&s->conf.macaddr);
962
963 s->conf.peers.ncs[0] = nd_table[0].netdev;
964
965 s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
966 object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
967 s);
968 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
969}
970
971static const VMStateDescription vmstate_ftgmac100 = {
972 .name = TYPE_FTGMAC100,
973 .version_id = 1,
974 .minimum_version_id = 1,
975 .fields = (VMStateField[]) {
976 VMSTATE_UINT32(irq_state, FTGMAC100State),
977 VMSTATE_UINT32(isr, FTGMAC100State),
978 VMSTATE_UINT32(ier, FTGMAC100State),
979 VMSTATE_UINT32(rx_enabled, FTGMAC100State),
980 VMSTATE_UINT32(rx_ring, FTGMAC100State),
981 VMSTATE_UINT32(rbsr, FTGMAC100State),
982 VMSTATE_UINT32(tx_ring, FTGMAC100State),
983 VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
984 VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
985 VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
986 VMSTATE_UINT32(itc, FTGMAC100State),
987 VMSTATE_UINT32(aptcr, FTGMAC100State),
988 VMSTATE_UINT32(dblac, FTGMAC100State),
989 VMSTATE_UINT32(revr, FTGMAC100State),
990 VMSTATE_UINT32(fear1, FTGMAC100State),
991 VMSTATE_UINT32(tpafcr, FTGMAC100State),
992 VMSTATE_UINT32(maccr, FTGMAC100State),
993 VMSTATE_UINT32(phycr, FTGMAC100State),
994 VMSTATE_UINT32(phydata, FTGMAC100State),
995 VMSTATE_UINT32(fcr, FTGMAC100State),
996 VMSTATE_UINT32(phy_status, FTGMAC100State),
997 VMSTATE_UINT32(phy_control, FTGMAC100State),
998 VMSTATE_UINT32(phy_advertise, FTGMAC100State),
999 VMSTATE_UINT32(phy_int, FTGMAC100State),
1000 VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
1001 VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
1002 VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
1003 VMSTATE_END_OF_LIST()
1004 }
1005};
1006
1007static Property ftgmac100_properties[] = {
1008 DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
1009 DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
1010 DEFINE_PROP_END_OF_LIST(),
1011};
1012
1013static void ftgmac100_class_init(ObjectClass *klass, void *data)
1014{
1015 DeviceClass *dc = DEVICE_CLASS(klass);
1016
1017 dc->vmsd = &vmstate_ftgmac100;
1018 dc->reset = ftgmac100_reset;
1019 dc->props = ftgmac100_properties;
1020 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1021 dc->realize = ftgmac100_realize;
1022 dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1023}
1024
1025static const TypeInfo ftgmac100_info = {
1026 .name = TYPE_FTGMAC100,
1027 .parent = TYPE_SYS_BUS_DEVICE,
1028 .instance_size = sizeof(FTGMAC100State),
1029 .class_init = ftgmac100_class_init,
1030};
1031
1032static void ftgmac100_register_types(void)
1033{
1034 type_register_static(&ftgmac100_info);
1035}
1036
1037type_init(ftgmac100_register_types)
1038
