LXR qemu/hw/pci-bridge/gen_pcie_root

   1/*
   2 * Generic PCI Express Root Port emulation
   3 *
   4 * Copyright (C) 2017 Red Hat Inc
   5 *
   6 * Authors:
   7 *   Marcel Apfelbaum <marcel@redhat.com>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 */
  12
  13#include "qemu/osdep.h"
  14#include "qapi/error.h"
  15#include "hw/pci/msix.h"
  16#include "hw/pci/pcie_port.h"
  17
  18#define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
  19#define GEN_PCIE_ROOT_PORT(obj) \
  20        OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
  21
  22#define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
  23#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
  24
  25typedef struct GenPCIERootPort {
  26    /*< private >*/
  27    PCIESlot parent_obj;
  28    /*< public >*/
  29
  30    bool migrate_msix;
  31
  32    /* additional resources to reserve */
  33    PCIResReserve res_reserve;
  34} GenPCIERootPort;
  35
  36static uint8_t gen_rp_aer_vector(const PCIDevice *d)
  37{
  38    return 0;
  39}
  40
  41static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
  42{
  43    int rc;
  44
  45    rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
  46
  47    if (rc < 0) {
  48        assert(rc == -ENOTSUP);
  49    } else {
  50        msix_vector_use(d, 0);
  51    }
  52
  53    return rc;
  54}
  55
  56static void gen_rp_interrupts_uninit(PCIDevice *d)
  57{
  58    msix_uninit_exclusive_bar(d);
  59}
  60
  61static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
  62{
  63    GenPCIERootPort *rp = opaque;
  64
  65    return rp->migrate_msix;
  66}
  67
  68static void gen_rp_realize(DeviceState *dev, Error **errp)
  69{
  70    PCIDevice *d = PCI_DEVICE(dev);
  71    GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
  72    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
  73    Error *local_err = NULL;
  74
  75    rpc->parent_realize(dev, &local_err);
  76    if (local_err) {
  77        error_propagate(errp, local_err);
  78        return;
  79    }
  80
  81    int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
  82                                              grp->res_reserve, errp);
  83
  84    if (rc < 0) {
  85        rpc->parent_class.exit(d);
  86        return;
  87    }
  88
  89    if (!grp->res_reserve.io) {
  90        pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
  91                                     PCI_COMMAND_IO);
  92        d->wmask[PCI_IO_BASE] = 0;
  93        d->wmask[PCI_IO_LIMIT] = 0;
  94    }
  95}
  96
  97static const VMStateDescription vmstate_rp_dev = {
  98    .name = "pcie-root-port",
  99    .priority = MIG_PRI_PCI_BUS,
 100    .version_id = 1,
 101    .minimum_version_id = 1,
 102    .post_load = pcie_cap_slot_post_load,
 103    .fields = (VMStateField[]) {
 104        VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 105        VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 106                       PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 107        VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
 108                          GenPCIERootPort,
 109                          gen_rp_test_migrate_msix),
 110        VMSTATE_END_OF_LIST()
 111    }
 112};
 113
 114static Property gen_rp_props[] = {
 115    DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
 116                     migrate_msix, true),
 117    DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
 118                       res_reserve.bus, -1),
 119    DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
 120                     res_reserve.io, -1),
 121    DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
 122                     res_reserve.mem_non_pref, -1),
 123    DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
 124                     res_reserve.mem_pref_32, -1),
 125    DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
 126                     res_reserve.mem_pref_64, -1),
 127    DEFINE_PROP_END_OF_LIST()
 128};
 129
 130static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
 131{
 132    DeviceClass *dc = DEVICE_CLASS(klass);
 133    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 134    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
 135
 136    k->vendor_id = PCI_VENDOR_ID_REDHAT;
 137    k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
 138    dc->desc = "PCI Express Root Port";
 139    dc->vmsd = &vmstate_rp_dev;
 140    dc->props = gen_rp_props;
 141
 142    device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
 143
 144    rpc->aer_vector = gen_rp_aer_vector;
 145    rpc->interrupts_init = gen_rp_interrupts_init;
 146    rpc->interrupts_uninit = gen_rp_interrupts_uninit;
 147    rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
 148}
 149
 150static const TypeInfo gen_rp_dev_info = {
 151    .name          = TYPE_GEN_PCIE_ROOT_PORT,
 152    .parent        = TYPE_PCIE_ROOT_PORT,
 153    .instance_size = sizeof(GenPCIERootPort),
 154    .class_init    = gen_rp_dev_class_init,
 155};
 156
 157 static void gen_rp_register_types(void)
 158 {
 159    type_register_static(&gen_rp_dev_info);
 160 }
 161 type_init(gen_rp_register_types)
 162