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17#include "qemu/osdep.h"
18#include "qemu/units.h"
19#include "qapi/error.h"
20#include "e500.h"
21#include "e500-ccsr.h"
22#include "net/net.h"
23#include "qemu/config-file.h"
24#include "hw/hw.h"
25#include "hw/char/serial.h"
26#include "hw/pci/pci.h"
27#include "hw/boards.h"
28#include "sysemu/sysemu.h"
29#include "sysemu/kvm.h"
30#include "kvm_ppc.h"
31#include "sysemu/device_tree.h"
32#include "hw/ppc/openpic.h"
33#include "hw/ppc/openpic_kvm.h"
34#include "hw/ppc/ppc.h"
35#include "hw/loader.h"
36#include "elf.h"
37#include "hw/sysbus.h"
38#include "exec/address-spaces.h"
39#include "qemu/host-utils.h"
40#include "qemu/option.h"
41#include "hw/pci-host/ppce500.h"
42#include "qemu/error-report.h"
43#include "hw/platform-bus.h"
44#include "hw/net/fsl_etsec/etsec.h"
45
46#define EPAPR_MAGIC (0x45504150)
47#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
48#define DTC_LOAD_PAD 0x1800000
49#define DTC_PAD_MASK 0xFFFFF
50#define DTB_MAX_SIZE (8 * MiB)
51#define INITRD_LOAD_PAD 0x2000000
52#define INITRD_PAD_MASK 0xFFFFFF
53
54#define RAM_SIZES_ALIGN (64 * MiB)
55
56
57#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
58#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
59#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
60#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
61#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
62#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
63#define MPC8544_PCI_REGS_SIZE 0x1000ULL
64#define MPC8544_UTIL_OFFSET 0xe0000ULL
65#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
66#define MPC8XXX_GPIO_IRQ 47
67
68struct boot_info
69{
70 uint32_t dt_base;
71 uint32_t dt_size;
72 uint32_t entry;
73};
74
75static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
76 int nr_slots, int *len)
77{
78 int i = 0;
79 int slot;
80 int pci_irq;
81 int host_irq;
82 int last_slot = first_slot + nr_slots;
83 uint32_t *pci_map;
84
85 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
86 pci_map = g_malloc(*len);
87
88 for (slot = first_slot; slot < last_slot; slot++) {
89 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
90 pci_map[i++] = cpu_to_be32(slot << 11);
91 pci_map[i++] = cpu_to_be32(0x0);
92 pci_map[i++] = cpu_to_be32(0x0);
93 pci_map[i++] = cpu_to_be32(pci_irq + 1);
94 pci_map[i++] = cpu_to_be32(mpic);
95 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
96 pci_map[i++] = cpu_to_be32(host_irq + 1);
97 pci_map[i++] = cpu_to_be32(0x1);
98 }
99 }
100
101 assert((i * sizeof(uint32_t)) == *len);
102
103 return pci_map;
104}
105
106static void dt_serial_create(void *fdt, unsigned long long offset,
107 const char *soc, const char *mpic,
108 const char *alias, int idx, bool defcon)
109{
110 char *ser;
111
112 ser = g_strdup_printf("%s/serial@%llx", soc, offset);
113 qemu_fdt_add_subnode(fdt, ser);
114 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
115 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
116 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
117 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
118 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
119 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
120 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
121 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
122
123 if (defcon) {
124
125
126
127
128
129
130 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
131 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
132 }
133 g_free(ser);
134}
135
136static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
137{
138 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
139 int irq0 = MPC8XXX_GPIO_IRQ;
140 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
141 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
142 int gpio_ph;
143
144 qemu_fdt_add_subnode(fdt, node);
145 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
146 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
147 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
148 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
149 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
150 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
151 gpio_ph = qemu_fdt_alloc_phandle(fdt);
152 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
153 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
154
155
156 qemu_fdt_add_subnode(fdt, poweroff);
157 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
158 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
159
160 g_free(node);
161 g_free(poweroff);
162}
163
164typedef struct PlatformDevtreeData {
165 void *fdt;
166 const char *mpic;
167 int irq_start;
168 const char *node;
169 PlatformBusDevice *pbus;
170} PlatformDevtreeData;
171
172static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
173{
174 eTSEC *etsec = ETSEC_COMMON(sbdev);
175 PlatformBusDevice *pbus = data->pbus;
176 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
177 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
178 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
179 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
180 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
181 gchar *group = g_strdup_printf("%s/queue-group", node);
182 void *fdt = data->fdt;
183
184 assert((int64_t)mmio0 >= 0);
185 assert(irq0 >= 0);
186 assert(irq1 >= 0);
187 assert(irq2 >= 0);
188
189 qemu_fdt_add_subnode(fdt, node);
190 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
191 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
192 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
193 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
194 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
195
196 qemu_fdt_add_subnode(fdt, group);
197 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
198 qemu_fdt_setprop_cells(fdt, group, "interrupts",
199 data->irq_start + irq0, 0x2,
200 data->irq_start + irq1, 0x2,
201 data->irq_start + irq2, 0x2);
202
203 g_free(node);
204 g_free(group);
205
206 return 0;
207}
208
209static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
210{
211 PlatformDevtreeData *data = opaque;
212 bool matched = false;
213
214 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
215 create_devtree_etsec(sbdev, data);
216 matched = true;
217 }
218
219 if (!matched) {
220 error_report("Device %s is not supported by this machine yet.",
221 qdev_fw_name(DEVICE(sbdev)));
222 exit(1);
223 }
224}
225
226static void platform_bus_create_devtree(PPCE500MachineState *pms,
227 void *fdt, const char *mpic)
228{
229 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
230 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
231 const char platcomp[] = "qemu,platform\0simple-bus";
232 uint64_t addr = pmc->platform_bus_base;
233 uint64_t size = pmc->platform_bus_size;
234 int irq_start = pmc->platform_bus_first_irq;
235
236
237
238 qemu_fdt_add_subnode(fdt, node);
239 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
240
241
242
243 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
244 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
245 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
246
247 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
248
249
250 PlatformDevtreeData data = {
251 .fdt = fdt,
252 .mpic = mpic,
253 .irq_start = irq_start,
254 .node = node,
255 .pbus = pms->pbus_dev,
256 };
257
258
259 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
260
261 g_free(node);
262}
263
264static int ppce500_load_device_tree(PPCE500MachineState *pms,
265 hwaddr addr,
266 hwaddr initrd_base,
267 hwaddr initrd_size,
268 hwaddr kernel_base,
269 hwaddr kernel_size,
270 bool dry_run)
271{
272 MachineState *machine = MACHINE(pms);
273 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
274 CPUPPCState *env = first_cpu->env_ptr;
275 int ret = -1;
276 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
277 int fdt_size;
278 void *fdt;
279 uint8_t hypercall[16];
280 uint32_t clock_freq = 400000000;
281 uint32_t tb_freq = 400000000;
282 int i;
283 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
284 char *soc;
285 char *mpic;
286 uint32_t mpic_ph;
287 uint32_t msi_ph;
288 char *gutil;
289 char *pci;
290 char *msi;
291 uint32_t *pci_map = NULL;
292 int len;
293 uint32_t pci_ranges[14] =
294 {
295 0x2000000, 0x0, pmc->pci_mmio_bus_base,
296 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
297 0x0, 0x20000000,
298
299 0x1000000, 0x0, 0x0,
300 pmc->pci_pio_base >> 32, pmc->pci_pio_base,
301 0x0, 0x10000,
302 };
303 QemuOpts *machine_opts = qemu_get_machine_opts();
304 const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
305 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
306
307 if (dtb_file) {
308 char *filename;
309 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
310 if (!filename) {
311 goto out;
312 }
313
314 fdt = load_device_tree(filename, &fdt_size);
315 g_free(filename);
316 if (!fdt) {
317 goto out;
318 }
319 goto done;
320 }
321
322 fdt = create_device_tree(&fdt_size);
323 if (fdt == NULL) {
324 goto out;
325 }
326
327
328 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
329 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
330
331 qemu_fdt_add_subnode(fdt, "/memory");
332 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
333 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
334 sizeof(mem_reg_property));
335
336 qemu_fdt_add_subnode(fdt, "/chosen");
337 if (initrd_size) {
338 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
339 initrd_base);
340 if (ret < 0) {
341 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
342 }
343
344 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
345 (initrd_base + initrd_size));
346 if (ret < 0) {
347 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
348 }
349
350 }
351
352 if (kernel_base != -1ULL) {
353 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
354 kernel_base >> 32, kernel_base,
355 kernel_size >> 32, kernel_size);
356 }
357
358 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
359 machine->kernel_cmdline);
360 if (ret < 0)
361 fprintf(stderr, "couldn't set /chosen/bootargs\n");
362
363 if (kvm_enabled()) {
364
365 clock_freq = kvmppc_get_clockfreq();
366 tb_freq = kvmppc_get_tbfreq();
367
368
369 qemu_fdt_add_subnode(fdt, "/hypervisor");
370 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
371 "linux,kvm");
372 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
373 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
374 hypercall, sizeof(hypercall));
375
376 if (kvmppc_get_hasidle(env)) {
377 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
378 }
379 }
380
381
382 qemu_fdt_add_subnode(fdt, "/cpus");
383 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
384 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
385
386
387
388 for (i = smp_cpus - 1; i >= 0; i--) {
389 CPUState *cpu;
390 char *cpu_name;
391 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
392
393 cpu = qemu_get_cpu(i);
394 if (cpu == NULL) {
395 continue;
396 }
397 env = cpu->env_ptr;
398
399 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
400 qemu_fdt_add_subnode(fdt, cpu_name);
401 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
402 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
403 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
404 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
405 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
406 env->dcache_line_size);
407 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
408 env->icache_line_size);
409 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
410 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
411 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
412 if (cpu->cpu_index) {
413 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
414 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
415 "spin-table");
416 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
417 cpu_release_addr);
418 } else {
419 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
420 }
421 g_free(cpu_name);
422 }
423
424 qemu_fdt_add_subnode(fdt, "/aliases");
425
426 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
427 qemu_fdt_add_subnode(fdt, soc);
428 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
429 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
430 sizeof(compatible_sb));
431 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
432 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
433 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
434 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
435 MPC8544_CCSRBAR_SIZE);
436
437 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
438
439 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
440 qemu_fdt_add_subnode(fdt, mpic);
441 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
442 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
443 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
444 0x40000);
445 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
446 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
447 mpic_ph = qemu_fdt_alloc_phandle(fdt);
448 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
449 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
450 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
451
452
453
454
455
456
457 if (serial_hd(1)) {
458 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
459 soc, mpic, "serial1", 1, false);
460 }
461
462 if (serial_hd(0)) {
463 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
464 soc, mpic, "serial0", 0, true);
465 }
466
467 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
468 MPC8544_UTIL_OFFSET);
469 qemu_fdt_add_subnode(fdt, gutil);
470 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
471 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
472 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
473 g_free(gutil);
474
475 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
476 qemu_fdt_add_subnode(fdt, msi);
477 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
478 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
479 msi_ph = qemu_fdt_alloc_phandle(fdt);
480 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
481 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
482 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
483 0xe0, 0x0,
484 0xe1, 0x0,
485 0xe2, 0x0,
486 0xe3, 0x0,
487 0xe4, 0x0,
488 0xe5, 0x0,
489 0xe6, 0x0,
490 0xe7, 0x0);
491 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
492 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
493 g_free(msi);
494
495 pci = g_strdup_printf("/pci@%llx",
496 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
497 qemu_fdt_add_subnode(fdt, pci);
498 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
499 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
500 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
501 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
502 0x0, 0x7);
503 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
504 pmc->pci_first_slot, pmc->pci_nr_slots,
505 &len);
506 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
507 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
508 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
509 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
510 for (i = 0; i < 14; i++) {
511 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
512 }
513 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
514 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
515 qemu_fdt_setprop_cells(fdt, pci, "reg",
516 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
517 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
518 0, 0x1000);
519 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
520 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
521 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
522 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
523 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
524 g_free(pci);
525
526 if (pmc->has_mpc8xxx_gpio) {
527 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
528 }
529 g_free(soc);
530
531 if (pms->pbus_dev) {
532 platform_bus_create_devtree(pms, fdt, mpic);
533 }
534 g_free(mpic);
535
536 pmc->fixup_devtree(fdt);
537
538 if (toplevel_compat) {
539 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
540 strlen(toplevel_compat) + 1);
541 }
542
543done:
544 if (!dry_run) {
545 qemu_fdt_dumpdtb(fdt, fdt_size);
546 cpu_physical_memory_write(addr, fdt, fdt_size);
547 }
548 ret = fdt_size;
549
550out:
551 g_free(pci_map);
552
553 return ret;
554}
555
556typedef struct DeviceTreeParams {
557 PPCE500MachineState *machine;
558 hwaddr addr;
559 hwaddr initrd_base;
560 hwaddr initrd_size;
561 hwaddr kernel_base;
562 hwaddr kernel_size;
563 Notifier notifier;
564} DeviceTreeParams;
565
566static void ppce500_reset_device_tree(void *opaque)
567{
568 DeviceTreeParams *p = opaque;
569 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
570 p->initrd_size, p->kernel_base, p->kernel_size,
571 false);
572}
573
574static void ppce500_init_notify(Notifier *notifier, void *data)
575{
576 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
577 ppce500_reset_device_tree(p);
578}
579
580static int ppce500_prep_device_tree(PPCE500MachineState *machine,
581 hwaddr addr,
582 hwaddr initrd_base,
583 hwaddr initrd_size,
584 hwaddr kernel_base,
585 hwaddr kernel_size)
586{
587 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
588 p->machine = machine;
589 p->addr = addr;
590 p->initrd_base = initrd_base;
591 p->initrd_size = initrd_size;
592 p->kernel_base = kernel_base;
593 p->kernel_size = kernel_size;
594
595 qemu_register_reset(ppce500_reset_device_tree, p);
596 p->notifier.notify = ppce500_init_notify;
597 qemu_add_machine_init_done_notifier(&p->notifier);
598
599
600 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
601 kernel_base, kernel_size, true);
602}
603
604
605hwaddr booke206_page_size_to_tlb(uint64_t size)
606{
607 return 63 - clz64(size / KiB);
608}
609
610static int booke206_initial_map_tsize(CPUPPCState *env)
611{
612 struct boot_info *bi = env->load_info;
613 hwaddr dt_end;
614 int ps;
615
616
617
618 dt_end = bi->dt_base + bi->dt_size;
619 ps = booke206_page_size_to_tlb(dt_end) + 1;
620 if (ps & 1) {
621
622 ps++;
623 }
624 return ps;
625}
626
627static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
628{
629 int tsize;
630
631 tsize = booke206_initial_map_tsize(env);
632 return (1ULL << 10 << tsize);
633}
634
635static void mmubooke_create_initial_mapping(CPUPPCState *env)
636{
637 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
638 hwaddr size;
639 int ps;
640
641 ps = booke206_initial_map_tsize(env);
642 size = (ps << MAS1_TSIZE_SHIFT);
643 tlb->mas1 = MAS1_VALID | size;
644 tlb->mas2 = 0;
645 tlb->mas7_3 = 0;
646 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
647
648 env->tlb_dirty = true;
649}
650
651static void ppce500_cpu_reset_sec(void *opaque)
652{
653 PowerPCCPU *cpu = opaque;
654 CPUState *cs = CPU(cpu);
655
656 cpu_reset(cs);
657
658
659
660 cs->halted = 1;
661 cs->exception_index = EXCP_HLT;
662}
663
664static void ppce500_cpu_reset(void *opaque)
665{
666 PowerPCCPU *cpu = opaque;
667 CPUState *cs = CPU(cpu);
668 CPUPPCState *env = &cpu->env;
669 struct boot_info *bi = env->load_info;
670
671 cpu_reset(cs);
672
673
674 cs->halted = 0;
675 env->gpr[1] = (16 * MiB) - 8;
676 env->gpr[3] = bi->dt_base;
677 env->gpr[4] = 0;
678 env->gpr[5] = 0;
679 env->gpr[6] = EPAPR_MAGIC;
680 env->gpr[7] = mmubooke_initial_mapsize(env);
681 env->gpr[8] = 0;
682 env->gpr[9] = 0;
683 env->nip = bi->entry;
684 mmubooke_create_initial_mapping(env);
685}
686
687static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
688 qemu_irq **irqs)
689{
690 DeviceState *dev;
691 SysBusDevice *s;
692 int i, j, k;
693 MachineState *machine = MACHINE(pms);
694 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
695
696 dev = qdev_create(NULL, TYPE_OPENPIC);
697 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev),
698 &error_fatal);
699 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
700 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
701
702 qdev_init_nofail(dev);
703 s = SYS_BUS_DEVICE(dev);
704
705 k = 0;
706 for (i = 0; i < smp_cpus; i++) {
707 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
708 sysbus_connect_irq(s, k++, irqs[i][j]);
709 }
710 }
711
712 return dev;
713}
714
715static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
716 qemu_irq **irqs, Error **errp)
717{
718 Error *err = NULL;
719 DeviceState *dev;
720 CPUState *cs;
721
722 dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
723 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
724
725 object_property_set_bool(OBJECT(dev), true, "realized", &err);
726 if (err) {
727 error_propagate(errp, err);
728 object_unparent(OBJECT(dev));
729 return NULL;
730 }
731
732 CPU_FOREACH(cs) {
733 if (kvm_openpic_connect_vcpu(dev, cs)) {
734 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
735 __func__);
736 abort();
737 }
738 }
739
740 return dev;
741}
742
743static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
744 MemoryRegion *ccsr,
745 qemu_irq **irqs)
746{
747 MachineState *machine = MACHINE(pms);
748 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
749 DeviceState *dev = NULL;
750 SysBusDevice *s;
751
752 if (kvm_enabled()) {
753 Error *err = NULL;
754
755 if (machine_kernel_irqchip_allowed(machine)) {
756 dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
757 }
758 if (machine_kernel_irqchip_required(machine) && !dev) {
759 error_reportf_err(err,
760 "kernel_irqchip requested but unavailable: ");
761 exit(1);
762 }
763 }
764
765 if (!dev) {
766 dev = ppce500_init_mpic_qemu(pms, irqs);
767 }
768
769 s = SYS_BUS_DEVICE(dev);
770 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
771 s->mmio[0].memory);
772
773 return dev;
774}
775
776static void ppce500_power_off(void *opaque, int line, int on)
777{
778 if (on) {
779 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
780 }
781}
782
783void ppce500_init(MachineState *machine)
784{
785 MemoryRegion *address_space_mem = get_system_memory();
786 MemoryRegion *ram = g_new(MemoryRegion, 1);
787 PPCE500MachineState *pms = PPCE500_MACHINE(machine);
788 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
789 PCIBus *pci_bus;
790 CPUPPCState *env = NULL;
791 uint64_t loadaddr;
792 hwaddr kernel_base = -1LL;
793 int kernel_size = 0;
794 hwaddr dt_base = 0;
795 hwaddr initrd_base = 0;
796 int initrd_size = 0;
797 hwaddr cur_base = 0;
798 char *filename;
799 const char *payload_name;
800 bool kernel_as_payload;
801 hwaddr bios_entry = 0;
802 target_long payload_size;
803 struct boot_info *boot_info;
804 int dt_size;
805 int i;
806
807
808 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
809 qemu_irq **irqs;
810 DeviceState *dev, *mpicdev;
811 CPUPPCState *firstenv = NULL;
812 MemoryRegion *ccsr_addr_space;
813 SysBusDevice *s;
814 PPCE500CCSRState *ccsr;
815
816 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
817 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
818 for (i = 0; i < smp_cpus; i++) {
819 PowerPCCPU *cpu;
820 CPUState *cs;
821 qemu_irq *input;
822
823 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
824 env = &cpu->env;
825 cs = CPU(cpu);
826
827 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
828 error_report("MMU model %i not supported by this machine",
829 env->mmu_model);
830 exit(1);
831 }
832
833 if (!firstenv) {
834 firstenv = env;
835 }
836
837 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
838 input = (qemu_irq *)env->irq_inputs;
839 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
840 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
841 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
842 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
843
844 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
845
846
847 if (!i) {
848
849 struct boot_info *boot_info;
850 boot_info = g_malloc0(sizeof(struct boot_info));
851 qemu_register_reset(ppce500_cpu_reset, cpu);
852 env->load_info = boot_info;
853 } else {
854
855 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
856 }
857 }
858
859 env = firstenv;
860
861
862 ram_size &= ~(RAM_SIZES_ALIGN - 1);
863 machine->ram_size = ram_size;
864
865
866 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
867 memory_region_add_subregion(address_space_mem, 0, ram);
868
869 dev = qdev_create(NULL, "e500-ccsr");
870 object_property_add_child(qdev_get_machine(), "e500-ccsr",
871 OBJECT(dev), NULL);
872 qdev_init_nofail(dev);
873 ccsr = CCSR(dev);
874 ccsr_addr_space = &ccsr->ccsr_space;
875 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
876 ccsr_addr_space);
877
878 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
879
880
881 if (serial_hd(0)) {
882 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
883 0, qdev_get_gpio_in(mpicdev, 42), 399193,
884 serial_hd(0), DEVICE_BIG_ENDIAN);
885 }
886
887 if (serial_hd(1)) {
888 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
889 0, qdev_get_gpio_in(mpicdev, 42), 399193,
890 serial_hd(1), DEVICE_BIG_ENDIAN);
891 }
892
893
894 dev = qdev_create(NULL, "mpc8544-guts");
895 qdev_init_nofail(dev);
896 s = SYS_BUS_DEVICE(dev);
897 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
898 sysbus_mmio_get_region(s, 0));
899
900
901 dev = qdev_create(NULL, "e500-pcihost");
902 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
903 &error_abort);
904 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
905 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
906 qdev_init_nofail(dev);
907 s = SYS_BUS_DEVICE(dev);
908 for (i = 0; i < PCI_NUM_PINS; i++) {
909 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
910 }
911
912 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
913 sysbus_mmio_get_region(s, 0));
914
915 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
916 if (!pci_bus)
917 printf("couldn't create PCI controller!\n");
918
919 if (pci_bus) {
920
921 for (i = 0; i < nb_nics; i++) {
922 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL);
923 }
924 }
925
926
927 sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
928
929 if (pmc->has_mpc8xxx_gpio) {
930 qemu_irq poweroff_irq;
931
932 dev = qdev_create(NULL, "mpc8xxx_gpio");
933 s = SYS_BUS_DEVICE(dev);
934 qdev_init_nofail(dev);
935 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
936 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
937 sysbus_mmio_get_region(s, 0));
938
939
940 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
941 qdev_connect_gpio_out(dev, 0, poweroff_irq);
942 }
943
944
945 if (pmc->has_platform_bus) {
946 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
947 dev->id = TYPE_PLATFORM_BUS_DEVICE;
948 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
949 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
950 qdev_init_nofail(dev);
951 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
952
953 s = SYS_BUS_DEVICE(pms->pbus_dev);
954 for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
955 int irqn = pmc->platform_bus_first_irq + i;
956 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
957 }
958
959 memory_region_add_subregion(address_space_mem,
960 pmc->platform_bus_base,
961 sysbus_mmio_get_region(s, 0));
962 }
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979 kernel_as_payload = false;
980 if (bios_name == NULL) {
981 if (machine->kernel_filename) {
982 payload_name = machine->kernel_filename;
983 kernel_as_payload = true;
984 } else {
985 payload_name = "u-boot.e500";
986 }
987 } else {
988 payload_name = bios_name;
989 }
990
991 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
992
993 payload_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL,
994 1, PPC_ELF_MACHINE, 0, 0);
995 if (payload_size < 0) {
996
997
998
999
1000 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1001 NULL, NULL);
1002 if (payload_size < 0) {
1003 error_report("could not load firmware '%s'", filename);
1004 exit(1);
1005 }
1006 }
1007
1008 g_free(filename);
1009
1010 if (kernel_as_payload) {
1011 kernel_base = loadaddr;
1012 kernel_size = payload_size;
1013 }
1014
1015 cur_base = loadaddr + payload_size;
1016 if (cur_base < 32 * MiB) {
1017
1018 cur_base = 32 * MiB;
1019 }
1020
1021
1022 if (machine->kernel_filename && !kernel_as_payload) {
1023 kernel_base = cur_base;
1024 kernel_size = load_image_targphys(machine->kernel_filename,
1025 cur_base,
1026 ram_size - cur_base);
1027 if (kernel_size < 0) {
1028 error_report("could not load kernel '%s'",
1029 machine->kernel_filename);
1030 exit(1);
1031 }
1032
1033 cur_base += kernel_size;
1034 }
1035
1036
1037 if (machine->initrd_filename) {
1038 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1039 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1040 ram_size - initrd_base);
1041
1042 if (initrd_size < 0) {
1043 error_report("could not load initial ram disk '%s'",
1044 machine->initrd_filename);
1045 exit(1);
1046 }
1047
1048 cur_base = initrd_base + initrd_size;
1049 }
1050
1051
1052
1053
1054
1055
1056
1057 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1058 if (dt_base + DTB_MAX_SIZE > ram_size) {
1059 error_report("not enough memory for device tree");
1060 exit(1);
1061 }
1062
1063 dt_size = ppce500_prep_device_tree(pms, dt_base,
1064 initrd_base, initrd_size,
1065 kernel_base, kernel_size);
1066 if (dt_size < 0) {
1067 error_report("couldn't load device tree");
1068 exit(1);
1069 }
1070 assert(dt_size < DTB_MAX_SIZE);
1071
1072 boot_info = env->load_info;
1073 boot_info->entry = bios_entry;
1074 boot_info->dt_base = dt_base;
1075 boot_info->dt_size = dt_size;
1076}
1077
1078static void e500_ccsr_initfn(Object *obj)
1079{
1080 PPCE500CCSRState *ccsr = CCSR(obj);
1081 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1082 MPC8544_CCSRBAR_SIZE);
1083}
1084
1085static const TypeInfo e500_ccsr_info = {
1086 .name = TYPE_CCSR,
1087 .parent = TYPE_SYS_BUS_DEVICE,
1088 .instance_size = sizeof(PPCE500CCSRState),
1089 .instance_init = e500_ccsr_initfn,
1090};
1091
1092static const TypeInfo ppce500_info = {
1093 .name = TYPE_PPCE500_MACHINE,
1094 .parent = TYPE_MACHINE,
1095 .abstract = true,
1096 .instance_size = sizeof(PPCE500MachineState),
1097 .class_size = sizeof(PPCE500MachineClass),
1098};
1099
1100static void e500_register_types(void)
1101{
1102 type_register_static(&e500_ccsr_info);
1103 type_register_static(&ppce500_info);
1104}
1105
1106type_init(e500_register_types)
1107