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19#include "qemu/osdep.h"
20#include "sysemu/sysemu.h"
21#include "qapi/error.h"
22#include "qemu/log.h"
23#include "target/ppc/cpu.h"
24#include "hw/ppc/ppc.h"
25#include "hw/ppc/pnv.h"
26#include "hw/ppc/pnv_core.h"
27#include "hw/ppc/pnv_xscom.h"
28#include "hw/ppc/xics.h"
29
30static const char *pnv_core_cpu_typename(PnvCore *pc)
31{
32 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
33 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
34 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
35 const char *cpu_type = object_class_get_name(object_class_by_name(s));
36 g_free(s);
37 return cpu_type;
38}
39
40static void pnv_cpu_reset(void *opaque)
41{
42 PowerPCCPU *cpu = opaque;
43 CPUState *cs = CPU(cpu);
44 CPUPPCState *env = &cpu->env;
45
46 cpu_reset(cs);
47
48
49
50
51
52 env->gpr[3] = PNV_FDT_ADDR;
53 env->nip = 0x10;
54 env->msr |= MSR_HVB;
55}
56
57
58
59
60#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
61#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
62
63static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
64 unsigned int width)
65{
66 uint32_t offset = addr >> 3;
67 uint64_t val = 0;
68
69
70 switch (offset) {
71 case PNV_XSCOM_EX_DTS_RESULT0:
72 val = 0x26f024f023f0000ull;
73 break;
74 case PNV_XSCOM_EX_DTS_RESULT1:
75 val = 0x24f000000000000ull;
76 break;
77 default:
78 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
79 addr);
80 }
81
82 return val;
83}
84
85static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
86 unsigned int width)
87{
88 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
89 addr);
90}
91
92static const MemoryRegionOps pnv_core_xscom_ops = {
93 .read = pnv_core_xscom_read,
94 .write = pnv_core_xscom_write,
95 .valid.min_access_size = 8,
96 .valid.max_access_size = 8,
97 .impl.min_access_size = 8,
98 .impl.max_access_size = 8,
99 .endianness = DEVICE_BIG_ENDIAN,
100};
101
102static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
103{
104 CPUPPCState *env = &cpu->env;
105 int core_pir;
106 int thread_index = 0;
107 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
108 Error *local_err = NULL;
109 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
110
111 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
112 if (local_err) {
113 error_propagate(errp, local_err);
114 return;
115 }
116
117 cpu->intc = pcc->intc_create(chip, OBJECT(cpu), &local_err);
118 if (local_err) {
119 error_propagate(errp, local_err);
120 return;
121 }
122
123 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
124
125
126
127
128
129
130 pir->default_value = core_pir + thread_index;
131
132
133 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
134
135 qemu_register_reset(pnv_cpu_reset, cpu);
136}
137
138static void pnv_core_realize(DeviceState *dev, Error **errp)
139{
140 PnvCore *pc = PNV_CORE(OBJECT(dev));
141 CPUCore *cc = CPU_CORE(OBJECT(dev));
142 const char *typename = pnv_core_cpu_typename(pc);
143 Error *local_err = NULL;
144 void *obj;
145 int i, j;
146 char name[32];
147 Object *chip;
148
149 chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
150 if (!chip) {
151 error_propagate_prepend(errp, local_err,
152 "required link 'chip' not found: ");
153 return;
154 }
155
156 pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
157 for (i = 0; i < cc->nr_threads; i++) {
158 obj = object_new(typename);
159
160 pc->threads[i] = POWERPC_CPU(obj);
161
162 snprintf(name, sizeof(name), "thread[%d]", i);
163 object_property_add_child(OBJECT(pc), name, obj, &error_abort);
164 object_property_add_alias(obj, "core-pir", OBJECT(pc),
165 "pir", &error_abort);
166 object_unref(obj);
167 }
168
169 for (j = 0; j < cc->nr_threads; j++) {
170 pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
171 if (local_err) {
172 goto err;
173 }
174 }
175
176 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
177 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
178 pc, name, PNV_XSCOM_EX_SIZE);
179 return;
180
181err:
182 while (--i >= 0) {
183 obj = OBJECT(pc->threads[i]);
184 object_unparent(obj);
185 }
186 g_free(pc->threads);
187 error_propagate(errp, local_err);
188}
189
190static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
191{
192 qemu_unregister_reset(pnv_cpu_reset, cpu);
193 object_unparent(cpu->intc);
194 cpu_remove_sync(CPU(cpu));
195 object_unparent(OBJECT(cpu));
196}
197
198static void pnv_core_unrealize(DeviceState *dev, Error **errp)
199{
200 PnvCore *pc = PNV_CORE(dev);
201 CPUCore *cc = CPU_CORE(dev);
202 int i;
203
204 for (i = 0; i < cc->nr_threads; i++) {
205 pnv_unrealize_vcpu(pc->threads[i]);
206 }
207 g_free(pc->threads);
208}
209
210static Property pnv_core_properties[] = {
211 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
212 DEFINE_PROP_END_OF_LIST(),
213};
214
215static void pnv_core_class_init(ObjectClass *oc, void *data)
216{
217 DeviceClass *dc = DEVICE_CLASS(oc);
218
219 dc->realize = pnv_core_realize;
220 dc->unrealize = pnv_core_unrealize;
221 dc->props = pnv_core_properties;
222}
223
224#define DEFINE_PNV_CORE_TYPE(cpu_model) \
225 { \
226 .parent = TYPE_PNV_CORE, \
227 .name = PNV_CORE_TYPE_NAME(cpu_model), \
228 }
229
230static const TypeInfo pnv_core_infos[] = {
231 {
232 .name = TYPE_PNV_CORE,
233 .parent = TYPE_CPU_CORE,
234 .instance_size = sizeof(PnvCore),
235 .class_size = sizeof(PnvCoreClass),
236 .class_init = pnv_core_class_init,
237 .abstract = true,
238 },
239 DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
240 DEFINE_PNV_CORE_TYPE("power8_v2.0"),
241 DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
242 DEFINE_PNV_CORE_TYPE("power9_v2.0"),
243};
244
245DEFINE_TYPES(pnv_core_infos)
246
