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25#include "qemu/osdep.h"
26#include "cpu.h"
27#include "hw/hw.h"
28#include "hw/timer/m48t59.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/block/fdc.h"
32#include "net/net.h"
33#include "sysemu/sysemu.h"
34#include "hw/isa/isa.h"
35#include "hw/pci/pci.h"
36#include "hw/pci/pci_host.h"
37#include "hw/ppc/ppc.h"
38#include "hw/boards.h"
39#include "qemu/error-report.h"
40#include "qemu/log.h"
41#include "hw/ide.h"
42#include "hw/loader.h"
43#include "hw/timer/mc146818rtc.h"
44#include "hw/input/i8042.h"
45#include "hw/isa/pc87312.h"
46#include "hw/net/ne2000-isa.h"
47#include "sysemu/arch_init.h"
48#include "sysemu/kvm.h"
49#include "sysemu/qtest.h"
50#include "exec/address-spaces.h"
51#include "trace.h"
52#include "elf.h"
53#include "qemu/units.h"
54#include "kvm_ppc.h"
55
56
57#define MAX_CPUS 1
58
59#define MAX_IDE_BUS 2
60
61#define CFG_ADDR 0xf0000510
62
63#define BIOS_SIZE (1 * MiB)
64#define BIOS_FILENAME "ppc_rom.bin"
65#define KERNEL_LOAD_ADDR 0x01000000
66#define INITRD_LOAD_ADDR 0x01800000
67
68
69static const int ide_iobase[2] = { 0x1f0, 0x170 };
70static const int ide_iobase2[2] = { 0x3f6, 0x376 };
71static const int ide_irq[2] = { 13, 13 };
72
73#define NE2000_NB_MAX 6
74
75static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
76static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
77
78
79#define PPC_IO_BASE 0x80000000
80
81
82typedef struct sysctrl_t {
83 qemu_irq reset_irq;
84 Nvram *nvram;
85 uint8_t state;
86 uint8_t syscontrol;
87 int contiguous_map;
88 qemu_irq contiguous_map_irq;
89 int endian;
90} sysctrl_t;
91
92enum {
93 STATE_HARDFILE = 0x01,
94};
95
96static sysctrl_t *sysctrl;
97
98static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
99{
100 sysctrl_t *sysctrl = opaque;
101
102 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
103 switch (addr) {
104 case 0x0092:
105
106
107 if (val & 0x01) {
108 qemu_irq_raise(sysctrl->reset_irq);
109 } else {
110 qemu_irq_lower(sysctrl->reset_irq);
111 }
112
113 if (val & 0x02) {
114 sysctrl->endian = 1;
115 } else {
116 sysctrl->endian = 0;
117 }
118 break;
119 case 0x0800:
120
121 break;
122 case 0x0802:
123
124 break;
125 case 0x0803:
126
127 break;
128 case 0x0808:
129
130 if (val & 1)
131 sysctrl->state |= STATE_HARDFILE;
132 else
133 sysctrl->state &= ~STATE_HARDFILE;
134 break;
135 case 0x0810:
136
137 if (sysctrl->nvram != NULL) {
138 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
139 (k->toggle_lock)(sysctrl->nvram, 1);
140 }
141 break;
142 case 0x0812:
143
144 if (sysctrl->nvram != NULL) {
145 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
146 (k->toggle_lock)(sysctrl->nvram, 2);
147 }
148 break;
149 case 0x0814:
150
151
152 break;
153 case 0x081C:
154
155 sysctrl->syscontrol = val & 0x0F;
156 break;
157 case 0x0850:
158
159 sysctrl->contiguous_map = val & 0x01;
160 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
161 break;
162 default:
163 printf("ERROR: unaffected IO port write: %04" PRIx32
164 " => %02" PRIx32"\n", addr, val);
165 break;
166 }
167}
168
169static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
170{
171 sysctrl_t *sysctrl = opaque;
172 uint32_t retval = 0xFF;
173
174 switch (addr) {
175 case 0x0092:
176
177 retval = sysctrl->endian << 1;
178 break;
179 case 0x0800:
180
181 retval = 0xEF;
182 break;
183 case 0x0802:
184
185 retval = 0xAD;
186 break;
187 case 0x0803:
188
189 retval = 0xE0;
190 break;
191 case 0x080C:
192
193
194
195
196
197
198 retval = 0x3C;
199 break;
200 case 0x0810:
201
202 retval = 0x39;
203 break;
204 case 0x0814:
205
206 break;
207 case 0x0818:
208
209 retval = 0x00;
210 break;
211 case 0x081C:
212
213
214
215 retval = sysctrl->syscontrol;
216 break;
217 case 0x0823:
218
219 retval = 0x03;
220 break;
221 case 0x0850:
222
223 retval = sysctrl->contiguous_map;
224 break;
225 default:
226 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
227 break;
228 }
229 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
230
231 return retval;
232}
233
234
235#define NVRAM_SIZE 0x2000
236
237static void fw_cfg_boot_set(void *opaque, const char *boot_device,
238 Error **errp)
239{
240 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
241}
242
243static void ppc_prep_reset(void *opaque)
244{
245 PowerPCCPU *cpu = opaque;
246
247 cpu_reset(CPU(cpu));
248}
249
250static const MemoryRegionPortio prep_portio_list[] = {
251
252 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
253 { 0x0800, 0x52, 1,
254 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
255
256 { 0x0F00, 4, 1, .write = PPC_debug_write, },
257 PORTIO_END_OF_LIST(),
258};
259
260static PortioList prep_port_list;
261
262
263
264static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
265{
266 NvramClass *k = NVRAM_GET_CLASS(nvram);
267 return (k->read)(nvram, addr);
268}
269
270static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
271{
272 NvramClass *k = NVRAM_GET_CLASS(nvram);
273 (k->write)(nvram, addr, val);
274}
275
276static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
277{
278 nvram_write(nvram, addr, value);
279}
280
281static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
282{
283 return nvram_read(nvram, addr);
284}
285
286static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
287{
288 nvram_write(nvram, addr, value >> 8);
289 nvram_write(nvram, addr + 1, value & 0xFF);
290}
291
292static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
293{
294 uint16_t tmp;
295
296 tmp = nvram_read(nvram, addr) << 8;
297 tmp |= nvram_read(nvram, addr + 1);
298
299 return tmp;
300}
301
302static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
303{
304 nvram_write(nvram, addr, value >> 24);
305 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
306 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
307 nvram_write(nvram, addr + 3, value & 0xFF);
308}
309
310static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
311 uint32_t max)
312{
313 int i;
314
315 for (i = 0; i < max && str[i] != '\0'; i++) {
316 nvram_write(nvram, addr + i, str[i]);
317 }
318 nvram_write(nvram, addr + i, str[i]);
319 nvram_write(nvram, addr + max - 1, '\0');
320}
321
322static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
323{
324 uint16_t tmp;
325 uint16_t pd, pd1, pd2;
326
327 tmp = prev >> 8;
328 pd = prev ^ value;
329 pd1 = pd & 0x000F;
330 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
331 tmp ^= (pd1 << 3) | (pd1 << 8);
332 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
333
334 return tmp;
335}
336
337static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
338{
339 uint32_t i;
340 uint16_t crc = 0xFFFF;
341 int odd;
342
343 odd = count & 1;
344 count &= ~1;
345 for (i = 0; i != count; i++) {
346 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
347 }
348 if (odd) {
349 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
350 }
351
352 return crc;
353}
354
355#define CMDLINE_ADDR 0x017ff000
356
357static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
358 const char *arch,
359 uint32_t RAM_size, int boot_device,
360 uint32_t kernel_image, uint32_t kernel_size,
361 const char *cmdline,
362 uint32_t initrd_image, uint32_t initrd_size,
363 uint32_t NVRAM_image,
364 int width, int height, int depth)
365{
366 uint16_t crc;
367
368
369 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
370 NVRAM_set_lword(nvram, 0x10, 0x00000002);
371 NVRAM_set_word(nvram, 0x14, NVRAM_size);
372 NVRAM_set_string(nvram, 0x20, arch, 16);
373 NVRAM_set_lword(nvram, 0x30, RAM_size);
374 NVRAM_set_byte(nvram, 0x34, boot_device);
375 NVRAM_set_lword(nvram, 0x38, kernel_image);
376 NVRAM_set_lword(nvram, 0x3C, kernel_size);
377 if (cmdline) {
378
379 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
380 cmdline);
381 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
382 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
383 } else {
384 NVRAM_set_lword(nvram, 0x40, 0);
385 NVRAM_set_lword(nvram, 0x44, 0);
386 }
387 NVRAM_set_lword(nvram, 0x48, initrd_image);
388 NVRAM_set_lword(nvram, 0x4C, initrd_size);
389 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
390
391 NVRAM_set_word(nvram, 0x54, width);
392 NVRAM_set_word(nvram, 0x56, height);
393 NVRAM_set_word(nvram, 0x58, depth);
394 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
395 NVRAM_set_word(nvram, 0xFC, crc);
396
397 return 0;
398}
399
400
401static void ppc_prep_init(MachineState *machine)
402{
403 ram_addr_t ram_size = machine->ram_size;
404 const char *kernel_filename = machine->kernel_filename;
405 const char *kernel_cmdline = machine->kernel_cmdline;
406 const char *initrd_filename = machine->initrd_filename;
407 const char *boot_device = machine->boot_order;
408 MemoryRegion *sysmem = get_system_memory();
409 PowerPCCPU *cpu = NULL;
410 CPUPPCState *env = NULL;
411 Nvram *m48t59;
412#if 0
413 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
414#endif
415 int linux_boot, i, nb_nics1;
416 MemoryRegion *ram = g_new(MemoryRegion, 1);
417 uint32_t kernel_base, initrd_base;
418 long kernel_size, initrd_size;
419 DeviceState *dev;
420 PCIHostState *pcihost;
421 PCIBus *pci_bus;
422 PCIDevice *pci;
423 ISABus *isa_bus;
424 ISADevice *isa;
425 int ppc_boot_device;
426 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
427
428 sysctrl = g_malloc0(sizeof(sysctrl_t));
429
430 linux_boot = (kernel_filename != NULL);
431
432
433 for (i = 0; i < smp_cpus; i++) {
434 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
435 env = &cpu->env;
436
437 if (env->flags & POWERPC_FLAG_RTC_CLK) {
438
439 cpu_ppc_tb_init(env, 7812500UL);
440 } else {
441
442 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
443 }
444 qemu_register_reset(ppc_prep_reset, cpu);
445 }
446
447
448 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
449 memory_region_add_subregion(sysmem, 0, ram);
450
451 if (linux_boot) {
452 kernel_base = KERNEL_LOAD_ADDR;
453
454 kernel_size = load_image_targphys(kernel_filename, kernel_base,
455 ram_size - kernel_base);
456 if (kernel_size < 0) {
457 error_report("could not load kernel '%s'", kernel_filename);
458 exit(1);
459 }
460
461 if (initrd_filename) {
462 initrd_base = INITRD_LOAD_ADDR;
463 initrd_size = load_image_targphys(initrd_filename, initrd_base,
464 ram_size - initrd_base);
465 if (initrd_size < 0) {
466 error_report("could not load initial ram disk '%s'",
467 initrd_filename);
468 exit(1);
469 }
470 } else {
471 initrd_base = 0;
472 initrd_size = 0;
473 }
474 ppc_boot_device = 'm';
475 } else {
476 kernel_base = 0;
477 kernel_size = 0;
478 initrd_base = 0;
479 initrd_size = 0;
480 ppc_boot_device = '\0';
481
482 for (i = 0; boot_device[i] != '\0'; i++) {
483 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
484 ppc_boot_device = boot_device[i];
485 break;
486 }
487 }
488 if (ppc_boot_device == '\0') {
489 error_report("No valid boot device for Mac99 machine");
490 exit(1);
491 }
492 }
493
494 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
495 error_report("Only 6xx bus is supported on PREP machine");
496 exit(1);
497 }
498
499 dev = qdev_create(NULL, "raven-pcihost");
500 if (bios_name == NULL) {
501 bios_name = BIOS_FILENAME;
502 }
503 qdev_prop_set_string(dev, "bios-name", bios_name);
504 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
505 qdev_prop_set_bit(dev, "is-legacy-prep", true);
506 pcihost = PCI_HOST_BRIDGE(dev);
507 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
508 qdev_init_nofail(dev);
509 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
510 if (pci_bus == NULL) {
511 error_report("Couldn't create PCI host controller");
512 exit(1);
513 }
514 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
515
516
517 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
518 cpu = POWERPC_CPU(first_cpu);
519 qdev_connect_gpio_out(&pci->qdev, 0,
520 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
521 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
522 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
523 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
524 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
525 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
526
527
528 isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
529 dev = DEVICE(isa);
530 qdev_prop_set_uint8(dev, "config", 13);
531 qdev_init_nofail(dev);
532
533
534 pci_vga_init(pci_bus);
535
536 nb_nics1 = nb_nics;
537 if (nb_nics1 > NE2000_NB_MAX)
538 nb_nics1 = NE2000_NB_MAX;
539 for(i = 0; i < nb_nics1; i++) {
540 if (nd_table[i].model == NULL) {
541 nd_table[i].model = g_strdup("ne2k_isa");
542 }
543 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
544 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
545 &nd_table[i]);
546 } else {
547 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
548 }
549 }
550
551 ide_drive_get(hd, ARRAY_SIZE(hd));
552 for(i = 0; i < MAX_IDE_BUS; i++) {
553 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
554 hd[2 * i],
555 hd[2 * i + 1]);
556 }
557
558 cpu = POWERPC_CPU(first_cpu);
559 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
560
561 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
562 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
563
564
565
566
567
568
569 if (machine_usb(machine)) {
570 pci_create_simple(pci_bus, -1, "pci-ohci");
571 }
572
573 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
574 if (m48t59 == NULL)
575 return;
576 sysctrl->nvram = m48t59;
577
578
579 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
580 ppc_boot_device,
581 kernel_base, kernel_size,
582 kernel_cmdline,
583 initrd_base, initrd_size,
584
585 0,
586 graphic_width, graphic_height, graphic_depth);
587}
588
589static void prep_machine_init(MachineClass *mc)
590{
591 mc->deprecation_reason = "use 40p machine type instead";
592 mc->desc = "PowerPC PREP platform";
593 mc->init = ppc_prep_init;
594 mc->block_default_type = IF_IDE;
595 mc->max_cpus = MAX_CPUS;
596 mc->default_boot_order = "cad";
597 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
598 mc->default_display = "std";
599}
600
601static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
602{
603 uint16_t checksum = *(uint16_t *)opaque;
604 ISADevice *rtc;
605
606 if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
607 rtc = ISA_DEVICE(dev);
608 rtc_set_memory(rtc, 0x2e, checksum & 0xff);
609 rtc_set_memory(rtc, 0x3e, checksum & 0xff);
610 rtc_set_memory(rtc, 0x2f, checksum >> 8);
611 rtc_set_memory(rtc, 0x3f, checksum >> 8);
612
613 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
614 "date", NULL);
615 }
616 return 0;
617}
618
619static void ibm_40p_init(MachineState *machine)
620{
621 CPUPPCState *env = NULL;
622 uint16_t cmos_checksum;
623 PowerPCCPU *cpu;
624 DeviceState *dev, *i82378_dev;
625 SysBusDevice *pcihost, *s;
626 Nvram *m48t59 = NULL;
627 PCIBus *pci_bus;
628 ISABus *isa_bus;
629 void *fw_cfg;
630 int i;
631 uint32_t kernel_base = 0, initrd_base = 0;
632 long kernel_size = 0, initrd_size = 0;
633 char boot_device;
634
635
636 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
637 env = &cpu->env;
638 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
639 error_report("only 6xx bus is supported on this machine");
640 exit(1);
641 }
642
643 if (env->flags & POWERPC_FLAG_RTC_CLK) {
644
645 cpu_ppc_tb_init(env, 7812500UL);
646 } else {
647
648 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
649 }
650 qemu_register_reset(ppc_prep_reset, cpu);
651
652
653 dev = qdev_create(NULL, "raven-pcihost");
654 if (!bios_name) {
655 bios_name = "openbios-ppc";
656 }
657 qdev_prop_set_string(dev, "bios-name", bios_name);
658 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
659 pcihost = SYS_BUS_DEVICE(dev);
660 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
661 qdev_init_nofail(dev);
662 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
663 if (!pci_bus) {
664 error_report("could not create PCI host controller");
665 exit(1);
666 }
667
668
669 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
670 qdev_connect_gpio_out(i82378_dev, 0,
671 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
672 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
673 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
674
675
676 dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
677 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
678 qdev_init_nofail(dev);
679
680
681 cmos_checksum = 0x6aa9;
682 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
683 &cmos_checksum);
684
685
686 if (defaults_enabled()) {
687 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
688
689 dev = DEVICE(isa_create(isa_bus, "cs4231a"));
690 qdev_prop_set_uint32(dev, "iobase", 0x830);
691 qdev_prop_set_uint32(dev, "irq", 10);
692 qdev_init_nofail(dev);
693
694 dev = DEVICE(isa_create(isa_bus, "pc87312"));
695 qdev_prop_set_uint32(dev, "config", 12);
696 qdev_init_nofail(dev);
697
698 dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
699 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
700 qdev_prop_set_uint32(dev, "equipment", 0xc0);
701 qdev_init_nofail(dev);
702
703 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
704 "lsi53c810"));
705 lsi53c8xx_handle_legacy_cmdline(dev);
706 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
707
708
709 pci_vga_init(pci_bus);
710
711 for (i = 0; i < nb_nics; i++) {
712 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
713 i == 0 ? "3" : NULL);
714 }
715 }
716
717
718 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
719 fw_cfg = FW_CFG(dev);
720 qdev_prop_set_uint32(dev, "data_width", 1);
721 qdev_prop_set_bit(dev, "dma_enabled", false);
722 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
723 OBJECT(fw_cfg), NULL);
724 qdev_init_nofail(dev);
725 s = SYS_BUS_DEVICE(dev);
726 sysbus_mmio_map(s, 0, CFG_ADDR);
727 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
728
729 if (machine->kernel_filename) {
730
731 kernel_base = KERNEL_LOAD_ADDR;
732 kernel_size = load_image_targphys(machine->kernel_filename,
733 kernel_base,
734 machine->ram_size - kernel_base);
735 if (kernel_size < 0) {
736 error_report("could not load kernel '%s'",
737 machine->kernel_filename);
738 exit(1);
739 }
740 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
741 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
742
743 if (machine->initrd_filename) {
744 initrd_base = INITRD_LOAD_ADDR;
745 initrd_size = load_image_targphys(machine->initrd_filename,
746 initrd_base,
747 machine->ram_size - initrd_base);
748 if (initrd_size < 0) {
749 error_report("could not load initial ram disk '%s'",
750 machine->initrd_filename);
751 exit(1);
752 }
753 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
754 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
755 }
756 if (machine->kernel_cmdline && *machine->kernel_cmdline) {
757 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
758 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
759 machine->kernel_cmdline);
760 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
761 machine->kernel_cmdline);
762 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
763 strlen(machine->kernel_cmdline) + 1);
764 }
765 boot_device = 'm';
766 } else {
767 boot_device = machine->boot_order[0];
768 }
769
770 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
771 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
772 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
773
774 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
775 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
776 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
777
778 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
779 if (kvm_enabled()) {
780#ifdef CONFIG_KVM
781 uint8_t *hypercall;
782
783 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
784 hypercall = g_malloc(16);
785 kvmppc_get_hypercall(env, hypercall, 16);
786 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
787 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
788#endif
789 } else {
790 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
791 }
792 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
793 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
794
795
796 if (m48t59) {
797 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
798 boot_device,
799 kernel_base, kernel_size,
800 machine->kernel_cmdline,
801 initrd_base, initrd_size,
802
803 0,
804 graphic_width, graphic_height, graphic_depth);
805 }
806}
807
808static void ibm_40p_machine_init(MachineClass *mc)
809{
810 mc->desc = "IBM RS/6000 7020 (40p)",
811 mc->init = ibm_40p_init;
812 mc->max_cpus = 1;
813 mc->default_ram_size = 128 * MiB;
814 mc->block_default_type = IF_SCSI;
815 mc->default_boot_order = "c";
816 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
817 mc->default_display = "std";
818}
819
820DEFINE_MACHINE("40p", ibm_40p_machine_init)
821DEFINE_MACHINE("prep", prep_machine_init)
822
