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27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "qapi/visitor.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/numa.h"
32#include "hw/hw.h"
33#include "qemu/log.h"
34#include "hw/fw-path-provider.h"
35#include "elf.h"
36#include "net/net.h"
37#include "sysemu/device_tree.h"
38#include "sysemu/cpus.h"
39#include "sysemu/hw_accel.h"
40#include "kvm_ppc.h"
41#include "migration/misc.h"
42#include "migration/global_state.h"
43#include "migration/register.h"
44#include "mmu-hash64.h"
45#include "mmu-book3s-v3.h"
46#include "cpu-models.h"
47#include "qom/cpu.h"
48
49#include "hw/boards.h"
50#include "hw/ppc/ppc.h"
51#include "hw/loader.h"
52
53#include "hw/ppc/fdt.h"
54#include "hw/ppc/spapr.h"
55#include "hw/ppc/spapr_vio.h"
56#include "hw/pci-host/spapr.h"
57#include "hw/pci/msi.h"
58
59#include "hw/pci/pci.h"
60#include "hw/scsi/scsi.h"
61#include "hw/virtio/virtio-scsi.h"
62#include "hw/virtio/vhost-scsi-common.h"
63
64#include "exec/address-spaces.h"
65#include "exec/ram_addr.h"
66#include "hw/usb.h"
67#include "qemu/config-file.h"
68#include "qemu/error-report.h"
69#include "trace.h"
70#include "hw/nmi.h"
71#include "hw/intc/intc.h"
72
73#include "hw/compat.h"
74#include "qemu/cutils.h"
75#include "hw/ppc/spapr_cpu_core.h"
76#include "hw/mem/memory-device.h"
77
78#include <libfdt.h>
79
80
81
82
83
84
85
86
87
88
89
90#define FDT_MAX_SIZE 0x100000
91#define RTAS_MAX_SIZE 0x10000
92#define RTAS_MAX_ADDR 0x80000000
93#define FW_MAX_SIZE 0x400000
94#define FW_FILE_NAME "slof.bin"
95#define FW_OVERHEAD 0x2800000
96#define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98#define MIN_RMA_SLOF 128UL
99
100#define PHANDLE_XICP 0x00001111
101
102
103
104
105
106static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
107{
108 assert(spapr->vsmt);
109 return
110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
111}
112static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
113 PowerPCCPU *cpu)
114{
115 assert(spapr->vsmt);
116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
117}
118
119static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
120{
121
122
123
124
125 return false;
126}
127
128static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
129 .name = "icp/server",
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .needed = pre_2_10_vmstate_dummy_icp_needed,
133 .fields = (VMStateField[]) {
134 VMSTATE_UNUSED(4),
135 VMSTATE_UNUSED(1),
136 VMSTATE_UNUSED(1),
137 VMSTATE_END_OF_LIST()
138 },
139};
140
141static void pre_2_10_vmstate_register_dummy_icp(int i)
142{
143 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
144 (void *)(uintptr_t) i);
145}
146
147static void pre_2_10_vmstate_unregister_dummy_icp(int i)
148{
149 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
150 (void *)(uintptr_t) i);
151}
152
153static int xics_max_server_number(sPAPRMachineState *spapr)
154{
155 assert(spapr->vsmt);
156 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
157}
158
159static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
160 int smt_threads)
161{
162 int i, ret = 0;
163 uint32_t servers_prop[smt_threads];
164 uint32_t gservers_prop[smt_threads * 2];
165 int index = spapr_get_vcpu_id(cpu);
166
167 if (cpu->compat_pvr) {
168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
169 if (ret < 0) {
170 return ret;
171 }
172 }
173
174
175 for (i = 0; i < smt_threads; i++) {
176 servers_prop[i] = cpu_to_be32(index + i);
177
178 gservers_prop[i*2] = cpu_to_be32(index + i);
179 gservers_prop[i*2 + 1] = 0;
180 }
181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
182 servers_prop, sizeof(servers_prop));
183 if (ret < 0) {
184 return ret;
185 }
186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
187 gservers_prop, sizeof(gservers_prop));
188
189 return ret;
190}
191
192static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
193{
194 int index = spapr_get_vcpu_id(cpu);
195 uint32_t associativity[] = {cpu_to_be32(0x5),
196 cpu_to_be32(0x0),
197 cpu_to_be32(0x0),
198 cpu_to_be32(0x0),
199 cpu_to_be32(cpu->node_id),
200 cpu_to_be32(index)};
201
202
203 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
204 sizeof(associativity));
205}
206
207
208static void spapr_populate_pa_features(sPAPRMachineState *spapr,
209 PowerPCCPU *cpu,
210 void *fdt, int offset,
211 bool legacy_guest)
212{
213 uint8_t pa_features_206[] = { 6, 0,
214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
215 uint8_t pa_features_207[] = { 24, 0,
216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
220 uint8_t pa_features_300[] = { 66, 0,
221
222
223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
224
225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
226
227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
228
229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
230
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
232
233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
234
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
236
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
238
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
240
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
242
243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
244 };
245 uint8_t *pa_features = NULL;
246 size_t pa_size;
247
248 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
249 pa_features = pa_features_206;
250 pa_size = sizeof(pa_features_206);
251 }
252 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
253 pa_features = pa_features_207;
254 pa_size = sizeof(pa_features_207);
255 }
256 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
257 pa_features = pa_features_300;
258 pa_size = sizeof(pa_features_300);
259 }
260 if (!pa_features) {
261 return;
262 }
263
264 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
265
266
267
268
269
270
271
272 pa_features[3] |= 0x20;
273 }
274 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
275 pa_features[24] |= 0x80;
276 }
277 if (legacy_guest && pa_size > 40) {
278
279
280
281 pa_features[40 + 2] &= ~0x80;
282 }
283
284 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
285}
286
287static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
288{
289 int ret = 0, offset, cpus_offset;
290 CPUState *cs;
291 char cpu_model[32];
292 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
293
294 CPU_FOREACH(cs) {
295 PowerPCCPU *cpu = POWERPC_CPU(cs);
296 DeviceClass *dc = DEVICE_GET_CLASS(cs);
297 int index = spapr_get_vcpu_id(cpu);
298 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
299
300 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
301 continue;
302 }
303
304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
305
306 cpus_offset = fdt_path_offset(fdt, "/cpus");
307 if (cpus_offset < 0) {
308 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
309 if (cpus_offset < 0) {
310 return cpus_offset;
311 }
312 }
313 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
314 if (offset < 0) {
315 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
316 if (offset < 0) {
317 return offset;
318 }
319 }
320
321 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
322 pft_size_prop, sizeof(pft_size_prop));
323 if (ret < 0) {
324 return ret;
325 }
326
327 if (nb_numa_nodes > 1) {
328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
329 if (ret < 0) {
330 return ret;
331 }
332 }
333
334 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
335 if (ret < 0) {
336 return ret;
337 }
338
339 spapr_populate_pa_features(spapr, cpu, fdt, offset,
340 spapr->cas_legacy_guest_workaround);
341 }
342 return ret;
343}
344
345static hwaddr spapr_node0_size(MachineState *machine)
346{
347 if (nb_numa_nodes) {
348 int i;
349 for (i = 0; i < nb_numa_nodes; ++i) {
350 if (numa_info[i].node_mem) {
351 return MIN(pow2floor(numa_info[i].node_mem),
352 machine->ram_size);
353 }
354 }
355 }
356 return machine->ram_size;
357}
358
359static void add_str(GString *s, const gchar *s1)
360{
361 g_string_append_len(s, s1, strlen(s1) + 1);
362}
363
364static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
365 hwaddr size)
366{
367 uint32_t associativity[] = {
368 cpu_to_be32(0x4),
369 cpu_to_be32(0x0), cpu_to_be32(0x0),
370 cpu_to_be32(0x0), cpu_to_be32(nodeid)
371 };
372 char mem_name[32];
373 uint64_t mem_reg_property[2];
374 int off;
375
376 mem_reg_property[0] = cpu_to_be64(start);
377 mem_reg_property[1] = cpu_to_be64(size);
378
379 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
380 off = fdt_add_subnode(fdt, 0, mem_name);
381 _FDT(off);
382 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
383 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
384 sizeof(mem_reg_property))));
385 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
386 sizeof(associativity))));
387 return off;
388}
389
390static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
391{
392 MachineState *machine = MACHINE(spapr);
393 hwaddr mem_start, node_size;
394 int i, nb_nodes = nb_numa_nodes;
395 NodeInfo *nodes = numa_info;
396 NodeInfo ramnode;
397
398
399 if (!nb_numa_nodes) {
400 nb_nodes = 1;
401 ramnode.node_mem = machine->ram_size;
402 nodes = &ramnode;
403 }
404
405 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
406 if (!nodes[i].node_mem) {
407 continue;
408 }
409 if (mem_start >= machine->ram_size) {
410 node_size = 0;
411 } else {
412 node_size = nodes[i].node_mem;
413 if (node_size > machine->ram_size - mem_start) {
414 node_size = machine->ram_size - mem_start;
415 }
416 }
417 if (!mem_start) {
418
419
420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
421 mem_start += spapr->rma_size;
422 node_size -= spapr->rma_size;
423 }
424 for ( ; node_size; ) {
425 hwaddr sizetmp = pow2floor(node_size);
426
427
428 if (ctzl(mem_start) < ctzl(sizetmp)) {
429 sizetmp = 1ULL << ctzl(mem_start);
430 }
431
432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
433 node_size -= sizetmp;
434 mem_start += sizetmp;
435 }
436 }
437
438 return 0;
439}
440
441static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
442 sPAPRMachineState *spapr)
443{
444 PowerPCCPU *cpu = POWERPC_CPU(cs);
445 CPUPPCState *env = &cpu->env;
446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
447 int index = spapr_get_vcpu_id(cpu);
448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ;
452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop[64];
454 size_t page_sizes_prop_size;
455 uint32_t vcpus_per_socket = smp_threads * smp_cores;
456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
457 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
458 sPAPRDRConnector *drc;
459 int drc_index;
460 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
461 int i;
462
463 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
464 if (drc) {
465 drc_index = spapr_drc_index(drc);
466 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
467 }
468
469 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
470 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
471
472 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
474 env->dcache_line_size)));
475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
476 env->dcache_line_size)));
477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
478 env->icache_line_size)));
479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
480 env->icache_line_size)));
481
482 if (pcc->l1_dcache_size) {
483 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
484 pcc->l1_dcache_size)));
485 } else {
486 warn_report("Unknown L1 dcache size for cpu");
487 }
488 if (pcc->l1_icache_size) {
489 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
490 pcc->l1_icache_size)));
491 } else {
492 warn_report("Unknown L1 icache size for cpu");
493 }
494
495 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
496 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
497 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
498 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
499 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
500 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
501
502 if (env->spr_cb[SPR_PURR].oea_read) {
503 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
504 }
505
506 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
507 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
508 segs, sizeof(segs))));
509 }
510
511
512
513
514
515
516
517 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
518 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
519 } else {
520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
521 }
522
523
524
525
526 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
528 }
529
530 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
531 sizeof(page_sizes_prop));
532 if (page_sizes_prop_size) {
533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
534 page_sizes_prop, page_sizes_prop_size)));
535 }
536
537 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
538
539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
540 cs->cpu_index / vcpus_per_socket)));
541
542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
543 pft_size_prop, sizeof(pft_size_prop))));
544
545 if (nb_numa_nodes > 1) {
546 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
547 }
548
549 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
550
551 if (pcc->radix_page_info) {
552 for (i = 0; i < pcc->radix_page_info->count; i++) {
553 radix_AP_encodings[i] =
554 cpu_to_be32(pcc->radix_page_info->entries[i]);
555 }
556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
557 radix_AP_encodings,
558 pcc->radix_page_info->count *
559 sizeof(radix_AP_encodings[0]))));
560 }
561}
562
563static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
564{
565 CPUState **rev;
566 CPUState *cs;
567 int n_cpus;
568 int cpus_offset;
569 char *nodename;
570 int i;
571
572 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
573 _FDT(cpus_offset);
574 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
575 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
576
577
578
579
580
581
582
583
584
585 n_cpus = 0;
586 rev = NULL;
587 CPU_FOREACH(cs) {
588 rev = g_renew(CPUState *, rev, n_cpus + 1);
589 rev[n_cpus++] = cs;
590 }
591
592 for (i = n_cpus - 1; i >= 0; i--) {
593 CPUState *cs = rev[i];
594 PowerPCCPU *cpu = POWERPC_CPU(cs);
595 int index = spapr_get_vcpu_id(cpu);
596 DeviceClass *dc = DEVICE_GET_CLASS(cs);
597 int offset;
598
599 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
600 continue;
601 }
602
603 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
604 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
605 g_free(nodename);
606 _FDT(offset);
607 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
608 }
609
610 g_free(rev);
611}
612
613static int spapr_rng_populate_dt(void *fdt)
614{
615 int node;
616 int ret;
617
618 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
619 if (node <= 0) {
620 return -1;
621 }
622 ret = fdt_setprop_string(fdt, node, "device_type",
623 "ibm,platform-facilities");
624 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
625 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
626
627 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
628 if (node <= 0) {
629 return -1;
630 }
631 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
632
633 return ret ? -1 : 0;
634}
635
636static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
637{
638 MemoryDeviceInfoList *info;
639
640 for (info = list; info; info = info->next) {
641 MemoryDeviceInfo *value = info->value;
642
643 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
644 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
645
646 if (addr >= pcdimm_info->addr &&
647 addr < (pcdimm_info->addr + pcdimm_info->size)) {
648 return pcdimm_info->node;
649 }
650 }
651 }
652
653 return -1;
654}
655
656struct sPAPRDrconfCellV2 {
657 uint32_t seq_lmbs;
658 uint64_t base_addr;
659 uint32_t drc_index;
660 uint32_t aa_index;
661 uint32_t flags;
662} QEMU_PACKED;
663
664typedef struct DrconfCellQueue {
665 struct sPAPRDrconfCellV2 cell;
666 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
667} DrconfCellQueue;
668
669static DrconfCellQueue *
670spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
671 uint32_t drc_index, uint32_t aa_index,
672 uint32_t flags)
673{
674 DrconfCellQueue *elem;
675
676 elem = g_malloc0(sizeof(*elem));
677 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
678 elem->cell.base_addr = cpu_to_be64(base_addr);
679 elem->cell.drc_index = cpu_to_be32(drc_index);
680 elem->cell.aa_index = cpu_to_be32(aa_index);
681 elem->cell.flags = cpu_to_be32(flags);
682
683 return elem;
684}
685
686
687static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt,
688 int offset, MemoryDeviceInfoList *dimms)
689{
690 MachineState *machine = MACHINE(spapr);
691 uint8_t *int_buf, *cur_index, buf_len;
692 int ret;
693 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
694 uint64_t addr, cur_addr, size;
695 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
696 uint64_t mem_end = machine->device_memory->base +
697 memory_region_size(&machine->device_memory->mr);
698 uint32_t node, nr_entries = 0;
699 sPAPRDRConnector *drc;
700 DrconfCellQueue *elem, *next;
701 MemoryDeviceInfoList *info;
702 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
703 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
704
705
706 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
707 SPAPR_LMB_FLAGS_RESERVED |
708 SPAPR_LMB_FLAGS_DRC_INVALID);
709 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
710 nr_entries++;
711
712 cur_addr = machine->device_memory->base;
713 for (info = dimms; info; info = info->next) {
714 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
715
716 addr = di->addr;
717 size = di->size;
718 node = di->node;
719
720
721 if (cur_addr < addr) {
722 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
723 g_assert(drc);
724 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
725 cur_addr, spapr_drc_index(drc), -1, 0);
726 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
727 nr_entries++;
728 }
729
730
731 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
732 g_assert(drc);
733 elem = spapr_get_drconf_cell(size / lmb_size, addr,
734 spapr_drc_index(drc), node,
735 SPAPR_LMB_FLAGS_ASSIGNED);
736 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
737 nr_entries++;
738 cur_addr = addr + size;
739 }
740
741
742 if (cur_addr < mem_end) {
743 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
744 g_assert(drc);
745 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
746 cur_addr, spapr_drc_index(drc), -1, 0);
747 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
748 nr_entries++;
749 }
750
751 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
752 int_buf = cur_index = g_malloc0(buf_len);
753 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
754 cur_index += sizeof(nr_entries);
755
756 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
757 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
758 cur_index += sizeof(elem->cell);
759 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
760 g_free(elem);
761 }
762
763 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
764 g_free(int_buf);
765 if (ret < 0) {
766 return -1;
767 }
768 return 0;
769}
770
771
772static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt,
773 int offset, MemoryDeviceInfoList *dimms)
774{
775 MachineState *machine = MACHINE(spapr);
776 int i, ret;
777 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
778 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
779 uint32_t nr_lmbs = (machine->device_memory->base +
780 memory_region_size(&machine->device_memory->mr)) /
781 lmb_size;
782 uint32_t *int_buf, *cur_index, buf_len;
783
784
785
786
787 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
788 cur_index = int_buf = g_malloc0(buf_len);
789 int_buf[0] = cpu_to_be32(nr_lmbs);
790 cur_index++;
791 for (i = 0; i < nr_lmbs; i++) {
792 uint64_t addr = i * lmb_size;
793 uint32_t *dynamic_memory = cur_index;
794
795 if (i >= device_lmb_start) {
796 sPAPRDRConnector *drc;
797
798 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
799 g_assert(drc);
800
801 dynamic_memory[0] = cpu_to_be32(addr >> 32);
802 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
803 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
804 dynamic_memory[3] = cpu_to_be32(0);
805 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
806 if (memory_region_present(get_system_memory(), addr)) {
807 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
808 } else {
809 dynamic_memory[5] = cpu_to_be32(0);
810 }
811 } else {
812
813
814
815
816
817 dynamic_memory[0] = cpu_to_be32(addr >> 32);
818 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
819 dynamic_memory[2] = cpu_to_be32(0);
820 dynamic_memory[3] = cpu_to_be32(0);
821 dynamic_memory[4] = cpu_to_be32(-1);
822 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
823 SPAPR_LMB_FLAGS_DRC_INVALID);
824 }
825
826 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
827 }
828 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
829 g_free(int_buf);
830 if (ret < 0) {
831 return -1;
832 }
833 return 0;
834}
835
836
837
838
839
840
841static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
842{
843 MachineState *machine = MACHINE(spapr);
844 int ret, i, offset;
845 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
846 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
847 uint32_t *int_buf, *cur_index, buf_len;
848 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
849 MemoryDeviceInfoList *dimms = NULL;
850
851
852
853
854 if (machine->ram_size == machine->maxram_size) {
855 return 0;
856 }
857
858 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
859
860 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
861 sizeof(prop_lmb_size));
862 if (ret < 0) {
863 return ret;
864 }
865
866 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
867 if (ret < 0) {
868 return ret;
869 }
870
871 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
872 if (ret < 0) {
873 return ret;
874 }
875
876
877 dimms = qmp_memory_device_list();
878 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
879 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
880 } else {
881 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
882 }
883 qapi_free_MemoryDeviceInfoList(dimms);
884
885 if (ret < 0) {
886 return ret;
887 }
888
889
890 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
891 cur_index = int_buf = g_malloc0(buf_len);
892
893 cur_index = int_buf;
894 int_buf[0] = cpu_to_be32(nr_nodes);
895 int_buf[1] = cpu_to_be32(4);
896 cur_index += 2;
897 for (i = 0; i < nr_nodes; i++) {
898 uint32_t associativity[] = {
899 cpu_to_be32(0x0),
900 cpu_to_be32(0x0),
901 cpu_to_be32(0x0),
902 cpu_to_be32(i)
903 };
904 memcpy(cur_index, associativity, sizeof(associativity));
905 cur_index += 4;
906 }
907 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
908 (cur_index - int_buf) * sizeof(uint32_t));
909 g_free(int_buf);
910
911 return ret;
912}
913
914static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
915 sPAPROptionVector *ov5_updates)
916{
917 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
918 int ret = 0, offset;
919
920
921 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
922 g_assert(smc->dr_lmb_enabled);
923 ret = spapr_populate_drconf_memory(spapr, fdt);
924 if (ret) {
925 goto out;
926 }
927 }
928
929 offset = fdt_path_offset(fdt, "/chosen");
930 if (offset < 0) {
931 offset = fdt_add_subnode(fdt, 0, "chosen");
932 if (offset < 0) {
933 return offset;
934 }
935 }
936 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
937 "ibm,architecture-vec-5");
938
939out:
940 return ret;
941}
942
943static bool spapr_hotplugged_dev_before_cas(void)
944{
945 Object *drc_container, *obj;
946 ObjectProperty *prop;
947 ObjectPropertyIterator iter;
948
949 drc_container = container_get(object_get_root(), "/dr-connector");
950 object_property_iter_init(&iter, drc_container);
951 while ((prop = object_property_iter_next(&iter))) {
952 if (!strstart(prop->type, "link<", NULL)) {
953 continue;
954 }
955 obj = object_property_get_link(drc_container, prop->name, NULL);
956 if (spapr_drc_needed(obj)) {
957 return true;
958 }
959 }
960 return false;
961}
962
963int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
964 target_ulong addr, target_ulong size,
965 sPAPROptionVector *ov5_updates)
966{
967 void *fdt, *fdt_skel;
968 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
969
970 if (spapr_hotplugged_dev_before_cas()) {
971 return 1;
972 }
973
974 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
975 error_report("SLOF provided an unexpected CAS buffer size "
976 TARGET_FMT_lu " (min: %zu, max: %u)",
977 size, sizeof(hdr), FW_MAX_SIZE);
978 exit(EXIT_FAILURE);
979 }
980
981 size -= sizeof(hdr);
982
983
984 fdt_skel = g_malloc0(size);
985 _FDT((fdt_create(fdt_skel, size)));
986 _FDT((fdt_finish_reservemap(fdt_skel)));
987 _FDT((fdt_begin_node(fdt_skel, "")));
988 _FDT((fdt_end_node(fdt_skel)));
989 _FDT((fdt_finish(fdt_skel)));
990 fdt = g_malloc0(size);
991 _FDT((fdt_open_into(fdt_skel, fdt, size)));
992 g_free(fdt_skel);
993
994
995 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
996
997 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
998 return -1;
999 }
1000
1001
1002 _FDT((fdt_pack(fdt)));
1003
1004 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1005 trace_spapr_cas_failed(size);
1006 return -1;
1007 }
1008
1009 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1010 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1011 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1012 g_free(fdt);
1013
1014 return 0;
1015}
1016
1017static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
1018{
1019 int rtas;
1020 GString *hypertas = g_string_sized_new(256);
1021 GString *qemu_hypertas = g_string_sized_new(256);
1022 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1023 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1024 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1025 uint32_t lrdr_capacity[] = {
1026 cpu_to_be32(max_device_addr >> 32),
1027 cpu_to_be32(max_device_addr & 0xffffffff),
1028 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1029 cpu_to_be32(max_cpus / smp_threads),
1030 };
1031 uint32_t maxdomains[] = {
1032 cpu_to_be32(4),
1033 cpu_to_be32(0),
1034 cpu_to_be32(0),
1035 cpu_to_be32(0),
1036 cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0),
1037 };
1038
1039 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1040
1041
1042 add_str(hypertas, "hcall-pft");
1043 add_str(hypertas, "hcall-term");
1044 add_str(hypertas, "hcall-dabr");
1045 add_str(hypertas, "hcall-interrupt");
1046 add_str(hypertas, "hcall-tce");
1047 add_str(hypertas, "hcall-vio");
1048 add_str(hypertas, "hcall-splpar");
1049 add_str(hypertas, "hcall-bulk");
1050 add_str(hypertas, "hcall-set-mode");
1051 add_str(hypertas, "hcall-sprg0");
1052 add_str(hypertas, "hcall-copy");
1053 add_str(hypertas, "hcall-debug");
1054 add_str(qemu_hypertas, "hcall-memop1");
1055
1056 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1057 add_str(hypertas, "hcall-multi-tce");
1058 }
1059
1060 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1061 add_str(hypertas, "hcall-hpt-resize");
1062 }
1063
1064 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1065 hypertas->str, hypertas->len));
1066 g_string_free(hypertas, TRUE);
1067 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1068 qemu_hypertas->str, qemu_hypertas->len));
1069 g_string_free(qemu_hypertas, TRUE);
1070
1071 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1072 refpoints, sizeof(refpoints)));
1073
1074 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1075 maxdomains, sizeof(maxdomains)));
1076
1077 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1078 RTAS_ERROR_LOG_MAX));
1079 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1080 RTAS_EVENT_SCAN_RATE));
1081
1082 g_assert(msi_nonbroken);
1083 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1084
1085
1086
1087
1088
1089
1090
1091
1092 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1093
1094 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1095 lrdr_capacity, sizeof(lrdr_capacity)));
1096
1097 spapr_dt_rtas_tokens(fdt, rtas);
1098}
1099
1100
1101
1102
1103static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
1104{
1105 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1106
1107 char val[2 * 4] = {
1108 23, 0x00,
1109 24, 0x00,
1110 25, 0x00,
1111 26, 0x40,
1112 };
1113
1114 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1115 first_ppc_cpu->compat_pvr)) {
1116
1117 val[3] = 0x00;
1118 } else if (kvm_enabled()) {
1119 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1120 val[3] = 0x80;
1121 } else if (kvmppc_has_cap_mmu_radix()) {
1122 val[3] = 0x40;
1123 } else {
1124 val[3] = 0x00;
1125 }
1126 } else {
1127
1128 val[3] = 0xC0;
1129 }
1130 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1131 val, sizeof(val)));
1132}
1133
1134static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1135{
1136 MachineState *machine = MACHINE(spapr);
1137 int chosen;
1138 const char *boot_device = machine->boot_order;
1139 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1140 size_t cb = 0;
1141 char *bootlist = get_boot_devices_list(&cb);
1142
1143 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1144
1145 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1146 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1147 spapr->initrd_base));
1148 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1149 spapr->initrd_base + spapr->initrd_size));
1150
1151 if (spapr->kernel_size) {
1152 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1153 cpu_to_be64(spapr->kernel_size) };
1154
1155 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1156 &kprop, sizeof(kprop)));
1157 if (spapr->kernel_le) {
1158 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1159 }
1160 }
1161 if (boot_menu) {
1162 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1163 }
1164 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1165 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1166 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1167
1168 if (cb && bootlist) {
1169 int i;
1170
1171 for (i = 0; i < cb; i++) {
1172 if (bootlist[i] == '\n') {
1173 bootlist[i] = ' ';
1174 }
1175 }
1176 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1177 }
1178
1179 if (boot_device && strlen(boot_device)) {
1180 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1181 }
1182
1183 if (!spapr->has_graphics && stdout_path) {
1184
1185
1186
1187
1188
1189
1190 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1191 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1192 }
1193
1194 spapr_dt_ov5_platform_support(fdt, chosen);
1195
1196 g_free(stdout_path);
1197 g_free(bootlist);
1198}
1199
1200static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1201{
1202
1203
1204 int hypervisor;
1205 uint8_t hypercall[16];
1206
1207 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1208
1209 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1210 if (kvmppc_has_cap_fixup_hcalls()) {
1211
1212
1213
1214
1215 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1216 sizeof(hypercall))) {
1217 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1218 hypercall, sizeof(hypercall)));
1219 }
1220 }
1221}
1222
1223static void *spapr_build_fdt(sPAPRMachineState *spapr,
1224 hwaddr rtas_addr,
1225 hwaddr rtas_size)
1226{
1227 MachineState *machine = MACHINE(spapr);
1228 MachineClass *mc = MACHINE_GET_CLASS(machine);
1229 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1230 int ret;
1231 void *fdt;
1232 sPAPRPHBState *phb;
1233 char *buf;
1234
1235 fdt = g_malloc0(FDT_MAX_SIZE);
1236 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1237
1238
1239 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1240 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1241 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1242
1243
1244
1245
1246
1247 if (kvmppc_get_host_model(&buf)) {
1248 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1249 g_free(buf);
1250 }
1251 if (kvmppc_get_host_serial(&buf)) {
1252 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1253 g_free(buf);
1254 }
1255
1256 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1257
1258 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1259 if (qemu_uuid_set) {
1260 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1261 }
1262 g_free(buf);
1263
1264 if (qemu_get_vm_name()) {
1265 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1266 qemu_get_vm_name()));
1267 }
1268
1269 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1270 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1271
1272
1273 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
1274
1275 ret = spapr_populate_memory(spapr, fdt);
1276 if (ret < 0) {
1277 error_report("couldn't setup memory nodes in fdt");
1278 exit(1);
1279 }
1280
1281
1282 spapr_dt_vdevice(spapr->vio_bus, fdt);
1283
1284 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1285 ret = spapr_rng_populate_dt(fdt);
1286 if (ret < 0) {
1287 error_report("could not set up rng device in the fdt");
1288 exit(1);
1289 }
1290 }
1291
1292 QLIST_FOREACH(phb, &spapr->phbs, list) {
1293 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, smc->irq->nr_msis);
1294 if (ret < 0) {
1295 error_report("couldn't setup PCI devices in fdt");
1296 exit(1);
1297 }
1298 }
1299
1300
1301 spapr_populate_cpus_dt_node(fdt, spapr);
1302
1303 if (smc->dr_lmb_enabled) {
1304 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1305 }
1306
1307 if (mc->has_hotpluggable_cpus) {
1308 int offset = fdt_path_offset(fdt, "/cpus");
1309 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1310 SPAPR_DR_CONNECTOR_TYPE_CPU);
1311 if (ret < 0) {
1312 error_report("Couldn't set up CPU DR device tree properties");
1313 exit(1);
1314 }
1315 }
1316
1317
1318 spapr_dt_events(spapr, fdt);
1319
1320
1321 spapr_dt_rtas(spapr, fdt);
1322
1323
1324 spapr_dt_chosen(spapr, fdt);
1325
1326
1327 if (kvm_enabled()) {
1328 spapr_dt_hypervisor(spapr, fdt);
1329 }
1330
1331
1332 if (spapr->kernel_size) {
1333 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1334 }
1335 if (spapr->initrd_size) {
1336 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1337 }
1338
1339
1340 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1341 if (ret < 0) {
1342 error_report("couldn't setup CAS properties fdt");
1343 exit(1);
1344 }
1345
1346 return fdt;
1347}
1348
1349static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1350{
1351 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1352}
1353
1354static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1355 PowerPCCPU *cpu)
1356{
1357 CPUPPCState *env = &cpu->env;
1358
1359
1360 g_assert(qemu_mutex_iothread_locked());
1361
1362 if (msr_pr) {
1363 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1364 env->gpr[3] = H_PRIVILEGE;
1365 } else {
1366 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1367 }
1368}
1369
1370static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1371{
1372 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1373
1374 return spapr->patb_entry;
1375}
1376
1377#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1378#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1379#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1380#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1381#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1382
1383
1384
1385
1386static int get_htab_fd(sPAPRMachineState *spapr)
1387{
1388 Error *local_err = NULL;
1389
1390 if (spapr->htab_fd >= 0) {
1391 return spapr->htab_fd;
1392 }
1393
1394 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1395 if (spapr->htab_fd < 0) {
1396 error_report_err(local_err);
1397 }
1398
1399 return spapr->htab_fd;
1400}
1401
1402void close_htab_fd(sPAPRMachineState *spapr)
1403{
1404 if (spapr->htab_fd >= 0) {
1405 close(spapr->htab_fd);
1406 }
1407 spapr->htab_fd = -1;
1408}
1409
1410static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1411{
1412 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1413
1414 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1415}
1416
1417static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1418{
1419 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1420
1421 assert(kvm_enabled());
1422
1423 if (!spapr->htab) {
1424 return 0;
1425 }
1426
1427 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1428}
1429
1430static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1431 hwaddr ptex, int n)
1432{
1433 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1434 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1435
1436 if (!spapr->htab) {
1437
1438
1439
1440 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1441 kvmppc_read_hptes(hptes, ptex, n);
1442 return hptes;
1443 }
1444
1445
1446
1447
1448
1449 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1450}
1451
1452static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1453 const ppc_hash_pte64_t *hptes,
1454 hwaddr ptex, int n)
1455{
1456 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1457
1458 if (!spapr->htab) {
1459 g_free((void *)hptes);
1460 }
1461
1462
1463}
1464
1465static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1466 uint64_t pte0, uint64_t pte1)
1467{
1468 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1469 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1470
1471 if (!spapr->htab) {
1472 kvmppc_write_hpte(ptex, pte0, pte1);
1473 } else {
1474 stq_p(spapr->htab + offset, pte0);
1475 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1476 }
1477}
1478
1479int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1480{
1481 int shift;
1482
1483
1484
1485
1486 shift = ctz64(pow2ceil(ramsize)) - 7;
1487 shift = MAX(shift, 18);
1488 shift = MIN(shift, 46);
1489 return shift;
1490}
1491
1492void spapr_free_hpt(sPAPRMachineState *spapr)
1493{
1494 g_free(spapr->htab);
1495 spapr->htab = NULL;
1496 spapr->htab_shift = 0;
1497 close_htab_fd(spapr);
1498}
1499
1500void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1501 Error **errp)
1502{
1503 long rc;
1504
1505
1506 spapr_free_hpt(spapr);
1507
1508 rc = kvmppc_reset_htab(shift);
1509 if (rc < 0) {
1510
1511 error_setg_errno(errp, errno,
1512 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1513 shift);
1514
1515
1516 } else if (rc > 0) {
1517
1518 if (rc != shift) {
1519 error_setg(errp,
1520 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1521 shift, rc);
1522 }
1523
1524 spapr->htab_shift = shift;
1525 spapr->htab = NULL;
1526 } else {
1527
1528 size_t size = 1ULL << shift;
1529 int i;
1530
1531 spapr->htab = qemu_memalign(size, size);
1532 if (!spapr->htab) {
1533 error_setg_errno(errp, errno,
1534 "Could not allocate HPT of order %d", shift);
1535 return;
1536 }
1537
1538 memset(spapr->htab, 0, size);
1539 spapr->htab_shift = shift;
1540
1541 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1542 DIRTY_HPTE(HPTE(spapr->htab, i));
1543 }
1544 }
1545
1546 spapr->patb_entry = 0;
1547}
1548
1549void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1550{
1551 int hpt_shift;
1552
1553 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1554 || (spapr->cas_reboot
1555 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1556 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1557 } else {
1558 uint64_t current_ram_size;
1559
1560 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1561 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1562 }
1563 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1564
1565 if (spapr->vrma_adjust) {
1566 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1567 spapr->htab_shift);
1568 }
1569}
1570
1571static int spapr_reset_drcs(Object *child, void *opaque)
1572{
1573 sPAPRDRConnector *drc =
1574 (sPAPRDRConnector *) object_dynamic_cast(child,
1575 TYPE_SPAPR_DR_CONNECTOR);
1576
1577 if (drc) {
1578 spapr_drc_reset(drc);
1579 }
1580
1581 return 0;
1582}
1583
1584static void spapr_machine_reset(void)
1585{
1586 MachineState *machine = MACHINE(qdev_get_machine());
1587 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1588 PowerPCCPU *first_ppc_cpu;
1589 uint32_t rtas_limit;
1590 hwaddr rtas_addr, fdt_addr;
1591 void *fdt;
1592 int rc;
1593
1594 spapr_caps_apply(spapr);
1595
1596 first_ppc_cpu = POWERPC_CPU(first_cpu);
1597 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1598 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1599 spapr->max_compat_pvr)) {
1600
1601
1602
1603 spapr->patb_entry = PATBE1_GR;
1604 } else {
1605 spapr_setup_hpt_and_vrma(spapr);
1606 }
1607
1608
1609
1610 if (!spapr->cas_reboot) {
1611 spapr_ovec_cleanup(spapr->ov5_cas);
1612 spapr->ov5_cas = spapr_ovec_new();
1613
1614 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1615 }
1616
1617 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1618 spapr_irq_msi_reset(spapr);
1619 }
1620
1621 qemu_devices_reset();
1622
1623
1624
1625
1626
1627
1628 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1629
1630 spapr_clear_pending_events(spapr);
1631
1632
1633
1634
1635
1636
1637 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1638 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1639 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1640
1641 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1642
1643 spapr_load_rtas(spapr, fdt, rtas_addr);
1644
1645 rc = fdt_pack(fdt);
1646
1647
1648 assert(rc == 0);
1649
1650 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1651 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1652 fdt_totalsize(fdt), FDT_MAX_SIZE);
1653 exit(1);
1654 }
1655
1656
1657 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1658 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1659 g_free(fdt);
1660
1661
1662 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1663 first_ppc_cpu->env.gpr[5] = 0;
1664
1665 spapr->cas_reboot = false;
1666}
1667
1668static void spapr_create_nvram(sPAPRMachineState *spapr)
1669{
1670 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1671 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1672
1673 if (dinfo) {
1674 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1675 &error_fatal);
1676 }
1677
1678 qdev_init_nofail(dev);
1679
1680 spapr->nvram = (struct sPAPRNVRAM *)dev;
1681}
1682
1683static void spapr_rtc_create(sPAPRMachineState *spapr)
1684{
1685 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1686 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1687 &error_fatal);
1688 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1689 &error_fatal);
1690 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1691 "date", &error_fatal);
1692}
1693
1694
1695static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1696{
1697 switch (vga_interface_type) {
1698 case VGA_NONE:
1699 return false;
1700 case VGA_DEVICE:
1701 return true;
1702 case VGA_STD:
1703 case VGA_VIRTIO:
1704 return pci_vga_init(pci_bus) != NULL;
1705 default:
1706 error_setg(errp,
1707 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1708 return false;
1709 }
1710}
1711
1712static int spapr_pre_load(void *opaque)
1713{
1714 int rc;
1715
1716 rc = spapr_caps_pre_load(opaque);
1717 if (rc) {
1718 return rc;
1719 }
1720
1721 return 0;
1722}
1723
1724static int spapr_post_load(void *opaque, int version_id)
1725{
1726 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1727 int err = 0;
1728
1729 err = spapr_caps_post_migration(spapr);
1730 if (err) {
1731 return err;
1732 }
1733
1734 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1735 CPUState *cs;
1736 CPU_FOREACH(cs) {
1737 PowerPCCPU *cpu = POWERPC_CPU(cs);
1738 icp_resend(ICP(cpu->intc));
1739 }
1740 }
1741
1742
1743
1744
1745
1746 if (version_id < 3) {
1747 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1748 }
1749
1750 if (kvm_enabled() && spapr->patb_entry) {
1751 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1752 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1753 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1754
1755 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1756 if (err) {
1757 error_report("Process table config unsupported by the host");
1758 return -EINVAL;
1759 }
1760 }
1761
1762 return err;
1763}
1764
1765static int spapr_pre_save(void *opaque)
1766{
1767 int rc;
1768
1769 rc = spapr_caps_pre_save(opaque);
1770 if (rc) {
1771 return rc;
1772 }
1773
1774 return 0;
1775}
1776
1777static bool version_before_3(void *opaque, int version_id)
1778{
1779 return version_id < 3;
1780}
1781
1782static bool spapr_pending_events_needed(void *opaque)
1783{
1784 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1785 return !QTAILQ_EMPTY(&spapr->pending_events);
1786}
1787
1788static const VMStateDescription vmstate_spapr_event_entry = {
1789 .name = "spapr_event_log_entry",
1790 .version_id = 1,
1791 .minimum_version_id = 1,
1792 .fields = (VMStateField[]) {
1793 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1794 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1795 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1796 NULL, extended_length),
1797 VMSTATE_END_OF_LIST()
1798 },
1799};
1800
1801static const VMStateDescription vmstate_spapr_pending_events = {
1802 .name = "spapr_pending_events",
1803 .version_id = 1,
1804 .minimum_version_id = 1,
1805 .needed = spapr_pending_events_needed,
1806 .fields = (VMStateField[]) {
1807 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1808 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1809 VMSTATE_END_OF_LIST()
1810 },
1811};
1812
1813static bool spapr_ov5_cas_needed(void *opaque)
1814{
1815 sPAPRMachineState *spapr = opaque;
1816 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1817 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1818 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1819 bool cas_needed;
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1847 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1848 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1849
1850
1851
1852
1853
1854
1855 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1856 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1857
1858 spapr_ovec_cleanup(ov5_mask);
1859 spapr_ovec_cleanup(ov5_legacy);
1860 spapr_ovec_cleanup(ov5_removed);
1861
1862 return cas_needed;
1863}
1864
1865static const VMStateDescription vmstate_spapr_ov5_cas = {
1866 .name = "spapr_option_vector_ov5_cas",
1867 .version_id = 1,
1868 .minimum_version_id = 1,
1869 .needed = spapr_ov5_cas_needed,
1870 .fields = (VMStateField[]) {
1871 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1872 vmstate_spapr_ovec, sPAPROptionVector),
1873 VMSTATE_END_OF_LIST()
1874 },
1875};
1876
1877static bool spapr_patb_entry_needed(void *opaque)
1878{
1879 sPAPRMachineState *spapr = opaque;
1880
1881 return !!spapr->patb_entry;
1882}
1883
1884static const VMStateDescription vmstate_spapr_patb_entry = {
1885 .name = "spapr_patb_entry",
1886 .version_id = 1,
1887 .minimum_version_id = 1,
1888 .needed = spapr_patb_entry_needed,
1889 .fields = (VMStateField[]) {
1890 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1891 VMSTATE_END_OF_LIST()
1892 },
1893};
1894
1895static bool spapr_irq_map_needed(void *opaque)
1896{
1897 sPAPRMachineState *spapr = opaque;
1898
1899 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1900}
1901
1902static const VMStateDescription vmstate_spapr_irq_map = {
1903 .name = "spapr_irq_map",
1904 .version_id = 1,
1905 .minimum_version_id = 1,
1906 .needed = spapr_irq_map_needed,
1907 .fields = (VMStateField[]) {
1908 VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr),
1909 VMSTATE_END_OF_LIST()
1910 },
1911};
1912
1913static const VMStateDescription vmstate_spapr = {
1914 .name = "spapr",
1915 .version_id = 3,
1916 .minimum_version_id = 1,
1917 .pre_load = spapr_pre_load,
1918 .post_load = spapr_post_load,
1919 .pre_save = spapr_pre_save,
1920 .fields = (VMStateField[]) {
1921
1922 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1923
1924
1925 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1926
1927 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1928 VMSTATE_END_OF_LIST()
1929 },
1930 .subsections = (const VMStateDescription*[]) {
1931 &vmstate_spapr_ov5_cas,
1932 &vmstate_spapr_patb_entry,
1933 &vmstate_spapr_pending_events,
1934 &vmstate_spapr_cap_htm,
1935 &vmstate_spapr_cap_vsx,
1936 &vmstate_spapr_cap_dfp,
1937 &vmstate_spapr_cap_cfpc,
1938 &vmstate_spapr_cap_sbbc,
1939 &vmstate_spapr_cap_ibs,
1940 &vmstate_spapr_irq_map,
1941 &vmstate_spapr_cap_nested_kvm_hv,
1942 NULL
1943 }
1944};
1945
1946static int htab_save_setup(QEMUFile *f, void *opaque)
1947{
1948 sPAPRMachineState *spapr = opaque;
1949
1950
1951 if (!spapr->htab_shift) {
1952 qemu_put_be32(f, -1);
1953 } else {
1954 qemu_put_be32(f, spapr->htab_shift);
1955 }
1956
1957 if (spapr->htab) {
1958 spapr->htab_save_index = 0;
1959 spapr->htab_first_pass = true;
1960 } else {
1961 if (spapr->htab_shift) {
1962 assert(kvm_enabled());
1963 }
1964 }
1965
1966
1967 return 0;
1968}
1969
1970static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1971 int chunkstart, int n_valid, int n_invalid)
1972{
1973 qemu_put_be32(f, chunkstart);
1974 qemu_put_be16(f, n_valid);
1975 qemu_put_be16(f, n_invalid);
1976 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1977 HASH_PTE_SIZE_64 * n_valid);
1978}
1979
1980static void htab_save_end_marker(QEMUFile *f)
1981{
1982 qemu_put_be32(f, 0);
1983 qemu_put_be16(f, 0);
1984 qemu_put_be16(f, 0);
1985}
1986
1987static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1988 int64_t max_ns)
1989{
1990 bool has_timeout = max_ns != -1;
1991 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1992 int index = spapr->htab_save_index;
1993 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1994
1995 assert(spapr->htab_first_pass);
1996
1997 do {
1998 int chunkstart;
1999
2000
2001 while ((index < htabslots)
2002 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2003 CLEAN_HPTE(HPTE(spapr->htab, index));
2004 index++;
2005 }
2006
2007
2008 chunkstart = index;
2009 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2010 && HPTE_VALID(HPTE(spapr->htab, index))) {
2011 CLEAN_HPTE(HPTE(spapr->htab, index));
2012 index++;
2013 }
2014
2015 if (index > chunkstart) {
2016 int n_valid = index - chunkstart;
2017
2018 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2019
2020 if (has_timeout &&
2021 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2022 break;
2023 }
2024 }
2025 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2026
2027 if (index >= htabslots) {
2028 assert(index == htabslots);
2029 index = 0;
2030 spapr->htab_first_pass = false;
2031 }
2032 spapr->htab_save_index = index;
2033}
2034
2035static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
2036 int64_t max_ns)
2037{
2038 bool final = max_ns < 0;
2039 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2040 int examined = 0, sent = 0;
2041 int index = spapr->htab_save_index;
2042 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2043
2044 assert(!spapr->htab_first_pass);
2045
2046 do {
2047 int chunkstart, invalidstart;
2048
2049
2050 while ((index < htabslots)
2051 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2052 index++;
2053 examined++;
2054 }
2055
2056 chunkstart = index;
2057
2058 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2059 && HPTE_DIRTY(HPTE(spapr->htab, index))
2060 && HPTE_VALID(HPTE(spapr->htab, index))) {
2061 CLEAN_HPTE(HPTE(spapr->htab, index));
2062 index++;
2063 examined++;
2064 }
2065
2066 invalidstart = index;
2067
2068 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2069 && HPTE_DIRTY(HPTE(spapr->htab, index))
2070 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2071 CLEAN_HPTE(HPTE(spapr->htab, index));
2072 index++;
2073 examined++;
2074 }
2075
2076 if (index > chunkstart) {
2077 int n_valid = invalidstart - chunkstart;
2078 int n_invalid = index - invalidstart;
2079
2080 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2081 sent += index - chunkstart;
2082
2083 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2084 break;
2085 }
2086 }
2087
2088 if (examined >= htabslots) {
2089 break;
2090 }
2091
2092 if (index >= htabslots) {
2093 assert(index == htabslots);
2094 index = 0;
2095 }
2096 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2097
2098 if (index >= htabslots) {
2099 assert(index == htabslots);
2100 index = 0;
2101 }
2102
2103 spapr->htab_save_index = index;
2104
2105 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2106}
2107
2108#define MAX_ITERATION_NS 5000000
2109#define MAX_KVM_BUF_SIZE 2048
2110
2111static int htab_save_iterate(QEMUFile *f, void *opaque)
2112{
2113 sPAPRMachineState *spapr = opaque;
2114 int fd;
2115 int rc = 0;
2116
2117
2118 if (!spapr->htab_shift) {
2119 qemu_put_be32(f, -1);
2120 return 1;
2121 } else {
2122 qemu_put_be32(f, 0);
2123 }
2124
2125 if (!spapr->htab) {
2126 assert(kvm_enabled());
2127
2128 fd = get_htab_fd(spapr);
2129 if (fd < 0) {
2130 return fd;
2131 }
2132
2133 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2134 if (rc < 0) {
2135 return rc;
2136 }
2137 } else if (spapr->htab_first_pass) {
2138 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2139 } else {
2140 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2141 }
2142
2143 htab_save_end_marker(f);
2144
2145 return rc;
2146}
2147
2148static int htab_save_complete(QEMUFile *f, void *opaque)
2149{
2150 sPAPRMachineState *spapr = opaque;
2151 int fd;
2152
2153
2154 if (!spapr->htab_shift) {
2155 qemu_put_be32(f, -1);
2156 return 0;
2157 } else {
2158 qemu_put_be32(f, 0);
2159 }
2160
2161 if (!spapr->htab) {
2162 int rc;
2163
2164 assert(kvm_enabled());
2165
2166 fd = get_htab_fd(spapr);
2167 if (fd < 0) {
2168 return fd;
2169 }
2170
2171 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2172 if (rc < 0) {
2173 return rc;
2174 }
2175 } else {
2176 if (spapr->htab_first_pass) {
2177 htab_save_first_pass(f, spapr, -1);
2178 }
2179 htab_save_later_pass(f, spapr, -1);
2180 }
2181
2182
2183 htab_save_end_marker(f);
2184
2185 return 0;
2186}
2187
2188static int htab_load(QEMUFile *f, void *opaque, int version_id)
2189{
2190 sPAPRMachineState *spapr = opaque;
2191 uint32_t section_hdr;
2192 int fd = -1;
2193 Error *local_err = NULL;
2194
2195 if (version_id < 1 || version_id > 1) {
2196 error_report("htab_load() bad version");
2197 return -EINVAL;
2198 }
2199
2200 section_hdr = qemu_get_be32(f);
2201
2202 if (section_hdr == -1) {
2203 spapr_free_hpt(spapr);
2204 return 0;
2205 }
2206
2207 if (section_hdr) {
2208
2209 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2210 if (local_err) {
2211 error_report_err(local_err);
2212 return -EINVAL;
2213 }
2214 return 0;
2215 }
2216
2217 if (!spapr->htab) {
2218 assert(kvm_enabled());
2219
2220 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2221 if (fd < 0) {
2222 error_report_err(local_err);
2223 return fd;
2224 }
2225 }
2226
2227 while (true) {
2228 uint32_t index;
2229 uint16_t n_valid, n_invalid;
2230
2231 index = qemu_get_be32(f);
2232 n_valid = qemu_get_be16(f);
2233 n_invalid = qemu_get_be16(f);
2234
2235 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2236
2237 break;
2238 }
2239
2240 if ((index + n_valid + n_invalid) >
2241 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2242
2243 error_report(
2244 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2245 index, n_valid, n_invalid, spapr->htab_shift);
2246 return -EINVAL;
2247 }
2248
2249 if (spapr->htab) {
2250 if (n_valid) {
2251 qemu_get_buffer(f, HPTE(spapr->htab, index),
2252 HASH_PTE_SIZE_64 * n_valid);
2253 }
2254 if (n_invalid) {
2255 memset(HPTE(spapr->htab, index + n_valid), 0,
2256 HASH_PTE_SIZE_64 * n_invalid);
2257 }
2258 } else {
2259 int rc;
2260
2261 assert(fd >= 0);
2262
2263 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2264 if (rc < 0) {
2265 return rc;
2266 }
2267 }
2268 }
2269
2270 if (!spapr->htab) {
2271 assert(fd >= 0);
2272 close(fd);
2273 }
2274
2275 return 0;
2276}
2277
2278static void htab_save_cleanup(void *opaque)
2279{
2280 sPAPRMachineState *spapr = opaque;
2281
2282 close_htab_fd(spapr);
2283}
2284
2285static SaveVMHandlers savevm_htab_handlers = {
2286 .save_setup = htab_save_setup,
2287 .save_live_iterate = htab_save_iterate,
2288 .save_live_complete_precopy = htab_save_complete,
2289 .save_cleanup = htab_save_cleanup,
2290 .load_state = htab_load,
2291};
2292
2293static void spapr_boot_set(void *opaque, const char *boot_device,
2294 Error **errp)
2295{
2296 MachineState *machine = MACHINE(opaque);
2297 machine->boot_order = g_strdup(boot_device);
2298}
2299
2300static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2301{
2302 MachineState *machine = MACHINE(spapr);
2303 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2304 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2305 int i;
2306
2307 for (i = 0; i < nr_lmbs; i++) {
2308 uint64_t addr;
2309
2310 addr = i * lmb_size + machine->device_memory->base;
2311 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2312 addr / lmb_size);
2313 }
2314}
2315
2316
2317
2318
2319
2320
2321static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2322{
2323 int i;
2324
2325 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2326 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2327 " is not aligned to %" PRIu64 " MiB",
2328 machine->ram_size,
2329 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2330 return;
2331 }
2332
2333 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2334 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2335 " is not aligned to %" PRIu64 " MiB",
2336 machine->ram_size,
2337 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2338 return;
2339 }
2340
2341 for (i = 0; i < nb_numa_nodes; i++) {
2342 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2343 error_setg(errp,
2344 "Node %d memory size 0x%" PRIx64
2345 " is not aligned to %" PRIu64 " MiB",
2346 i, numa_info[i].node_mem,
2347 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2348 return;
2349 }
2350 }
2351}
2352
2353
2354static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2355{
2356 int index = id / smp_threads;
2357
2358 if (index >= ms->possible_cpus->len) {
2359 return NULL;
2360 }
2361 if (idx) {
2362 *idx = index;
2363 }
2364 return &ms->possible_cpus->cpus[index];
2365}
2366
2367static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2368{
2369 Error *local_err = NULL;
2370 bool vsmt_user = !!spapr->vsmt;
2371 int kvm_smt = kvmppc_smt_threads();
2372 int ret;
2373
2374 if (!kvm_enabled() && (smp_threads > 1)) {
2375 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2376 "on a pseries machine");
2377 goto out;
2378 }
2379 if (!is_power_of_2(smp_threads)) {
2380 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2381 "machine because it must be a power of 2", smp_threads);
2382 goto out;
2383 }
2384
2385
2386 if (vsmt_user) {
2387 if (spapr->vsmt < smp_threads) {
2388 error_setg(&local_err, "Cannot support VSMT mode %d"
2389 " because it must be >= threads/core (%d)",
2390 spapr->vsmt, smp_threads);
2391 goto out;
2392 }
2393
2394 } else {
2395
2396
2397
2398
2399
2400
2401
2402 spapr->vsmt = MAX(8, smp_threads);
2403 }
2404
2405
2406 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2407 ret = kvmppc_set_smt_threads(spapr->vsmt);
2408 if (ret) {
2409
2410 error_setg(&local_err,
2411 "Failed to set KVM's VSMT mode to %d (errno %d)",
2412 spapr->vsmt, ret);
2413
2414
2415
2416
2417 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2418 warn_report_err(local_err);
2419 local_err = NULL;
2420 goto out;
2421 } else {
2422 if (!vsmt_user) {
2423 error_append_hint(&local_err,
2424 "On PPC, a VM with %d threads/core"
2425 " on a host with %d threads/core"
2426 " requires the use of VSMT mode %d.\n",
2427 smp_threads, kvm_smt, spapr->vsmt);
2428 }
2429 kvmppc_hint_smt_possible(&local_err);
2430 goto out;
2431 }
2432 }
2433 }
2434
2435out:
2436 error_propagate(errp, local_err);
2437}
2438
2439static void spapr_init_cpus(sPAPRMachineState *spapr)
2440{
2441 MachineState *machine = MACHINE(spapr);
2442 MachineClass *mc = MACHINE_GET_CLASS(machine);
2443 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2444 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2445 const CPUArchIdList *possible_cpus;
2446 int boot_cores_nr = smp_cpus / smp_threads;
2447 int i;
2448
2449 possible_cpus = mc->possible_cpu_arch_ids(machine);
2450 if (mc->has_hotpluggable_cpus) {
2451 if (smp_cpus % smp_threads) {
2452 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2453 smp_cpus, smp_threads);
2454 exit(1);
2455 }
2456 if (max_cpus % smp_threads) {
2457 error_report("max_cpus (%u) must be multiple of threads (%u)",
2458 max_cpus, smp_threads);
2459 exit(1);
2460 }
2461 } else {
2462 if (max_cpus != smp_cpus) {
2463 error_report("This machine version does not support CPU hotplug");
2464 exit(1);
2465 }
2466 boot_cores_nr = possible_cpus->len;
2467 }
2468
2469
2470
2471
2472 spapr_set_vsmt_mode(spapr, &error_fatal);
2473
2474 if (smc->pre_2_10_has_unused_icps) {
2475 int i;
2476
2477 for (i = 0; i < xics_max_server_number(spapr); i++) {
2478
2479
2480
2481 pre_2_10_vmstate_register_dummy_icp(i);
2482 }
2483 }
2484
2485 for (i = 0; i < possible_cpus->len; i++) {
2486 int core_id = i * smp_threads;
2487
2488 if (mc->has_hotpluggable_cpus) {
2489 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2490 spapr_vcpu_id(spapr, core_id));
2491 }
2492
2493 if (i < boot_cores_nr) {
2494 Object *core = object_new(type);
2495 int nr_threads = smp_threads;
2496
2497
2498 if ((i + 1) * smp_threads >= smp_cpus) {
2499 nr_threads = smp_cpus - i * smp_threads;
2500 }
2501
2502 object_property_set_int(core, nr_threads, "nr-threads",
2503 &error_fatal);
2504 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2505 &error_fatal);
2506 object_property_set_bool(core, true, "realized", &error_fatal);
2507
2508 object_unref(core);
2509 }
2510 }
2511}
2512
2513
2514static void spapr_machine_init(MachineState *machine)
2515{
2516 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2517 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2518 const char *kernel_filename = machine->kernel_filename;
2519 const char *initrd_filename = machine->initrd_filename;
2520 PCIHostState *phb;
2521 int i;
2522 MemoryRegion *sysmem = get_system_memory();
2523 MemoryRegion *ram = g_new(MemoryRegion, 1);
2524 hwaddr node0_size = spapr_node0_size(machine);
2525 long load_limit, fw_size;
2526 char *filename;
2527 Error *resize_hpt_err = NULL;
2528
2529 msi_nonbroken = true;
2530
2531 QLIST_INIT(&spapr->phbs);
2532 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2533
2534
2535 spapr_caps_init(spapr);
2536
2537 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2538 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2539
2540
2541
2542
2543
2544
2545 if (resize_hpt_err) {
2546 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2547 error_free(resize_hpt_err);
2548 resize_hpt_err = NULL;
2549 } else {
2550 spapr->resize_hpt = smc->resize_hpt_default;
2551 }
2552 }
2553
2554 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2555
2556 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2557
2558
2559
2560 error_report_err(resize_hpt_err);
2561 exit(1);
2562 }
2563
2564 spapr->rma_size = node0_size;
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575 if (kvm_enabled()) {
2576 spapr->vrma_adjust = 1;
2577 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2578 }
2579
2580
2581
2582
2583
2584
2585 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2586
2587 if (spapr->rma_size > node0_size) {
2588 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2589 spapr->rma_size);
2590 exit(1);
2591 }
2592
2593
2594 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2595
2596
2597 smc->irq->init(spapr, &error_fatal);
2598
2599
2600
2601 spapr->ov5 = spapr_ovec_new();
2602 spapr->ov5_cas = spapr_ovec_new();
2603
2604 if (smc->dr_lmb_enabled) {
2605 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2606 spapr_validate_node_memory(machine, &error_fatal);
2607 }
2608
2609 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2610
2611
2612 if (spapr->use_hotplug_event_source) {
2613 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2614 }
2615
2616
2617 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2618 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2619 }
2620
2621
2622 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2623
2624
2625 spapr_init_cpus(spapr);
2626
2627 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2628 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2629 spapr->max_compat_pvr)) {
2630
2631 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2632 }
2633
2634
2635 if (kvm_enabled()) {
2636
2637 kvmppc_enable_logical_ci_hcalls();
2638 kvmppc_enable_set_mode_hcall();
2639
2640
2641 kvmppc_enable_clear_ref_mod_hcalls();
2642 }
2643
2644
2645 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2646 machine->ram_size);
2647 memory_region_add_subregion(sysmem, 0, ram);
2648
2649
2650 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2651
2652
2653 if (machine->ram_size < machine->maxram_size) {
2654 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2655
2656
2657
2658
2659
2660 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2661 SPAPR_MAX_RAM_SLOTS;
2662
2663 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2664 max_memslots = SPAPR_MAX_RAM_SLOTS;
2665 }
2666 if (machine->ram_slots > max_memslots) {
2667 error_report("Specified number of memory slots %"
2668 PRIu64" exceeds max supported %d",
2669 machine->ram_slots, max_memslots);
2670 exit(1);
2671 }
2672
2673 machine->device_memory->base = ROUND_UP(machine->ram_size,
2674 SPAPR_DEVICE_MEM_ALIGN);
2675 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2676 "device-memory", device_mem_size);
2677 memory_region_add_subregion(sysmem, machine->device_memory->base,
2678 &machine->device_memory->mr);
2679 }
2680
2681 if (smc->dr_lmb_enabled) {
2682 spapr_create_lmb_dr_connectors(spapr);
2683 }
2684
2685 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2686 if (!filename) {
2687 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2688 exit(1);
2689 }
2690 spapr->rtas_size = get_image_size(filename);
2691 if (spapr->rtas_size < 0) {
2692 error_report("Could not get size of LPAR rtas '%s'", filename);
2693 exit(1);
2694 }
2695 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2696 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2697 error_report("Could not load LPAR rtas '%s'", filename);
2698 exit(1);
2699 }
2700 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2701 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2702 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2703 exit(1);
2704 }
2705 g_free(filename);
2706
2707
2708 spapr_events_init(spapr);
2709
2710
2711 spapr_rtc_create(spapr);
2712
2713
2714 spapr->vio_bus = spapr_vio_bus_init();
2715
2716 for (i = 0; i < serial_max_hds(); i++) {
2717 if (serial_hd(i)) {
2718 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2719 }
2720 }
2721
2722
2723 spapr_create_nvram(spapr);
2724
2725
2726 spapr_pci_rtas_init();
2727
2728 phb = spapr_create_phb(spapr, 0);
2729
2730 for (i = 0; i < nb_nics; i++) {
2731 NICInfo *nd = &nd_table[i];
2732
2733 if (!nd->model) {
2734 nd->model = g_strdup("spapr-vlan");
2735 }
2736
2737 if (g_str_equal(nd->model, "spapr-vlan") ||
2738 g_str_equal(nd->model, "ibmveth")) {
2739 spapr_vlan_create(spapr->vio_bus, nd);
2740 } else {
2741 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2742 }
2743 }
2744
2745 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2746 spapr_vscsi_create(spapr->vio_bus);
2747 }
2748
2749
2750 if (spapr_vga_init(phb->bus, &error_fatal)) {
2751 spapr->has_graphics = true;
2752 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2753 }
2754
2755 if (machine->usb) {
2756 if (smc->use_ohci_by_default) {
2757 pci_create_simple(phb->bus, -1, "pci-ohci");
2758 } else {
2759 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2760 }
2761
2762 if (spapr->has_graphics) {
2763 USBBus *usb_bus = usb_bus_find(-1);
2764
2765 usb_create_simple(usb_bus, "usb-kbd");
2766 usb_create_simple(usb_bus, "usb-mouse");
2767 }
2768 }
2769
2770 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
2771 error_report(
2772 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2773 MIN_RMA_SLOF);
2774 exit(1);
2775 }
2776
2777 if (kernel_filename) {
2778 uint64_t lowaddr = 0;
2779
2780 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2781 NULL, NULL, &lowaddr, NULL, 1,
2782 PPC_ELF_MACHINE, 0, 0);
2783 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2784 spapr->kernel_size = load_elf(kernel_filename,
2785 translate_kernel_address, NULL, NULL,
2786 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2787 0, 0);
2788 spapr->kernel_le = spapr->kernel_size > 0;
2789 }
2790 if (spapr->kernel_size < 0) {
2791 error_report("error loading %s: %s", kernel_filename,
2792 load_elf_strerror(spapr->kernel_size));
2793 exit(1);
2794 }
2795
2796
2797 if (initrd_filename) {
2798
2799
2800
2801 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2802 + 0x1ffff) & ~0xffff;
2803 spapr->initrd_size = load_image_targphys(initrd_filename,
2804 spapr->initrd_base,
2805 load_limit
2806 - spapr->initrd_base);
2807 if (spapr->initrd_size < 0) {
2808 error_report("could not load initial ram disk '%s'",
2809 initrd_filename);
2810 exit(1);
2811 }
2812 }
2813 }
2814
2815 if (bios_name == NULL) {
2816 bios_name = FW_FILE_NAME;
2817 }
2818 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2819 if (!filename) {
2820 error_report("Could not find LPAR firmware '%s'", bios_name);
2821 exit(1);
2822 }
2823 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2824 if (fw_size <= 0) {
2825 error_report("Could not load LPAR firmware '%s'", filename);
2826 exit(1);
2827 }
2828 g_free(filename);
2829
2830
2831
2832
2833 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2834 register_savevm_live(NULL, "spapr/htab", -1, 1,
2835 &savevm_htab_handlers, spapr);
2836
2837 qemu_register_boot_set(spapr_boot_set, spapr);
2838
2839 if (kvm_enabled()) {
2840
2841 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2842 &spapr->tb);
2843
2844 kvmppc_spapr_enable_inkernel_multitce();
2845 }
2846}
2847
2848static int spapr_kvm_type(const char *vm_type)
2849{
2850 if (!vm_type) {
2851 return 0;
2852 }
2853
2854 if (!strcmp(vm_type, "HV")) {
2855 return 1;
2856 }
2857
2858 if (!strcmp(vm_type, "PR")) {
2859 return 2;
2860 }
2861
2862 error_report("Unknown kvm-type specified '%s'", vm_type);
2863 exit(1);
2864}
2865
2866
2867
2868
2869
2870static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2871 DeviceState *dev)
2872{
2873#define CAST(type, obj, name) \
2874 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2875 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2876 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2877 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2878
2879 if (d) {
2880 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2881 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2882 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2883
2884 if (spapr) {
2885
2886
2887
2888
2889
2890 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2891 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2892 (uint64_t)id << 48);
2893 } else if (virtio) {
2894
2895
2896
2897
2898
2899
2900
2901 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2902 if (d->lun >= 256) {
2903
2904 id |= 0x4000;
2905 }
2906 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2907 (uint64_t)id << 32);
2908 } else if (usb) {
2909
2910
2911
2912
2913 unsigned usb_port = atoi(usb->port->path);
2914 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2915 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2916 (uint64_t)id << 32);
2917 }
2918 }
2919
2920
2921
2922
2923
2924
2925
2926 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2927 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2928 if (usb_host_dev_is_scsi_storage(usbdev)) {
2929 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2930 }
2931 }
2932
2933 if (phb) {
2934
2935 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2936 }
2937
2938 if (vsc) {
2939
2940 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2941 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2942 }
2943
2944 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2945
2946 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2947 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2948 }
2949
2950 return NULL;
2951}
2952
2953static char *spapr_get_kvm_type(Object *obj, Error **errp)
2954{
2955 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2956
2957 return g_strdup(spapr->kvm_type);
2958}
2959
2960static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2961{
2962 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2963
2964 g_free(spapr->kvm_type);
2965 spapr->kvm_type = g_strdup(value);
2966}
2967
2968static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2969{
2970 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2971
2972 return spapr->use_hotplug_event_source;
2973}
2974
2975static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2976 Error **errp)
2977{
2978 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2979
2980 spapr->use_hotplug_event_source = value;
2981}
2982
2983static bool spapr_get_msix_emulation(Object *obj, Error **errp)
2984{
2985 return true;
2986}
2987
2988static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2989{
2990 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2991
2992 switch (spapr->resize_hpt) {
2993 case SPAPR_RESIZE_HPT_DEFAULT:
2994 return g_strdup("default");
2995 case SPAPR_RESIZE_HPT_DISABLED:
2996 return g_strdup("disabled");
2997 case SPAPR_RESIZE_HPT_ENABLED:
2998 return g_strdup("enabled");
2999 case SPAPR_RESIZE_HPT_REQUIRED:
3000 return g_strdup("required");
3001 }
3002 g_assert_not_reached();
3003}
3004
3005static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3006{
3007 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3008
3009 if (strcmp(value, "default") == 0) {
3010 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3011 } else if (strcmp(value, "disabled") == 0) {
3012 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3013 } else if (strcmp(value, "enabled") == 0) {
3014 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3015 } else if (strcmp(value, "required") == 0) {
3016 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3017 } else {
3018 error_setg(errp, "Bad value for \"resize-hpt\" property");
3019 }
3020}
3021
3022static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3023 void *opaque, Error **errp)
3024{
3025 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3026}
3027
3028static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3029 void *opaque, Error **errp)
3030{
3031 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3032}
3033
3034static void spapr_instance_init(Object *obj)
3035{
3036 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3037
3038 spapr->htab_fd = -1;
3039 spapr->use_hotplug_event_source = true;
3040 object_property_add_str(obj, "kvm-type",
3041 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3042 object_property_set_description(obj, "kvm-type",
3043 "Specifies the KVM virtualization mode (HV, PR)",
3044 NULL);
3045 object_property_add_bool(obj, "modern-hotplug-events",
3046 spapr_get_modern_hotplug_events,
3047 spapr_set_modern_hotplug_events,
3048 NULL);
3049 object_property_set_description(obj, "modern-hotplug-events",
3050 "Use dedicated hotplug event mechanism in"
3051 " place of standard EPOW events when possible"
3052 " (required for memory hot-unplug support)",
3053 NULL);
3054 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3055 "Maximum permitted CPU compatibility mode",
3056 &error_fatal);
3057
3058 object_property_add_str(obj, "resize-hpt",
3059 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3060 object_property_set_description(obj, "resize-hpt",
3061 "Resizing of the Hash Page Table (enabled, disabled, required)",
3062 NULL);
3063 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3064 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3065 object_property_set_description(obj, "vsmt",
3066 "Virtual SMT: KVM behaves as if this were"
3067 " the host's SMT mode", &error_abort);
3068 object_property_add_bool(obj, "vfio-no-msix-emulation",
3069 spapr_get_msix_emulation, NULL, NULL);
3070}
3071
3072static void spapr_machine_finalizefn(Object *obj)
3073{
3074 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3075
3076 g_free(spapr->kvm_type);
3077}
3078
3079void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3080{
3081 cpu_synchronize_state(cs);
3082 ppc_cpu_do_system_reset(cs);
3083}
3084
3085static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3086{
3087 CPUState *cs;
3088
3089 CPU_FOREACH(cs) {
3090 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3091 }
3092}
3093
3094static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3095 uint32_t node, bool dedicated_hp_event_source,
3096 Error **errp)
3097{
3098 sPAPRDRConnector *drc;
3099 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3100 int i, fdt_offset, fdt_size;
3101 void *fdt;
3102 uint64_t addr = addr_start;
3103 bool hotplugged = spapr_drc_hotplugged(dev);
3104 Error *local_err = NULL;
3105
3106 for (i = 0; i < nr_lmbs; i++) {
3107 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3108 addr / SPAPR_MEMORY_BLOCK_SIZE);
3109 g_assert(drc);
3110
3111 fdt = create_device_tree(&fdt_size);
3112 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
3113 SPAPR_MEMORY_BLOCK_SIZE);
3114
3115 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3116 if (local_err) {
3117 while (addr > addr_start) {
3118 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3119 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3120 addr / SPAPR_MEMORY_BLOCK_SIZE);
3121 spapr_drc_detach(drc);
3122 }
3123 g_free(fdt);
3124 error_propagate(errp, local_err);
3125 return;
3126 }
3127 if (!hotplugged) {
3128 spapr_drc_reset(drc);
3129 }
3130 addr += SPAPR_MEMORY_BLOCK_SIZE;
3131 }
3132
3133
3134
3135 if (hotplugged) {
3136 if (dedicated_hp_event_source) {
3137 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3138 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3139 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3140 nr_lmbs,
3141 spapr_drc_index(drc));
3142 } else {
3143 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3144 nr_lmbs);
3145 }
3146 }
3147}
3148
3149static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3150 Error **errp)
3151{
3152 Error *local_err = NULL;
3153 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3154 PCDIMMDevice *dimm = PC_DIMM(dev);
3155 uint64_t size, addr;
3156 uint32_t node;
3157
3158 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3159
3160 pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3161 if (local_err) {
3162 goto out;
3163 }
3164
3165 addr = object_property_get_uint(OBJECT(dimm),
3166 PC_DIMM_ADDR_PROP, &local_err);
3167 if (local_err) {
3168 goto out_unplug;
3169 }
3170
3171 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP,
3172 &error_abort);
3173 spapr_add_lmbs(dev, addr, size, node,
3174 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3175 &local_err);
3176 if (local_err) {
3177 goto out_unplug;
3178 }
3179
3180 return;
3181
3182out_unplug:
3183 pc_dimm_unplug(dimm, MACHINE(ms));
3184out:
3185 error_propagate(errp, local_err);
3186}
3187
3188static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3189 Error **errp)
3190{
3191 const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3192 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3193 PCDIMMDevice *dimm = PC_DIMM(dev);
3194 Error *local_err = NULL;
3195 uint64_t size;
3196 Object *memdev;
3197 hwaddr pagesize;
3198
3199 if (!smc->dr_lmb_enabled) {
3200 error_setg(errp, "Memory hotplug not supported for this machine");
3201 return;
3202 }
3203
3204 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3205 if (local_err) {
3206 error_propagate(errp, local_err);
3207 return;
3208 }
3209
3210 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3211 error_setg(errp, "Hotplugged memory size must be a multiple of "
3212 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3213 return;
3214 }
3215
3216 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3217 &error_abort);
3218 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3219 spapr_check_pagesize(spapr, pagesize, &local_err);
3220 if (local_err) {
3221 error_propagate(errp, local_err);
3222 return;
3223 }
3224
3225 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3226}
3227
3228struct sPAPRDIMMState {
3229 PCDIMMDevice *dimm;
3230 uint32_t nr_lmbs;
3231 QTAILQ_ENTRY(sPAPRDIMMState) next;
3232};
3233
3234static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3235 PCDIMMDevice *dimm)
3236{
3237 sPAPRDIMMState *dimm_state = NULL;
3238
3239 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3240 if (dimm_state->dimm == dimm) {
3241 break;
3242 }
3243 }
3244 return dimm_state;
3245}
3246
3247static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3248 uint32_t nr_lmbs,
3249 PCDIMMDevice *dimm)
3250{
3251 sPAPRDIMMState *ds = NULL;
3252
3253
3254
3255
3256
3257
3258
3259 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3260 if (!ds) {
3261 ds = g_malloc0(sizeof(sPAPRDIMMState));
3262 ds->nr_lmbs = nr_lmbs;
3263 ds->dimm = dimm;
3264 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3265 }
3266 return ds;
3267}
3268
3269static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3270 sPAPRDIMMState *dimm_state)
3271{
3272 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3273 g_free(dimm_state);
3274}
3275
3276static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3277 PCDIMMDevice *dimm)
3278{
3279 sPAPRDRConnector *drc;
3280 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3281 &error_abort);
3282 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3283 uint32_t avail_lmbs = 0;
3284 uint64_t addr_start, addr;
3285 int i;
3286
3287 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3288 &error_abort);
3289
3290 addr = addr_start;
3291 for (i = 0; i < nr_lmbs; i++) {
3292 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3293 addr / SPAPR_MEMORY_BLOCK_SIZE);
3294 g_assert(drc);
3295 if (drc->dev) {
3296 avail_lmbs++;
3297 }
3298 addr += SPAPR_MEMORY_BLOCK_SIZE;
3299 }
3300
3301 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3302}
3303
3304
3305void spapr_lmb_release(DeviceState *dev)
3306{
3307 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3308 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3309 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3310
3311
3312
3313 if (ds == NULL) {
3314 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3315 g_assert(ds);
3316
3317 g_assert(ds->nr_lmbs);
3318 }
3319
3320 if (--ds->nr_lmbs) {
3321 return;
3322 }
3323
3324
3325
3326
3327
3328 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3329}
3330
3331static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3332{
3333 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3334 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3335
3336 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3337 object_unparent(OBJECT(dev));
3338 spapr_pending_dimm_unplugs_remove(spapr, ds);
3339}
3340
3341static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3342 DeviceState *dev, Error **errp)
3343{
3344 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3345 Error *local_err = NULL;
3346 PCDIMMDevice *dimm = PC_DIMM(dev);
3347 uint32_t nr_lmbs;
3348 uint64_t size, addr_start, addr;
3349 int i;
3350 sPAPRDRConnector *drc;
3351
3352 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3353 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3354
3355 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3356 &local_err);
3357 if (local_err) {
3358 goto out;
3359 }
3360
3361
3362
3363
3364
3365
3366
3367 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3368 error_setg(&local_err,
3369 "Memory unplug already in progress for device %s",
3370 dev->id);
3371 goto out;
3372 }
3373
3374 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3375
3376 addr = addr_start;
3377 for (i = 0; i < nr_lmbs; i++) {
3378 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3379 addr / SPAPR_MEMORY_BLOCK_SIZE);
3380 g_assert(drc);
3381
3382 spapr_drc_detach(drc);
3383 addr += SPAPR_MEMORY_BLOCK_SIZE;
3384 }
3385
3386 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3387 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3388 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3389 nr_lmbs, spapr_drc_index(drc));
3390out:
3391 error_propagate(errp, local_err);
3392}
3393
3394static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3395 sPAPRMachineState *spapr)
3396{
3397 PowerPCCPU *cpu = POWERPC_CPU(cs);
3398 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3399 int id = spapr_get_vcpu_id(cpu);
3400 void *fdt;
3401 int offset, fdt_size;
3402 char *nodename;
3403
3404 fdt = create_device_tree(&fdt_size);
3405 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3406 offset = fdt_add_subnode(fdt, 0, nodename);
3407
3408 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3409 g_free(nodename);
3410
3411 *fdt_offset = offset;
3412 return fdt;
3413}
3414
3415
3416void spapr_core_release(DeviceState *dev)
3417{
3418 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3419
3420
3421 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3422}
3423
3424static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3425{
3426 MachineState *ms = MACHINE(hotplug_dev);
3427 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3428 CPUCore *cc = CPU_CORE(dev);
3429 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3430
3431 if (smc->pre_2_10_has_unused_icps) {
3432 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3433 int i;
3434
3435 for (i = 0; i < cc->nr_threads; i++) {
3436 CPUState *cs = CPU(sc->threads[i]);
3437
3438 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3439 }
3440 }
3441
3442 assert(core_slot);
3443 core_slot->cpu = NULL;
3444 object_unparent(OBJECT(dev));
3445}
3446
3447static
3448void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3449 Error **errp)
3450{
3451 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3452 int index;
3453 sPAPRDRConnector *drc;
3454 CPUCore *cc = CPU_CORE(dev);
3455
3456 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3457 error_setg(errp, "Unable to find CPU core with core-id: %d",
3458 cc->core_id);
3459 return;
3460 }
3461 if (index == 0) {
3462 error_setg(errp, "Boot CPU core may not be unplugged");
3463 return;
3464 }
3465
3466 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3467 spapr_vcpu_id(spapr, cc->core_id));
3468 g_assert(drc);
3469
3470 spapr_drc_detach(drc);
3471
3472 spapr_hotplug_req_remove_by_index(drc);
3473}
3474
3475static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3476 Error **errp)
3477{
3478 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3479 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3480 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3481 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3482 CPUCore *cc = CPU_CORE(dev);
3483 CPUState *cs = CPU(core->threads[0]);
3484 sPAPRDRConnector *drc;
3485 Error *local_err = NULL;
3486 CPUArchId *core_slot;
3487 int index;
3488 bool hotplugged = spapr_drc_hotplugged(dev);
3489
3490 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3491 if (!core_slot) {
3492 error_setg(errp, "Unable to find CPU core with core-id: %d",
3493 cc->core_id);
3494 return;
3495 }
3496 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3497 spapr_vcpu_id(spapr, cc->core_id));
3498
3499 g_assert(drc || !mc->has_hotpluggable_cpus);
3500
3501 if (drc) {
3502 void *fdt;
3503 int fdt_offset;
3504
3505 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3506
3507 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3508 if (local_err) {
3509 g_free(fdt);
3510 error_propagate(errp, local_err);
3511 return;
3512 }
3513
3514 if (hotplugged) {
3515
3516
3517
3518
3519 spapr_hotplug_req_add_by_index(drc);
3520 } else {
3521 spapr_drc_reset(drc);
3522 }
3523 }
3524
3525 core_slot->cpu = OBJECT(dev);
3526
3527 if (smc->pre_2_10_has_unused_icps) {
3528 int i;
3529
3530 for (i = 0; i < cc->nr_threads; i++) {
3531 cs = CPU(core->threads[i]);
3532 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3533 }
3534 }
3535}
3536
3537static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3538 Error **errp)
3539{
3540 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3541 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3542 Error *local_err = NULL;
3543 CPUCore *cc = CPU_CORE(dev);
3544 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3545 const char *type = object_get_typename(OBJECT(dev));
3546 CPUArchId *core_slot;
3547 int index;
3548
3549 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3550 error_setg(&local_err, "CPU hotplug not supported for this machine");
3551 goto out;
3552 }
3553
3554 if (strcmp(base_core_type, type)) {
3555 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3556 goto out;
3557 }
3558
3559 if (cc->core_id % smp_threads) {
3560 error_setg(&local_err, "invalid core id %d", cc->core_id);
3561 goto out;
3562 }
3563
3564
3565
3566
3567
3568
3569
3570 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3571 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3572 cc->nr_threads, smp_threads);
3573 goto out;
3574 }
3575
3576 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3577 if (!core_slot) {
3578 error_setg(&local_err, "core id %d out of range", cc->core_id);
3579 goto out;
3580 }
3581
3582 if (core_slot->cpu) {
3583 error_setg(&local_err, "core %d already populated", cc->core_id);
3584 goto out;
3585 }
3586
3587 numa_cpu_pre_plug(core_slot, dev, &local_err);
3588
3589out:
3590 error_propagate(errp, local_err);
3591}
3592
3593static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3594 DeviceState *dev, Error **errp)
3595{
3596 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3597 spapr_memory_plug(hotplug_dev, dev, errp);
3598 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3599 spapr_core_plug(hotplug_dev, dev, errp);
3600 }
3601}
3602
3603static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
3604 DeviceState *dev, Error **errp)
3605{
3606 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3607 spapr_memory_unplug(hotplug_dev, dev);
3608 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3609 spapr_core_unplug(hotplug_dev, dev);
3610 }
3611}
3612
3613static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3614 DeviceState *dev, Error **errp)
3615{
3616 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3617 MachineClass *mc = MACHINE_GET_CLASS(sms);
3618
3619 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3620 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3621 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3622 } else {
3623
3624
3625
3626
3627
3628
3629 error_setg(errp, "Memory hot unplug not supported for this guest");
3630 }
3631 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3632 if (!mc->has_hotpluggable_cpus) {
3633 error_setg(errp, "CPU hot unplug not supported on this machine");
3634 return;
3635 }
3636 spapr_core_unplug_request(hotplug_dev, dev, errp);
3637 }
3638}
3639
3640static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3641 DeviceState *dev, Error **errp)
3642{
3643 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3644 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3645 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3646 spapr_core_pre_plug(hotplug_dev, dev, errp);
3647 }
3648}
3649
3650static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3651 DeviceState *dev)
3652{
3653 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3654 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3655 return HOTPLUG_HANDLER(machine);
3656 }
3657 return NULL;
3658}
3659
3660static CpuInstanceProperties
3661spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3662{
3663 CPUArchId *core_slot;
3664 MachineClass *mc = MACHINE_GET_CLASS(machine);
3665
3666
3667 mc->possible_cpu_arch_ids(machine);
3668
3669 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3670 assert(core_slot);
3671 return core_slot->props;
3672}
3673
3674static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3675{
3676 return idx / smp_cores % nb_numa_nodes;
3677}
3678
3679static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3680{
3681 int i;
3682 const char *core_type;
3683 int spapr_max_cores = max_cpus / smp_threads;
3684 MachineClass *mc = MACHINE_GET_CLASS(machine);
3685
3686 if (!mc->has_hotpluggable_cpus) {
3687 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3688 }
3689 if (machine->possible_cpus) {
3690 assert(machine->possible_cpus->len == spapr_max_cores);
3691 return machine->possible_cpus;
3692 }
3693
3694 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3695 if (!core_type) {
3696 error_report("Unable to find sPAPR CPU Core definition");
3697 exit(1);
3698 }
3699
3700 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3701 sizeof(CPUArchId) * spapr_max_cores);
3702 machine->possible_cpus->len = spapr_max_cores;
3703 for (i = 0; i < machine->possible_cpus->len; i++) {
3704 int core_id = i * smp_threads;
3705
3706 machine->possible_cpus->cpus[i].type = core_type;
3707 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3708 machine->possible_cpus->cpus[i].arch_id = core_id;
3709 machine->possible_cpus->cpus[i].props.has_core_id = true;
3710 machine->possible_cpus->cpus[i].props.core_id = core_id;
3711 }
3712 return machine->possible_cpus;
3713}
3714
3715static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3716 uint64_t *buid, hwaddr *pio,
3717 hwaddr *mmio32, hwaddr *mmio64,
3718 unsigned n_dma, uint32_t *liobns, Error **errp)
3719{
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735 const uint64_t base_buid = 0x800000020000000ULL;
3736#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3737 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3738 int i;
3739
3740
3741 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3742 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3743 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3744 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3745
3746 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3747 SPAPR_PCI_MEM32_WIN_SIZE);
3748 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3749 SPAPR_PCI_MEM64_WIN_SIZE);
3750
3751 if (index >= SPAPR_MAX_PHBS) {
3752 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3753 SPAPR_MAX_PHBS - 1);
3754 return;
3755 }
3756
3757 *buid = base_buid + index;
3758 for (i = 0; i < n_dma; ++i) {
3759 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3760 }
3761
3762 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3763 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3764 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3765}
3766
3767static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3768{
3769 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3770
3771 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3772}
3773
3774static void spapr_ics_resend(XICSFabric *dev)
3775{
3776 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3777
3778 ics_resend(spapr->ics);
3779}
3780
3781static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3782{
3783 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3784
3785 return cpu ? ICP(cpu->intc) : NULL;
3786}
3787
3788static void spapr_pic_print_info(InterruptStatsProvider *obj,
3789 Monitor *mon)
3790{
3791 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3792 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3793
3794 smc->irq->print_info(spapr, mon);
3795}
3796
3797int spapr_get_vcpu_id(PowerPCCPU *cpu)
3798{
3799 return cpu->vcpu_id;
3800}
3801
3802void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3803{
3804 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3805 int vcpu_id;
3806
3807 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
3808
3809 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3810 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3811 error_append_hint(errp, "Adjust the number of cpus to %d "
3812 "or try to raise the number of threads per core\n",
3813 vcpu_id * smp_threads / spapr->vsmt);
3814 return;
3815 }
3816
3817 cpu->vcpu_id = vcpu_id;
3818}
3819
3820PowerPCCPU *spapr_find_cpu(int vcpu_id)
3821{
3822 CPUState *cs;
3823
3824 CPU_FOREACH(cs) {
3825 PowerPCCPU *cpu = POWERPC_CPU(cs);
3826
3827 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
3828 return cpu;
3829 }
3830 }
3831
3832 return NULL;
3833}
3834
3835static void spapr_machine_class_init(ObjectClass *oc, void *data)
3836{
3837 MachineClass *mc = MACHINE_CLASS(oc);
3838 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3839 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3840 NMIClass *nc = NMI_CLASS(oc);
3841 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3842 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3843 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3844 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3845
3846 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3847 mc->ignore_boot_device_suffixes = true;
3848
3849
3850
3851
3852
3853
3854 mc->init = spapr_machine_init;
3855 mc->reset = spapr_machine_reset;
3856 mc->block_default_type = IF_SCSI;
3857 mc->max_cpus = 1024;
3858 mc->no_parallel = 1;
3859 mc->default_boot_order = "";
3860 mc->default_ram_size = 512 * MiB;
3861 mc->default_display = "std";
3862 mc->kvm_type = spapr_kvm_type;
3863 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
3864 mc->pci_allow_0_address = true;
3865 assert(!mc->get_hotplug_handler);
3866 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3867 hc->pre_plug = spapr_machine_device_pre_plug;
3868 hc->plug = spapr_machine_device_plug;
3869 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3870 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3871 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3872 hc->unplug_request = spapr_machine_device_unplug_request;
3873 hc->unplug = spapr_machine_device_unplug;
3874
3875 smc->dr_lmb_enabled = true;
3876 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3877 mc->has_hotpluggable_cpus = true;
3878 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3879 fwc->get_dev_path = spapr_get_fw_dev_path;
3880 nc->nmi_monitor_handler = spapr_nmi;
3881 smc->phb_placement = spapr_phb_placement;
3882 vhc->hypercall = emulate_spapr_hypercall;
3883 vhc->hpt_mask = spapr_hpt_mask;
3884 vhc->map_hptes = spapr_map_hptes;
3885 vhc->unmap_hptes = spapr_unmap_hptes;
3886 vhc->store_hpte = spapr_store_hpte;
3887 vhc->get_patbe = spapr_get_patbe;
3888 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3889 xic->ics_get = spapr_ics_get;
3890 xic->ics_resend = spapr_ics_resend;
3891 xic->icp_get = spapr_icp_get;
3892 ispc->print_info = spapr_pic_print_info;
3893
3894
3895
3896
3897 mc->numa_mem_align_shift = 28;
3898
3899 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
3900 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
3901 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
3902 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
3903 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
3904 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
3905 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16;
3906 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
3907 spapr_caps_add_properties(smc, &error_abort);
3908 smc->irq = &spapr_irq_xics;
3909}
3910
3911static const TypeInfo spapr_machine_info = {
3912 .name = TYPE_SPAPR_MACHINE,
3913 .parent = TYPE_MACHINE,
3914 .abstract = true,
3915 .instance_size = sizeof(sPAPRMachineState),
3916 .instance_init = spapr_instance_init,
3917 .instance_finalize = spapr_machine_finalizefn,
3918 .class_size = sizeof(sPAPRMachineClass),
3919 .class_init = spapr_machine_class_init,
3920 .interfaces = (InterfaceInfo[]) {
3921 { TYPE_FW_PATH_PROVIDER },
3922 { TYPE_NMI },
3923 { TYPE_HOTPLUG_HANDLER },
3924 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3925 { TYPE_XICS_FABRIC },
3926 { TYPE_INTERRUPT_STATS_PROVIDER },
3927 { }
3928 },
3929};
3930
3931#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3932 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3933 void *data) \
3934 { \
3935 MachineClass *mc = MACHINE_CLASS(oc); \
3936 spapr_machine_##suffix##_class_options(mc); \
3937 if (latest) { \
3938 mc->alias = "pseries"; \
3939 mc->is_default = 1; \
3940 } \
3941 } \
3942 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3943 { \
3944 MachineState *machine = MACHINE(obj); \
3945 spapr_machine_##suffix##_instance_options(machine); \
3946 } \
3947 static const TypeInfo spapr_machine_##suffix##_info = { \
3948 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3949 .parent = TYPE_SPAPR_MACHINE, \
3950 .class_init = spapr_machine_##suffix##_class_init, \
3951 .instance_init = spapr_machine_##suffix##_instance_init, \
3952 }; \
3953 static void spapr_machine_register_##suffix(void) \
3954 { \
3955 type_register(&spapr_machine_##suffix##_info); \
3956 } \
3957 type_init(spapr_machine_register_##suffix)
3958
3959
3960
3961
3962static void spapr_machine_3_1_instance_options(MachineState *machine)
3963{
3964}
3965
3966static void spapr_machine_3_1_class_options(MachineClass *mc)
3967{
3968
3969}
3970
3971DEFINE_SPAPR_MACHINE(3_1, "3.1", true);
3972
3973
3974
3975
3976#define SPAPR_COMPAT_3_0 \
3977 HW_COMPAT_3_0
3978
3979static void spapr_machine_3_0_instance_options(MachineState *machine)
3980{
3981 spapr_machine_3_1_instance_options(machine);
3982}
3983
3984static void spapr_machine_3_0_class_options(MachineClass *mc)
3985{
3986 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3987
3988 spapr_machine_3_1_class_options(mc);
3989 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0);
3990
3991 smc->legacy_irq_allocation = true;
3992 smc->irq = &spapr_irq_xics_legacy;
3993}
3994
3995DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
3996
3997
3998
3999
4000#define SPAPR_COMPAT_2_12 \
4001 HW_COMPAT_2_12 \
4002 { \
4003 .driver = TYPE_POWERPC_CPU, \
4004 .property = "pre-3.0-migration", \
4005 .value = "on", \
4006 }, \
4007 { \
4008 .driver = TYPE_SPAPR_CPU_CORE, \
4009 .property = "pre-3.0-migration", \
4010 .value = "on", \
4011 },
4012
4013static void spapr_machine_2_12_instance_options(MachineState *machine)
4014{
4015 spapr_machine_3_0_instance_options(machine);
4016}
4017
4018static void spapr_machine_2_12_class_options(MachineClass *mc)
4019{
4020 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4021
4022 spapr_machine_3_0_class_options(mc);
4023 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12);
4024
4025
4026
4027
4028
4029
4030 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4031}
4032
4033DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4034
4035static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine)
4036{
4037 spapr_machine_2_12_instance_options(machine);
4038}
4039
4040static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4041{
4042 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4043
4044 spapr_machine_2_12_class_options(mc);
4045 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4046 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4047 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4048}
4049
4050DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4051
4052
4053
4054
4055#define SPAPR_COMPAT_2_11 \
4056 HW_COMPAT_2_11
4057
4058static void spapr_machine_2_11_instance_options(MachineState *machine)
4059{
4060 spapr_machine_2_12_instance_options(machine);
4061}
4062
4063static void spapr_machine_2_11_class_options(MachineClass *mc)
4064{
4065 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4066
4067 spapr_machine_2_12_class_options(mc);
4068 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4069 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
4070}
4071
4072DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4073
4074
4075
4076
4077#define SPAPR_COMPAT_2_10 \
4078 HW_COMPAT_2_10
4079
4080static void spapr_machine_2_10_instance_options(MachineState *machine)
4081{
4082 spapr_machine_2_11_instance_options(machine);
4083}
4084
4085static void spapr_machine_2_10_class_options(MachineClass *mc)
4086{
4087 spapr_machine_2_11_class_options(mc);
4088 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
4089}
4090
4091DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4092
4093
4094
4095
4096#define SPAPR_COMPAT_2_9 \
4097 HW_COMPAT_2_9 \
4098 { \
4099 .driver = TYPE_POWERPC_CPU, \
4100 .property = "pre-2.10-migration", \
4101 .value = "on", \
4102 }, \
4103
4104static void spapr_machine_2_9_instance_options(MachineState *machine)
4105{
4106 spapr_machine_2_10_instance_options(machine);
4107}
4108
4109static void spapr_machine_2_9_class_options(MachineClass *mc)
4110{
4111 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4112
4113 spapr_machine_2_10_class_options(mc);
4114 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4115 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4116 smc->pre_2_10_has_unused_icps = true;
4117 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4118}
4119
4120DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4121
4122
4123
4124
4125#define SPAPR_COMPAT_2_8 \
4126 HW_COMPAT_2_8 \
4127 { \
4128 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4129 .property = "pcie-extended-configuration-space", \
4130 .value = "off", \
4131 },
4132
4133static void spapr_machine_2_8_instance_options(MachineState *machine)
4134{
4135 spapr_machine_2_9_instance_options(machine);
4136}
4137
4138static void spapr_machine_2_8_class_options(MachineClass *mc)
4139{
4140 spapr_machine_2_9_class_options(mc);
4141 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4142 mc->numa_mem_align_shift = 23;
4143}
4144
4145DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4146
4147
4148
4149
4150#define SPAPR_COMPAT_2_7 \
4151 HW_COMPAT_2_7 \
4152 { \
4153 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4154 .property = "mem_win_size", \
4155 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4156 }, \
4157 { \
4158 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4159 .property = "mem64_win_size", \
4160 .value = "0", \
4161 }, \
4162 { \
4163 .driver = TYPE_POWERPC_CPU, \
4164 .property = "pre-2.8-migration", \
4165 .value = "on", \
4166 }, \
4167 { \
4168 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4169 .property = "pre-2.8-migration", \
4170 .value = "on", \
4171 },
4172
4173static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4174 uint64_t *buid, hwaddr *pio,
4175 hwaddr *mmio32, hwaddr *mmio64,
4176 unsigned n_dma, uint32_t *liobns, Error **errp)
4177{
4178
4179 const uint64_t base_buid = 0x800000020000000ULL;
4180 const hwaddr phb_spacing = 0x1000000000ULL;
4181 const hwaddr mmio_offset = 0xa0000000;
4182 const hwaddr pio_offset = 0x80000000;
4183 const uint32_t max_index = 255;
4184 const hwaddr phb0_alignment = 0x10000000000ULL;
4185
4186 uint64_t ram_top = MACHINE(spapr)->ram_size;
4187 hwaddr phb0_base, phb_base;
4188 int i;
4189
4190
4191 if (MACHINE(spapr)->maxram_size > ram_top) {
4192
4193
4194
4195 ram_top = MACHINE(spapr)->device_memory->base +
4196 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4197 }
4198
4199 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4200
4201 if (index > max_index) {
4202 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4203 max_index);
4204 return;
4205 }
4206
4207 *buid = base_buid + index;
4208 for (i = 0; i < n_dma; ++i) {
4209 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4210 }
4211
4212 phb_base = phb0_base + index * phb_spacing;
4213 *pio = phb_base + pio_offset;
4214 *mmio32 = phb_base + mmio_offset;
4215
4216
4217
4218
4219
4220}
4221
4222static void spapr_machine_2_7_instance_options(MachineState *machine)
4223{
4224 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4225
4226 spapr_machine_2_8_instance_options(machine);
4227 spapr->use_hotplug_event_source = false;
4228}
4229
4230static void spapr_machine_2_7_class_options(MachineClass *mc)
4231{
4232 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4233
4234 spapr_machine_2_8_class_options(mc);
4235 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4236 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4237 smc->phb_placement = phb_placement_2_7;
4238}
4239
4240DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4241
4242
4243
4244
4245#define SPAPR_COMPAT_2_6 \
4246 HW_COMPAT_2_6 \
4247 { \
4248 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4249 .property = "ddw",\
4250 .value = stringify(off),\
4251 },
4252
4253static void spapr_machine_2_6_instance_options(MachineState *machine)
4254{
4255 spapr_machine_2_7_instance_options(machine);
4256}
4257
4258static void spapr_machine_2_6_class_options(MachineClass *mc)
4259{
4260 spapr_machine_2_7_class_options(mc);
4261 mc->has_hotpluggable_cpus = false;
4262 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4263}
4264
4265DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4266
4267
4268
4269
4270#define SPAPR_COMPAT_2_5 \
4271 HW_COMPAT_2_5 \
4272 { \
4273 .driver = "spapr-vlan", \
4274 .property = "use-rx-buffer-pools", \
4275 .value = "off", \
4276 },
4277
4278static void spapr_machine_2_5_instance_options(MachineState *machine)
4279{
4280 spapr_machine_2_6_instance_options(machine);
4281}
4282
4283static void spapr_machine_2_5_class_options(MachineClass *mc)
4284{
4285 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4286
4287 spapr_machine_2_6_class_options(mc);
4288 smc->use_ohci_by_default = true;
4289 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4290}
4291
4292DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4293
4294
4295
4296
4297#define SPAPR_COMPAT_2_4 \
4298 HW_COMPAT_2_4
4299
4300static void spapr_machine_2_4_instance_options(MachineState *machine)
4301{
4302 spapr_machine_2_5_instance_options(machine);
4303}
4304
4305static void spapr_machine_2_4_class_options(MachineClass *mc)
4306{
4307 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4308
4309 spapr_machine_2_5_class_options(mc);
4310 smc->dr_lmb_enabled = false;
4311 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4312}
4313
4314DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4315
4316
4317
4318
4319#define SPAPR_COMPAT_2_3 \
4320 HW_COMPAT_2_3 \
4321 {\
4322 .driver = "spapr-pci-host-bridge",\
4323 .property = "dynamic-reconfiguration",\
4324 .value = "off",\
4325 },
4326
4327static void spapr_machine_2_3_instance_options(MachineState *machine)
4328{
4329 spapr_machine_2_4_instance_options(machine);
4330}
4331
4332static void spapr_machine_2_3_class_options(MachineClass *mc)
4333{
4334 spapr_machine_2_4_class_options(mc);
4335 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4336}
4337DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4338
4339
4340
4341
4342
4343#define SPAPR_COMPAT_2_2 \
4344 HW_COMPAT_2_2 \
4345 {\
4346 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4347 .property = "mem_win_size",\
4348 .value = "0x20000000",\
4349 },
4350
4351static void spapr_machine_2_2_instance_options(MachineState *machine)
4352{
4353 spapr_machine_2_3_instance_options(machine);
4354 machine->suppress_vmdesc = true;
4355}
4356
4357static void spapr_machine_2_2_class_options(MachineClass *mc)
4358{
4359 spapr_machine_2_3_class_options(mc);
4360 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4361}
4362DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4363
4364
4365
4366
4367#define SPAPR_COMPAT_2_1 \
4368 HW_COMPAT_2_1
4369
4370static void spapr_machine_2_1_instance_options(MachineState *machine)
4371{
4372 spapr_machine_2_2_instance_options(machine);
4373}
4374
4375static void spapr_machine_2_1_class_options(MachineClass *mc)
4376{
4377 spapr_machine_2_2_class_options(mc);
4378 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4379}
4380DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4381
4382static void spapr_machine_register_types(void)
4383{
4384 type_register_static(&spapr_machine_info);
4385}
4386
4387type_init(spapr_machine_register_types)
4388