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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu-common.h"
28#include "cpu.h"
29#include "hw/hw.h"
30#include "hw/sysbus.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/msi.h"
33#include "hw/pci/msix.h"
34#include "hw/pci/pci_host.h"
35#include "hw/ppc/spapr.h"
36#include "hw/pci-host/spapr.h"
37#include "exec/address-spaces.h"
38#include "exec/ram_addr.h"
39#include <libfdt.h>
40#include "trace.h"
41#include "qemu/error-report.h"
42#include "qapi/qmp/qerror.h"
43#include "hw/ppc/fdt.h"
44#include "hw/pci/pci_bridge.h"
45#include "hw/pci/pci_bus.h"
46#include "hw/pci/pci_ids.h"
47#include "hw/ppc/spapr_drc.h"
48#include "sysemu/device_tree.h"
49#include "sysemu/kvm.h"
50#include "sysemu/hostmem.h"
51#include "sysemu/numa.h"
52
53
54#define RTAS_QUERY_FN 0
55#define RTAS_CHANGE_FN 1
56#define RTAS_RESET_FN 2
57#define RTAS_CHANGE_MSI_FN 3
58#define RTAS_CHANGE_MSIX_FN 4
59
60
61#define RTAS_TYPE_MSI 1
62#define RTAS_TYPE_MSIX 2
63
64sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid)
65{
66 sPAPRPHBState *sphb;
67
68 QLIST_FOREACH(sphb, &spapr->phbs, list) {
69 if (sphb->buid != buid) {
70 continue;
71 }
72 return sphb;
73 }
74
75 return NULL;
76}
77
78PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
79 uint32_t config_addr)
80{
81 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
82 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
83 int bus_num = (config_addr >> 16) & 0xFF;
84 int devfn = (config_addr >> 8) & 0xFF;
85
86 if (!phb) {
87 return NULL;
88 }
89
90 return pci_find_device(phb->bus, bus_num, devfn);
91}
92
93static uint32_t rtas_pci_cfgaddr(uint32_t arg)
94{
95
96 return ((arg >> 20) & 0xf00) | (arg & 0xff);
97}
98
99static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid,
100 uint32_t addr, uint32_t size,
101 target_ulong rets)
102{
103 PCIDevice *pci_dev;
104 uint32_t val;
105
106 if ((size != 1) && (size != 2) && (size != 4)) {
107
108 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
109 return;
110 }
111
112 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
113 addr = rtas_pci_cfgaddr(addr);
114
115 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
116
117
118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119 return;
120 }
121
122 val = pci_host_config_read_common(pci_dev, addr,
123 pci_config_size(pci_dev), size);
124
125 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
126 rtas_st(rets, 1, val);
127}
128
129static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
130 uint32_t token, uint32_t nargs,
131 target_ulong args,
132 uint32_t nret, target_ulong rets)
133{
134 uint64_t buid;
135 uint32_t size, addr;
136
137 if ((nargs != 4) || (nret != 2)) {
138 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
139 return;
140 }
141
142 buid = rtas_ldq(args, 1);
143 size = rtas_ld(args, 3);
144 addr = rtas_ld(args, 0);
145
146 finish_read_pci_config(spapr, buid, addr, size, rets);
147}
148
149static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
150 uint32_t token, uint32_t nargs,
151 target_ulong args,
152 uint32_t nret, target_ulong rets)
153{
154 uint32_t size, addr;
155
156 if ((nargs != 2) || (nret != 2)) {
157 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
158 return;
159 }
160
161 size = rtas_ld(args, 1);
162 addr = rtas_ld(args, 0);
163
164 finish_read_pci_config(spapr, 0, addr, size, rets);
165}
166
167static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid,
168 uint32_t addr, uint32_t size,
169 uint32_t val, target_ulong rets)
170{
171 PCIDevice *pci_dev;
172
173 if ((size != 1) && (size != 2) && (size != 4)) {
174
175 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
176 return;
177 }
178
179 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
180 addr = rtas_pci_cfgaddr(addr);
181
182 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
183
184
185 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
186 return;
187 }
188
189 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
190 val, size);
191
192 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
193}
194
195static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
196 uint32_t token, uint32_t nargs,
197 target_ulong args,
198 uint32_t nret, target_ulong rets)
199{
200 uint64_t buid;
201 uint32_t val, size, addr;
202
203 if ((nargs != 5) || (nret != 1)) {
204 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
205 return;
206 }
207
208 buid = rtas_ldq(args, 1);
209 val = rtas_ld(args, 4);
210 size = rtas_ld(args, 3);
211 addr = rtas_ld(args, 0);
212
213 finish_write_pci_config(spapr, buid, addr, size, val, rets);
214}
215
216static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
217 uint32_t token, uint32_t nargs,
218 target_ulong args,
219 uint32_t nret, target_ulong rets)
220{
221 uint32_t val, size, addr;
222
223 if ((nargs != 3) || (nret != 1)) {
224 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
225 return;
226 }
227
228
229 val = rtas_ld(args, 2);
230 size = rtas_ld(args, 1);
231 addr = rtas_ld(args, 0);
232
233 finish_write_pci_config(spapr, 0, addr, size, val, rets);
234}
235
236
237
238
239
240
241
242
243
244static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
245 unsigned first_irq, unsigned req_num)
246{
247 unsigned i;
248 MSIMessage msg = { .address = addr, .data = first_irq };
249
250 if (!msix) {
251 msi_set_message(pdev, msg);
252 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
253 return;
254 }
255
256 for (i = 0; i < req_num; ++i) {
257 msix_set_message(pdev, i, msg);
258 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
259 if (addr) {
260 ++msg.data;
261 }
262 }
263}
264
265static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
266 uint32_t token, uint32_t nargs,
267 target_ulong args, uint32_t nret,
268 target_ulong rets)
269{
270 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
271 uint32_t config_addr = rtas_ld(args, 0);
272 uint64_t buid = rtas_ldq(args, 1);
273 unsigned int func = rtas_ld(args, 3);
274 unsigned int req_num = rtas_ld(args, 4);
275 unsigned int seq_num = rtas_ld(args, 5);
276 unsigned int ret_intr_type;
277 unsigned int irq, max_irqs = 0;
278 sPAPRPHBState *phb = NULL;
279 PCIDevice *pdev = NULL;
280 spapr_pci_msi *msi;
281 int *config_addr_key;
282 Error *err = NULL;
283 int i;
284
285
286 phb = spapr_pci_find_phb(spapr, buid);
287 if (phb) {
288 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
289 }
290 if (!phb || !pdev) {
291 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
292 return;
293 }
294
295 switch (func) {
296 case RTAS_CHANGE_FN:
297 if (msi_present(pdev)) {
298 ret_intr_type = RTAS_TYPE_MSI;
299 } else if (msix_present(pdev)) {
300 ret_intr_type = RTAS_TYPE_MSIX;
301 } else {
302 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
303 return;
304 }
305 break;
306 case RTAS_CHANGE_MSI_FN:
307 if (msi_present(pdev)) {
308 ret_intr_type = RTAS_TYPE_MSI;
309 } else {
310 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
311 return;
312 }
313 break;
314 case RTAS_CHANGE_MSIX_FN:
315 if (msix_present(pdev)) {
316 ret_intr_type = RTAS_TYPE_MSIX;
317 } else {
318 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
319 return;
320 }
321 break;
322 default:
323 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
324 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
325 return;
326 }
327
328 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
329
330
331 if (!req_num) {
332 if (!msi) {
333 trace_spapr_pci_msi("Releasing wrong config", config_addr);
334 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
335 return;
336 }
337
338 if (!smc->legacy_irq_allocation) {
339 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
340 }
341 spapr_irq_free(spapr, msi->first_irq, msi->num);
342 if (msi_present(pdev)) {
343 spapr_msi_setmsg(pdev, 0, false, 0, 0);
344 }
345 if (msix_present(pdev)) {
346 spapr_msi_setmsg(pdev, 0, true, 0, 0);
347 }
348 g_hash_table_remove(phb->msi, &config_addr);
349
350 trace_spapr_pci_msi("Released MSIs", config_addr);
351 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
352 rtas_st(rets, 1, 0);
353 return;
354 }
355
356
357
358
359 if (ret_intr_type == RTAS_TYPE_MSI) {
360 max_irqs = msi_nr_vectors_allocated(pdev);
361 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
362 max_irqs = pdev->msix_entries_nr;
363 }
364 if (!max_irqs) {
365 error_report("Requested interrupt type %d is not enabled for device %x",
366 ret_intr_type, config_addr);
367 rtas_st(rets, 0, -1);
368 return;
369 }
370
371 if (req_num > max_irqs) {
372 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
373 req_num = max_irqs;
374 irq = 0;
375 goto out;
376 }
377
378
379 if (smc->legacy_irq_allocation) {
380 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
381 &err);
382 } else {
383 irq = spapr_irq_msi_alloc(spapr, req_num,
384 ret_intr_type == RTAS_TYPE_MSI, &err);
385 }
386 if (err) {
387 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
388 config_addr);
389 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
390 return;
391 }
392
393 for (i = 0; i < req_num; i++) {
394 spapr_irq_claim(spapr, irq + i, false, &err);
395 if (err) {
396 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
397 config_addr);
398 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
399 return;
400 }
401 }
402
403
404 if (msi) {
405 if (!smc->legacy_irq_allocation) {
406 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
407 }
408 spapr_irq_free(spapr, msi->first_irq, msi->num);
409 g_hash_table_remove(phb->msi, &config_addr);
410 }
411
412
413 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
414 irq, req_num);
415
416
417 msi = g_new(spapr_pci_msi, 1);
418 msi->first_irq = irq;
419 msi->num = req_num;
420 config_addr_key = g_new(int, 1);
421 *config_addr_key = config_addr;
422 g_hash_table_insert(phb->msi, config_addr_key, msi);
423
424out:
425 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
426 rtas_st(rets, 1, req_num);
427 rtas_st(rets, 2, ++seq_num);
428 if (nret > 3) {
429 rtas_st(rets, 3, ret_intr_type);
430 }
431
432 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
433}
434
435static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
436 sPAPRMachineState *spapr,
437 uint32_t token,
438 uint32_t nargs,
439 target_ulong args,
440 uint32_t nret,
441 target_ulong rets)
442{
443 uint32_t config_addr = rtas_ld(args, 0);
444 uint64_t buid = rtas_ldq(args, 1);
445 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
446 sPAPRPHBState *phb = NULL;
447 PCIDevice *pdev = NULL;
448 spapr_pci_msi *msi;
449
450
451 phb = spapr_pci_find_phb(spapr, buid);
452 if (phb) {
453 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
454 }
455 if (!phb || !pdev) {
456 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
457 return;
458 }
459
460
461 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
462 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
463 trace_spapr_pci_msi("Failed to return vector", config_addr);
464 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
465 return;
466 }
467 intr_src_num = msi->first_irq + ioa_intr_num;
468 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
469 intr_src_num);
470
471 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
472 rtas_st(rets, 1, intr_src_num);
473 rtas_st(rets, 2, 1);
474}
475
476static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
477 sPAPRMachineState *spapr,
478 uint32_t token, uint32_t nargs,
479 target_ulong args, uint32_t nret,
480 target_ulong rets)
481{
482 sPAPRPHBState *sphb;
483 uint32_t addr, option;
484 uint64_t buid;
485 int ret;
486
487 if ((nargs != 4) || (nret != 1)) {
488 goto param_error_exit;
489 }
490
491 buid = rtas_ldq(args, 1);
492 addr = rtas_ld(args, 0);
493 option = rtas_ld(args, 3);
494
495 sphb = spapr_pci_find_phb(spapr, buid);
496 if (!sphb) {
497 goto param_error_exit;
498 }
499
500 if (!spapr_phb_eeh_available(sphb)) {
501 goto param_error_exit;
502 }
503
504 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
505 rtas_st(rets, 0, ret);
506 return;
507
508param_error_exit:
509 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
510}
511
512static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
513 sPAPRMachineState *spapr,
514 uint32_t token, uint32_t nargs,
515 target_ulong args, uint32_t nret,
516 target_ulong rets)
517{
518 sPAPRPHBState *sphb;
519 PCIDevice *pdev;
520 uint32_t addr, option;
521 uint64_t buid;
522
523 if ((nargs != 4) || (nret != 2)) {
524 goto param_error_exit;
525 }
526
527 buid = rtas_ldq(args, 1);
528 sphb = spapr_pci_find_phb(spapr, buid);
529 if (!sphb) {
530 goto param_error_exit;
531 }
532
533 if (!spapr_phb_eeh_available(sphb)) {
534 goto param_error_exit;
535 }
536
537
538
539
540
541 option = rtas_ld(args, 3);
542 switch (option) {
543 case RTAS_GET_PE_ADDR:
544 addr = rtas_ld(args, 0);
545 pdev = spapr_pci_find_dev(spapr, buid, addr);
546 if (!pdev) {
547 goto param_error_exit;
548 }
549
550 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
551 break;
552 case RTAS_GET_PE_MODE:
553 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
554 break;
555 default:
556 goto param_error_exit;
557 }
558
559 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
560 return;
561
562param_error_exit:
563 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
564}
565
566static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
567 sPAPRMachineState *spapr,
568 uint32_t token, uint32_t nargs,
569 target_ulong args, uint32_t nret,
570 target_ulong rets)
571{
572 sPAPRPHBState *sphb;
573 uint64_t buid;
574 int state, ret;
575
576 if ((nargs != 3) || (nret != 4 && nret != 5)) {
577 goto param_error_exit;
578 }
579
580 buid = rtas_ldq(args, 1);
581 sphb = spapr_pci_find_phb(spapr, buid);
582 if (!sphb) {
583 goto param_error_exit;
584 }
585
586 if (!spapr_phb_eeh_available(sphb)) {
587 goto param_error_exit;
588 }
589
590 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
591 rtas_st(rets, 0, ret);
592 if (ret != RTAS_OUT_SUCCESS) {
593 return;
594 }
595
596 rtas_st(rets, 1, state);
597 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
598 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
599 if (nret >= 5) {
600 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
601 }
602 return;
603
604param_error_exit:
605 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
606}
607
608static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
609 sPAPRMachineState *spapr,
610 uint32_t token, uint32_t nargs,
611 target_ulong args, uint32_t nret,
612 target_ulong rets)
613{
614 sPAPRPHBState *sphb;
615 uint32_t option;
616 uint64_t buid;
617 int ret;
618
619 if ((nargs != 4) || (nret != 1)) {
620 goto param_error_exit;
621 }
622
623 buid = rtas_ldq(args, 1);
624 option = rtas_ld(args, 3);
625 sphb = spapr_pci_find_phb(spapr, buid);
626 if (!sphb) {
627 goto param_error_exit;
628 }
629
630 if (!spapr_phb_eeh_available(sphb)) {
631 goto param_error_exit;
632 }
633
634 ret = spapr_phb_vfio_eeh_reset(sphb, option);
635 rtas_st(rets, 0, ret);
636 return;
637
638param_error_exit:
639 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
640}
641
642static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
643 sPAPRMachineState *spapr,
644 uint32_t token, uint32_t nargs,
645 target_ulong args, uint32_t nret,
646 target_ulong rets)
647{
648 sPAPRPHBState *sphb;
649 uint64_t buid;
650 int ret;
651
652 if ((nargs != 3) || (nret != 1)) {
653 goto param_error_exit;
654 }
655
656 buid = rtas_ldq(args, 1);
657 sphb = spapr_pci_find_phb(spapr, buid);
658 if (!sphb) {
659 goto param_error_exit;
660 }
661
662 if (!spapr_phb_eeh_available(sphb)) {
663 goto param_error_exit;
664 }
665
666 ret = spapr_phb_vfio_eeh_configure(sphb);
667 rtas_st(rets, 0, ret);
668 return;
669
670param_error_exit:
671 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
672}
673
674
675static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
676 sPAPRMachineState *spapr,
677 uint32_t token, uint32_t nargs,
678 target_ulong args, uint32_t nret,
679 target_ulong rets)
680{
681 sPAPRPHBState *sphb;
682 int option;
683 uint64_t buid;
684
685 if ((nargs != 8) || (nret != 1)) {
686 goto param_error_exit;
687 }
688
689 buid = rtas_ldq(args, 1);
690 sphb = spapr_pci_find_phb(spapr, buid);
691 if (!sphb) {
692 goto param_error_exit;
693 }
694
695 if (!spapr_phb_eeh_available(sphb)) {
696 goto param_error_exit;
697 }
698
699 option = rtas_ld(args, 7);
700 switch (option) {
701 case RTAS_SLOT_TEMP_ERR_LOG:
702 case RTAS_SLOT_PERM_ERR_LOG:
703 break;
704 default:
705 goto param_error_exit;
706 }
707
708
709 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
710 return;
711
712param_error_exit:
713 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
714}
715
716static int pci_spapr_swizzle(int slot, int pin)
717{
718 return (slot + pin) % PCI_NUM_PINS;
719}
720
721static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
722{
723
724
725
726
727
728
729 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
730}
731
732static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
733{
734
735
736
737
738 sPAPRPHBState *phb = opaque;
739
740 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
741 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
742}
743
744static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
745{
746 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
747 PCIINTxRoute route;
748
749 route.mode = PCI_INTX_ENABLED;
750 route.irq = sphb->lsi_table[pin].irq;
751
752 return route;
753}
754
755
756
757
758
759
760static void spapr_msi_write(void *opaque, hwaddr addr,
761 uint64_t data, unsigned size)
762{
763 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
764 uint32_t irq = data;
765
766 trace_spapr_pci_msi_write(addr, data, irq);
767
768 qemu_irq_pulse(spapr_qirq(spapr, irq));
769}
770
771static const MemoryRegionOps spapr_msi_ops = {
772
773 .read = NULL,
774 .write = spapr_msi_write,
775 .endianness = DEVICE_LITTLE_ENDIAN
776};
777
778
779
780
781static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
782{
783 sPAPRPHBState *phb = opaque;
784
785 return &phb->iommu_as;
786}
787
788static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
789{
790 char *path = NULL, *buf = NULL, *host = NULL;
791
792
793 host = object_property_get_str(OBJECT(pdev), "host", NULL);
794 if (!host) {
795 goto err_out;
796 }
797
798
799 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
800 g_free(host);
801 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
802 goto err_out;
803 }
804 g_free(path);
805
806
807 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
808 g_free(buf);
809 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
810 goto err_out;
811 }
812 return buf;
813
814err_out:
815 g_free(path);
816 return NULL;
817}
818
819static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
820{
821 char *buf;
822 const char *devtype = "qemu";
823 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
824
825 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
826 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
827 if (buf) {
828 return buf;
829 }
830 devtype = "vfio";
831 }
832
833
834
835
836 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
837 devtype, pdev->name, sphb->index, busnr,
838 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
839 return buf;
840}
841
842
843#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
844#define b_n(x) b_x((x), 31, 1)
845#define b_p(x) b_x((x), 30, 1)
846#define b_t(x) b_x((x), 29, 1)
847#define b_ss(x) b_x((x), 24, 2)
848#define b_bbbbbbbb(x) b_x((x), 16, 8)
849#define b_ddddd(x) b_x((x), 11, 5)
850#define b_fff(x) b_x((x), 8, 3)
851#define b_rrrrrrrr(x) b_x((x), 0, 8)
852
853
854#define RESOURCE_CELLS_SIZE 2
855#define RESOURCE_CELLS_ADDRESS 3
856
857typedef struct ResourceFields {
858 uint32_t phys_hi;
859 uint32_t phys_mid;
860 uint32_t phys_lo;
861 uint32_t size_hi;
862 uint32_t size_lo;
863} QEMU_PACKED ResourceFields;
864
865typedef struct ResourceProps {
866 ResourceFields reg[8];
867 ResourceFields assigned[7];
868 uint32_t reg_len;
869 uint32_t assigned_len;
870} ResourceProps;
871
872
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922
923
924
925static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
926{
927 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
928 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
929 b_ddddd(PCI_SLOT(d->devfn)) |
930 b_fff(PCI_FUNC(d->devfn)));
931 ResourceFields *reg, *assigned;
932 int i, reg_idx = 0, assigned_idx = 0;
933
934
935 reg = &rp->reg[reg_idx++];
936 reg->phys_hi = cpu_to_be32(dev_id);
937 reg->phys_mid = 0;
938 reg->phys_lo = 0;
939 reg->size_hi = 0;
940 reg->size_lo = 0;
941
942 for (i = 0; i < PCI_NUM_REGIONS; i++) {
943 if (!d->io_regions[i].size) {
944 continue;
945 }
946
947 reg = &rp->reg[reg_idx++];
948
949 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
950 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
951 reg->phys_hi |= cpu_to_be32(b_ss(1));
952 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
953 reg->phys_hi |= cpu_to_be32(b_ss(3));
954 } else {
955 reg->phys_hi |= cpu_to_be32(b_ss(2));
956 }
957 reg->phys_mid = 0;
958 reg->phys_lo = 0;
959 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
960 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
961
962 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
963 continue;
964 }
965
966 assigned = &rp->assigned[assigned_idx++];
967 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1));
968 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
969 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
970 assigned->size_hi = reg->size_hi;
971 assigned->size_lo = reg->size_lo;
972 }
973
974 rp->reg_len = reg_idx * sizeof(ResourceFields);
975 rp->assigned_len = assigned_idx * sizeof(ResourceFields);
976}
977
978typedef struct PCIClass PCIClass;
979typedef struct PCISubClass PCISubClass;
980typedef struct PCIIFace PCIIFace;
981
982struct PCIIFace {
983 int iface;
984 const char *name;
985};
986
987struct PCISubClass {
988 int subclass;
989 const char *name;
990 const PCIIFace *iface;
991};
992
993struct PCIClass {
994 const char *name;
995 const PCISubClass *subc;
996};
997
998static const PCISubClass undef_subclass[] = {
999 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
1000 { 0xFF, NULL, NULL },
1001};
1002
1003static const PCISubClass mass_subclass[] = {
1004 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
1005 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
1006 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
1007 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
1008 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
1009 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
1010 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
1011 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
1012 { 0xFF, NULL, NULL },
1013};
1014
1015static const PCISubClass net_subclass[] = {
1016 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
1017 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
1018 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
1019 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
1020 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
1021 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
1022 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
1023 { 0xFF, NULL, NULL },
1024};
1025
1026static const PCISubClass displ_subclass[] = {
1027 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
1028 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
1029 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
1030 { 0xFF, NULL, NULL },
1031};
1032
1033static const PCISubClass media_subclass[] = {
1034 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1035 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1036 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1037 { 0xFF, NULL, NULL },
1038};
1039
1040static const PCISubClass mem_subclass[] = {
1041 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1042 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1043 { 0xFF, NULL, NULL },
1044};
1045
1046static const PCISubClass bridg_subclass[] = {
1047 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1048 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1049 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1050 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1051 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1052 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1053 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1054 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1055 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1056 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1057 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1058 { 0xFF, NULL, NULL },
1059};
1060
1061static const PCISubClass comm_subclass[] = {
1062 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1063 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1064 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1065 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1066 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1067 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1068 { 0xFF, NULL, NULL, },
1069};
1070
1071static const PCIIFace pic_iface[] = {
1072 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1073 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1074 { 0xFF, NULL },
1075};
1076
1077static const PCISubClass sys_subclass[] = {
1078 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1079 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1080 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1081 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1082 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1083 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1084 { 0xFF, NULL, NULL },
1085};
1086
1087static const PCISubClass inp_subclass[] = {
1088 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1089 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1090 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1091 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1092 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1093 { 0xFF, NULL, NULL },
1094};
1095
1096static const PCISubClass dock_subclass[] = {
1097 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1098 { 0xFF, NULL, NULL },
1099};
1100
1101static const PCISubClass cpu_subclass[] = {
1102 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1103 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1104 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1105 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1106 { 0xFF, NULL, NULL },
1107};
1108
1109static const PCIIFace usb_iface[] = {
1110 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1111 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1112 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1113 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1114 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1115 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1116 { 0xFF, NULL },
1117};
1118
1119static const PCISubClass ser_subclass[] = {
1120 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1121 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1122 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1123 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1124 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1125 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1126 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1127 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1128 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1129 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1130 { 0xFF, NULL, NULL },
1131};
1132
1133static const PCISubClass wrl_subclass[] = {
1134 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1135 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1136 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1137 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1138 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1139 { 0xFF, NULL, NULL },
1140};
1141
1142static const PCISubClass sat_subclass[] = {
1143 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1144 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1145 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1146 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1147 { 0xFF, NULL, NULL },
1148};
1149
1150static const PCISubClass crypt_subclass[] = {
1151 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1152 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1153 "entertainment-encryption", NULL },
1154 { 0xFF, NULL, NULL },
1155};
1156
1157static const PCISubClass spc_subclass[] = {
1158 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1159 { PCI_CLASS_SP_PERF, "counter", NULL },
1160 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1161 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1162 { 0xFF, NULL, NULL },
1163};
1164
1165static const PCIClass pci_classes[] = {
1166 { "legacy-device", undef_subclass },
1167 { "mass-storage", mass_subclass },
1168 { "network", net_subclass },
1169 { "display", displ_subclass, },
1170 { "multimedia-device", media_subclass },
1171 { "memory-controller", mem_subclass },
1172 { "unknown-bridge", bridg_subclass },
1173 { "communication-controller", comm_subclass},
1174 { "system-peripheral", sys_subclass },
1175 { "input-controller", inp_subclass },
1176 { "docking-station", dock_subclass },
1177 { "cpu", cpu_subclass },
1178 { "serial-bus", ser_subclass },
1179 { "wireless-controller", wrl_subclass },
1180 { "intelligent-io", NULL },
1181 { "satellite-device", sat_subclass },
1182 { "encryption", crypt_subclass },
1183 { "data-processing-controller", spc_subclass },
1184};
1185
1186static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1187 uint8_t iface)
1188{
1189 const PCIClass *pclass;
1190 const PCISubClass *psubclass;
1191 const PCIIFace *piface;
1192 const char *name;
1193
1194 if (class >= ARRAY_SIZE(pci_classes)) {
1195 return "pci";
1196 }
1197
1198 pclass = pci_classes + class;
1199 name = pclass->name;
1200
1201 if (pclass->subc == NULL) {
1202 return name;
1203 }
1204
1205 psubclass = pclass->subc;
1206 while ((psubclass->subclass & 0xff) != 0xff) {
1207 if ((psubclass->subclass & 0xff) == subclass) {
1208 name = psubclass->name;
1209 break;
1210 }
1211 psubclass++;
1212 }
1213
1214 piface = psubclass->iface;
1215 if (piface == NULL) {
1216 return name;
1217 }
1218 while ((piface->iface & 0xff) != 0xff) {
1219 if ((piface->iface & 0xff) == iface) {
1220 name = piface->name;
1221 break;
1222 }
1223 piface++;
1224 }
1225
1226 return name;
1227}
1228
1229static gchar *pci_get_node_name(PCIDevice *dev)
1230{
1231 int slot = PCI_SLOT(dev->devfn);
1232 int func = PCI_FUNC(dev->devfn);
1233 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1234 const char *name;
1235
1236 name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1237 ccode & 0xff);
1238
1239 if (func != 0) {
1240 return g_strdup_printf("%s@%x,%x", name, slot, func);
1241 } else {
1242 return g_strdup_printf("%s@%x", name, slot);
1243 }
1244}
1245
1246static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1247 PCIDevice *pdev);
1248
1249static void spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1250 sPAPRPHBState *sphb)
1251{
1252 ResourceProps rp;
1253 bool is_bridge = false;
1254 int pci_status;
1255 char *buf = NULL;
1256 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1257 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1258 uint32_t max_msi, max_msix;
1259
1260 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1261 PCI_HEADER_TYPE_BRIDGE) {
1262 is_bridge = true;
1263 }
1264
1265
1266 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1267 pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1268 _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1269 pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1270 _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1271 pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1272 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1273 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1274 _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1275 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1276 }
1277
1278 if (!is_bridge) {
1279 _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1280 pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1281 _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1282 pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1283 }
1284
1285 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1286 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1287 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1288 }
1289
1290 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1291 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1292 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1293 }
1294
1295 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1296 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1297
1298
1299 pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1300 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1301 PCI_STATUS_DEVSEL_MASK & pci_status));
1302
1303 if (pci_status & PCI_STATUS_FAST_BACK) {
1304 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1305 }
1306 if (pci_status & PCI_STATUS_66MHZ) {
1307 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1308 }
1309 if (pci_status & PCI_STATUS_UDF) {
1310 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1311 }
1312
1313 _FDT(fdt_setprop_string(fdt, offset, "name",
1314 pci_find_device_name((ccode >> 16) & 0xff,
1315 (ccode >> 8) & 0xff,
1316 ccode & 0xff)));
1317
1318 buf = spapr_phb_get_loc_code(sphb, dev);
1319 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", buf));
1320 g_free(buf);
1321
1322 if (drc_index) {
1323 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1324 }
1325
1326 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1327 RESOURCE_CELLS_ADDRESS));
1328 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1329 RESOURCE_CELLS_SIZE));
1330
1331 if (msi_present(dev)) {
1332 max_msi = msi_nr_vectors_allocated(dev);
1333 if (max_msi) {
1334 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1335 }
1336 }
1337 if (msix_present(dev)) {
1338 max_msix = dev->msix_entries_nr;
1339 if (max_msix) {
1340 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1341 }
1342 }
1343
1344 populate_resource_props(dev, &rp);
1345 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1346 _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1347 (uint8_t *)rp.assigned, rp.assigned_len));
1348
1349 if (sphb->pcie_ecs && pci_is_express(dev)) {
1350 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1351 }
1352}
1353
1354
1355static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev,
1356 void *fdt, int node_offset)
1357{
1358 int offset;
1359 gchar *nodename;
1360
1361 nodename = pci_get_node_name(dev);
1362 _FDT(offset = fdt_add_subnode(fdt, node_offset, nodename));
1363 g_free(nodename);
1364
1365 spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1366
1367 return offset;
1368}
1369
1370
1371void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1372{
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383 pci_device_reset(PCI_DEVICE(dev));
1384 object_unparent(OBJECT(dev));
1385}
1386
1387static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb,
1388 uint32_t busnr,
1389 int32_t devfn)
1390{
1391 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1392 (phb->index << 16) | (busnr << 8) | devfn);
1393}
1394
1395static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb,
1396 PCIDevice *pdev)
1397{
1398 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1399 return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1400}
1401
1402static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1403 PCIDevice *pdev)
1404{
1405 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1406
1407 if (!drc) {
1408 return 0;
1409 }
1410
1411 return spapr_drc_index(drc);
1412}
1413
1414static void spapr_pci_plug(HotplugHandler *plug_handler,
1415 DeviceState *plugged_dev, Error **errp)
1416{
1417 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1418 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1419 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1420 Error *local_err = NULL;
1421 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1422 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1423 void *fdt = NULL;
1424 int fdt_start_offset, fdt_size;
1425
1426
1427
1428
1429 if (!phb->dr_enabled) {
1430
1431
1432
1433 if (plugged_dev->hotplugged) {
1434 error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
1435 object_get_typename(OBJECT(phb)));
1436 }
1437 goto out;
1438 }
1439
1440 g_assert(drc);
1441
1442
1443
1444
1445
1446 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1447 PCI_FUNC(pdev->devfn) != 0) {
1448 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
1449 " additional functions can no longer be exposed to guest.",
1450 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1451 goto out;
1452 }
1453
1454 fdt = create_device_tree(&fdt_size);
1455 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0);
1456
1457 spapr_drc_attach(drc, DEVICE(pdev), fdt, fdt_start_offset, &local_err);
1458 if (local_err) {
1459 goto out;
1460 }
1461
1462
1463
1464
1465 if (!spapr_drc_hotplugged(plugged_dev)) {
1466 spapr_drc_reset(drc);
1467 } else if (PCI_FUNC(pdev->devfn) == 0) {
1468 int i;
1469
1470 for (i = 0; i < 8; i++) {
1471 sPAPRDRConnector *func_drc;
1472 sPAPRDRConnectorClass *func_drck;
1473 sPAPRDREntitySense state;
1474
1475 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1476 PCI_DEVFN(slotnr, i));
1477 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1478 state = func_drck->dr_entity_sense(func_drc);
1479
1480 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1481 spapr_hotplug_req_add_by_index(func_drc);
1482 }
1483 }
1484 }
1485
1486out:
1487 if (local_err) {
1488 error_propagate(errp, local_err);
1489 g_free(fdt);
1490 }
1491}
1492
1493static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1494 DeviceState *plugged_dev, Error **errp)
1495{
1496 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1497 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1498 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1499
1500 if (!phb->dr_enabled) {
1501 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1502 object_get_typename(OBJECT(phb)));
1503 return;
1504 }
1505
1506 g_assert(drc);
1507 g_assert(drc->dev == plugged_dev);
1508
1509 if (!spapr_drc_unplug_requested(drc)) {
1510 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1511 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1512 sPAPRDRConnector *func_drc;
1513 sPAPRDRConnectorClass *func_drck;
1514 sPAPRDREntitySense state;
1515 int i;
1516
1517
1518 if (PCI_FUNC(pdev->devfn) == 0) {
1519 for (i = 1; i < 8; i++) {
1520 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1521 PCI_DEVFN(slotnr, i));
1522 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1523 state = func_drck->dr_entity_sense(func_drc);
1524 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1525 && !spapr_drc_unplug_requested(func_drc)) {
1526 error_setg(errp,
1527 "PCI: slot %d, function %d still present. "
1528 "Must unplug all non-0 functions first.",
1529 slotnr, i);
1530 return;
1531 }
1532 }
1533 }
1534
1535 spapr_drc_detach(drc);
1536
1537
1538
1539
1540 if (PCI_FUNC(pdev->devfn) == 0) {
1541 for (i = 7; i >= 0; i--) {
1542 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1543 PCI_DEVFN(slotnr, i));
1544 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1545 state = func_drck->dr_entity_sense(func_drc);
1546 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1547 spapr_hotplug_req_remove_by_index(func_drc);
1548 }
1549 }
1550 }
1551 }
1552}
1553
1554static void spapr_phb_realize(DeviceState *dev, Error **errp)
1555{
1556
1557
1558
1559 sPAPRMachineState *spapr =
1560 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
1561 TYPE_SPAPR_MACHINE);
1562 sPAPRMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
1563 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1564 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1565 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1566 char *namebuf;
1567 int i;
1568 PCIBus *bus;
1569 uint64_t msi_window_size = 4096;
1570 sPAPRTCETable *tcet;
1571 const unsigned windows_supported =
1572 sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
1573
1574 if (!spapr) {
1575 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1576 return;
1577 }
1578
1579 if (sphb->index != (uint32_t)-1) {
1580 Error *local_err = NULL;
1581
1582 smc->phb_placement(spapr, sphb->index,
1583 &sphb->buid, &sphb->io_win_addr,
1584 &sphb->mem_win_addr, &sphb->mem64_win_addr,
1585 windows_supported, sphb->dma_liobn, &local_err);
1586 if (local_err) {
1587 error_propagate(errp, local_err);
1588 return;
1589 }
1590 } else {
1591 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
1592 return;
1593 }
1594
1595 if (sphb->mem64_win_size != 0) {
1596 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1597 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1598 " (max 2 GiB)", sphb->mem_win_size);
1599 return;
1600 }
1601
1602
1603 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1604 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1605
1606
1607
1608
1609
1610
1611
1612 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1613 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1614 sphb->mem64_win_pciaddr =
1615 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1616 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1617 }
1618
1619 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1620 error_setg(errp, "PCI host bridges must have unique BUIDs");
1621 return;
1622 }
1623
1624 if (sphb->numa_node != -1 &&
1625 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1626 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1627 return;
1628 }
1629
1630 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1631
1632
1633 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1634 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1635 g_free(namebuf);
1636
1637 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1638 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1639 namebuf, &sphb->memspace,
1640 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1641 g_free(namebuf);
1642 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1643 &sphb->mem32window);
1644
1645 if (sphb->mem64_win_size != 0) {
1646 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1647 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1648 namebuf, &sphb->memspace,
1649 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1650 g_free(namebuf);
1651
1652 memory_region_add_subregion(get_system_memory(),
1653 sphb->mem64_win_addr,
1654 &sphb->mem64window);
1655 }
1656
1657
1658 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1659 memory_region_init(&sphb->iospace, OBJECT(sphb),
1660 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1661 g_free(namebuf);
1662
1663 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1664 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1665 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1666 g_free(namebuf);
1667 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1668 &sphb->iowindow);
1669
1670 bus = pci_register_root_bus(dev, NULL,
1671 pci_spapr_set_irq, pci_spapr_map_irq, sphb,
1672 &sphb->memspace, &sphb->iospace,
1673 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
1674 phb->bus = bus;
1675 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL);
1676
1677
1678
1679
1680
1681
1682
1683
1684 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1685 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1686 namebuf, UINT64_MAX);
1687 g_free(namebuf);
1688 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1689 sphb->dtbusname);
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702#ifdef CONFIG_KVM
1703 if (kvm_enabled()) {
1704 msi_window_size = getpagesize();
1705 }
1706#endif
1707
1708 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1709 "msi", msi_window_size);
1710 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1711 &sphb->msiwindow);
1712
1713 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1714
1715 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1716
1717 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1718
1719
1720 for (i = 0; i < PCI_NUM_PINS; i++) {
1721 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
1722 Error *local_err = NULL;
1723
1724 if (smc->legacy_irq_allocation) {
1725 irq = spapr_irq_findone(spapr, &local_err);
1726 if (local_err) {
1727 error_propagate_prepend(errp, local_err,
1728 "can't allocate LSIs: ");
1729 return;
1730 }
1731 }
1732
1733 spapr_irq_claim(spapr, irq, true, &local_err);
1734 if (local_err) {
1735 error_propagate_prepend(errp, local_err, "can't allocate LSIs: ");
1736 return;
1737 }
1738
1739 sphb->lsi_table[i].irq = irq;
1740 }
1741
1742
1743 if (sphb->dr_enabled) {
1744 for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1745 spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI,
1746 (sphb->index << 16) | i);
1747 }
1748 }
1749
1750
1751 for (i = 0; i < windows_supported; ++i) {
1752 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1753 if (!tcet) {
1754 error_setg(errp, "Creating window#%d failed for %s",
1755 i, sphb->dtbusname);
1756 return;
1757 }
1758 memory_region_add_subregion(&sphb->iommu_root, 0,
1759 spapr_tce_get_iommu(tcet));
1760 }
1761
1762 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1763}
1764
1765static int spapr_phb_children_reset(Object *child, void *opaque)
1766{
1767 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1768
1769 if (dev) {
1770 device_reset(dev);
1771 }
1772
1773 return 0;
1774}
1775
1776void spapr_phb_dma_reset(sPAPRPHBState *sphb)
1777{
1778 int i;
1779 sPAPRTCETable *tcet;
1780
1781 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1782 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1783
1784 if (tcet && tcet->nb_table) {
1785 spapr_tce_table_disable(tcet);
1786 }
1787 }
1788
1789
1790 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1791 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1792 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1793}
1794
1795static void spapr_phb_reset(DeviceState *qdev)
1796{
1797 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1798
1799 spapr_phb_dma_reset(sphb);
1800
1801
1802 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1803
1804 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1805 spapr_phb_vfio_reset(qdev);
1806 }
1807}
1808
1809static Property spapr_phb_properties[] = {
1810 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
1811 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
1812 SPAPR_PCI_MEM32_WIN_SIZE),
1813 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size,
1814 SPAPR_PCI_MEM64_WIN_SIZE),
1815 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
1816 SPAPR_PCI_IO_WIN_SIZE),
1817 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled,
1818 true),
1819
1820 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0),
1821 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000),
1822 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr,
1823 0x800000000000000ULL),
1824 DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
1825 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
1826 (1ULL << 12) | (1ULL << 16)),
1827 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
1828 DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
1829 pre_2_8_migration, false),
1830 DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
1831 pcie_ecs, true),
1832 DEFINE_PROP_END_OF_LIST(),
1833};
1834
1835static const VMStateDescription vmstate_spapr_pci_lsi = {
1836 .name = "spapr_pci/lsi",
1837 .version_id = 1,
1838 .minimum_version_id = 1,
1839 .fields = (VMStateField[]) {
1840 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1841
1842 VMSTATE_END_OF_LIST()
1843 },
1844};
1845
1846static const VMStateDescription vmstate_spapr_pci_msi = {
1847 .name = "spapr_pci/msi",
1848 .version_id = 1,
1849 .minimum_version_id = 1,
1850 .fields = (VMStateField []) {
1851 VMSTATE_UINT32(key, spapr_pci_msi_mig),
1852 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1853 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1854 VMSTATE_END_OF_LIST()
1855 },
1856};
1857
1858static int spapr_pci_pre_save(void *opaque)
1859{
1860 sPAPRPHBState *sphb = opaque;
1861 GHashTableIter iter;
1862 gpointer key, value;
1863 int i;
1864
1865 if (sphb->pre_2_8_migration) {
1866 sphb->mig_liobn = sphb->dma_liobn[0];
1867 sphb->mig_mem_win_addr = sphb->mem_win_addr;
1868 sphb->mig_mem_win_size = sphb->mem_win_size;
1869 sphb->mig_io_win_addr = sphb->io_win_addr;
1870 sphb->mig_io_win_size = sphb->io_win_size;
1871
1872 if ((sphb->mem64_win_size != 0)
1873 && (sphb->mem64_win_addr
1874 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1875 sphb->mig_mem_win_size += sphb->mem64_win_size;
1876 }
1877 }
1878
1879 g_free(sphb->msi_devs);
1880 sphb->msi_devs = NULL;
1881 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1882 if (!sphb->msi_devs_num) {
1883 return 0;
1884 }
1885 sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num);
1886
1887 g_hash_table_iter_init(&iter, sphb->msi);
1888 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1889 sphb->msi_devs[i].key = *(uint32_t *) key;
1890 sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1891 }
1892
1893 return 0;
1894}
1895
1896static int spapr_pci_post_load(void *opaque, int version_id)
1897{
1898 sPAPRPHBState *sphb = opaque;
1899 gpointer key, value;
1900 int i;
1901
1902 for (i = 0; i < sphb->msi_devs_num; ++i) {
1903 key = g_memdup(&sphb->msi_devs[i].key,
1904 sizeof(sphb->msi_devs[i].key));
1905 value = g_memdup(&sphb->msi_devs[i].value,
1906 sizeof(sphb->msi_devs[i].value));
1907 g_hash_table_insert(sphb->msi, key, value);
1908 }
1909 g_free(sphb->msi_devs);
1910 sphb->msi_devs = NULL;
1911 sphb->msi_devs_num = 0;
1912
1913 return 0;
1914}
1915
1916static bool pre_2_8_migration(void *opaque, int version_id)
1917{
1918 sPAPRPHBState *sphb = opaque;
1919
1920 return sphb->pre_2_8_migration;
1921}
1922
1923static const VMStateDescription vmstate_spapr_pci = {
1924 .name = "spapr_pci",
1925 .version_id = 2,
1926 .minimum_version_id = 2,
1927 .pre_save = spapr_pci_pre_save,
1928 .post_load = spapr_pci_post_load,
1929 .fields = (VMStateField[]) {
1930 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState, NULL),
1931 VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration),
1932 VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration),
1933 VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration),
1934 VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration),
1935 VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration),
1936 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1937 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1938 VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1939 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1940 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1941 VMSTATE_END_OF_LIST()
1942 },
1943};
1944
1945static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1946 PCIBus *rootbus)
1947{
1948 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1949
1950 return sphb->dtbusname;
1951}
1952
1953static void spapr_phb_class_init(ObjectClass *klass, void *data)
1954{
1955 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1956 DeviceClass *dc = DEVICE_CLASS(klass);
1957 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
1958
1959 hc->root_bus_path = spapr_phb_root_bus_path;
1960 dc->realize = spapr_phb_realize;
1961 dc->props = spapr_phb_properties;
1962 dc->reset = spapr_phb_reset;
1963 dc->vmsd = &vmstate_spapr_pci;
1964
1965 dc->user_creatable = true;
1966 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1967 hp->plug = spapr_pci_plug;
1968 hp->unplug_request = spapr_pci_unplug_request;
1969}
1970
1971static const TypeInfo spapr_phb_info = {
1972 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
1973 .parent = TYPE_PCI_HOST_BRIDGE,
1974 .instance_size = sizeof(sPAPRPHBState),
1975 .class_init = spapr_phb_class_init,
1976 .interfaces = (InterfaceInfo[]) {
1977 { TYPE_HOTPLUG_HANDLER },
1978 { }
1979 }
1980};
1981
1982PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index)
1983{
1984 DeviceState *dev;
1985
1986 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
1987 qdev_prop_set_uint32(dev, "index", index);
1988 qdev_init_nofail(dev);
1989
1990 return PCI_HOST_BRIDGE(dev);
1991}
1992
1993typedef struct sPAPRFDT {
1994 void *fdt;
1995 int node_off;
1996 sPAPRPHBState *sphb;
1997} sPAPRFDT;
1998
1999static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
2000 void *opaque)
2001{
2002 PCIBus *sec_bus;
2003 sPAPRFDT *p = opaque;
2004 int offset;
2005 sPAPRFDT s_fdt;
2006
2007 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
2008 if (!offset) {
2009 error_report("Failed to create pci child device tree node");
2010 return;
2011 }
2012
2013 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2014 PCI_HEADER_TYPE_BRIDGE)) {
2015 return;
2016 }
2017
2018 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2019 if (!sec_bus) {
2020 return;
2021 }
2022
2023 s_fdt.fdt = p->fdt;
2024 s_fdt.node_off = offset;
2025 s_fdt.sphb = p->sphb;
2026 pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
2027 spapr_populate_pci_devices_dt,
2028 &s_fdt);
2029}
2030
2031static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2032 void *opaque)
2033{
2034 unsigned int *bus_no = opaque;
2035 unsigned int primary = *bus_no;
2036 unsigned int subordinate = 0xff;
2037 PCIBus *sec_bus = NULL;
2038
2039 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2040 PCI_HEADER_TYPE_BRIDGE)) {
2041 return;
2042 }
2043
2044 (*bus_no)++;
2045 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1);
2046 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2047 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2048
2049 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2050 if (!sec_bus) {
2051 return;
2052 }
2053
2054 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1);
2055 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2056 spapr_phb_pci_enumerate_bridge, bus_no);
2057 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2058}
2059
2060static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
2061{
2062 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2063 unsigned int bus_no = 0;
2064
2065 pci_for_each_device(bus, pci_bus_num(bus),
2066 spapr_phb_pci_enumerate_bridge,
2067 &bus_no);
2068
2069}
2070
2071int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt,
2072 uint32_t nr_msis)
2073{
2074 int bus_off, i, j, ret;
2075 gchar *nodename;
2076 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2077 struct {
2078 uint32_t hi;
2079 uint64_t child;
2080 uint64_t parent;
2081 uint64_t size;
2082 } QEMU_PACKED ranges[] = {
2083 {
2084 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2085 cpu_to_be64(phb->io_win_addr),
2086 cpu_to_be64(memory_region_size(&phb->iospace)),
2087 },
2088 {
2089 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2090 cpu_to_be64(phb->mem_win_addr),
2091 cpu_to_be64(phb->mem_win_size),
2092 },
2093 {
2094 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2095 cpu_to_be64(phb->mem64_win_addr),
2096 cpu_to_be64(phb->mem64_win_size),
2097 },
2098 };
2099 const unsigned sizeof_ranges =
2100 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2101 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2102 uint32_t interrupt_map_mask[] = {
2103 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2104 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2105 uint32_t ddw_applicable[] = {
2106 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2107 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2108 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2109 };
2110 uint32_t ddw_extensions[] = {
2111 cpu_to_be32(1),
2112 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2113 };
2114 uint32_t associativity[] = {cpu_to_be32(0x4),
2115 cpu_to_be32(0x0),
2116 cpu_to_be32(0x0),
2117 cpu_to_be32(0x0),
2118 cpu_to_be32(phb->numa_node)};
2119 sPAPRTCETable *tcet;
2120 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2121 sPAPRFDT s_fdt;
2122
2123
2124 nodename = g_strdup_printf("pci@%" PRIx64, phb->buid);
2125 _FDT(bus_off = fdt_add_subnode(fdt, 0, nodename));
2126 g_free(nodename);
2127
2128
2129 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2130 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2131 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2132 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2133 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2134 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2135 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2136 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2137 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2138 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2139 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis));
2140
2141
2142 if (phb->ddw_enabled) {
2143 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2144 sizeof(ddw_applicable)));
2145 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2146 &ddw_extensions, sizeof(ddw_extensions)));
2147 }
2148
2149
2150 if (phb->numa_node != -1) {
2151 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2152 sizeof(associativity)));
2153 }
2154
2155
2156
2157
2158 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2159 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2160 for (i = 0; i < PCI_SLOT_MAX; i++) {
2161 for (j = 0; j < PCI_NUM_PINS; j++) {
2162 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2163 int lsi_num = pci_spapr_swizzle(i, j);
2164
2165 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2166 irqmap[1] = 0;
2167 irqmap[2] = 0;
2168 irqmap[3] = cpu_to_be32(j+1);
2169 irqmap[4] = cpu_to_be32(xics_phandle);
2170 spapr_dt_xics_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2171 }
2172 }
2173
2174 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2175 sizeof(interrupt_map)));
2176
2177 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2178 if (!tcet) {
2179 return -1;
2180 }
2181 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2182 tcet->liobn, tcet->bus_offset,
2183 tcet->nb_table << tcet->page_shift);
2184
2185
2186 spapr_phb_pci_enumerate(phb);
2187 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2188
2189
2190 s_fdt.fdt = fdt;
2191 s_fdt.node_off = bus_off;
2192 s_fdt.sphb = phb;
2193 pci_for_each_device_reverse(bus, pci_bus_num(bus),
2194 spapr_populate_pci_devices_dt,
2195 &s_fdt);
2196
2197 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2198 SPAPR_DR_CONNECTOR_TYPE_PCI);
2199 if (ret) {
2200 return ret;
2201 }
2202
2203 return 0;
2204}
2205
2206void spapr_pci_rtas_init(void)
2207{
2208 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2209 rtas_read_pci_config);
2210 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2211 rtas_write_pci_config);
2212 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2213 rtas_ibm_read_pci_config);
2214 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2215 rtas_ibm_write_pci_config);
2216 if (msi_nonbroken) {
2217 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2218 "ibm,query-interrupt-source-number",
2219 rtas_ibm_query_interrupt_source_number);
2220 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2221 rtas_ibm_change_msi);
2222 }
2223
2224 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2225 "ibm,set-eeh-option",
2226 rtas_ibm_set_eeh_option);
2227 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2228 "ibm,get-config-addr-info2",
2229 rtas_ibm_get_config_addr_info2);
2230 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2231 "ibm,read-slot-reset-state2",
2232 rtas_ibm_read_slot_reset_state2);
2233 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2234 "ibm,set-slot-reset",
2235 rtas_ibm_set_slot_reset);
2236 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2237 "ibm,configure-pe",
2238 rtas_ibm_configure_pe);
2239 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2240 "ibm,slot-error-detail",
2241 rtas_ibm_slot_error_detail);
2242}
2243
2244static void spapr_pci_register_types(void)
2245{
2246 type_register_static(&spapr_phb_info);
2247}
2248
2249type_init(spapr_pci_register_types)
2250
2251static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2252{
2253 bool be = *(bool *)opaque;
2254
2255 if (object_dynamic_cast(OBJECT(dev), "VGA")
2256 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2257 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2258 &error_abort);
2259 }
2260 return 0;
2261}
2262
2263void spapr_pci_switch_vga(bool big_endian)
2264{
2265 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2266 sPAPRPHBState *sphb;
2267
2268
2269
2270
2271
2272
2273 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2274 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2275 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2276 &big_endian);
2277 }
2278}
2279