LXR qemu/hw/riscv/sifive

   1/*
   2 * SiFive CLINT (Core Local Interruptor)
   3 *
   4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5 * Copyright (c) 2017 SiFive, Inc.
   6 *
   7 * This provides real-time clock, timer and interprocessor interrupts.
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms and conditions of the GNU General Public License,
  11 * version 2 or later, as published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope it will be useful, but WITHOUT
  14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16 * more details.
  17 *
  18 * You should have received a copy of the GNU General Public License along with
  19 * this program.  If not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#include "qemu/osdep.h"
  23#include "qemu/error-report.h"
  24#include "hw/sysbus.h"
  25#include "target/riscv/cpu.h"
  26#include "hw/riscv/sifive_clint.h"
  27#include "qemu/timer.h"
  28
  29static uint64_t cpu_riscv_read_rtc(void)
  30{
  31    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
  32        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
  33}
  34
  35/*
  36 * Called when timecmp is written to update the QEMU timer or immediately
  37 * trigger timer interrupt if mtimecmp <= current timer value.
  38 */
  39static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
  40{
  41    uint64_t next;
  42    uint64_t diff;
  43
  44    uint64_t rtc_r = cpu_riscv_read_rtc();
  45
  46    cpu->env.timecmp = value;
  47    if (cpu->env.timecmp <= rtc_r) {
  48        /* if we're setting an MTIMECMP value in the "past",
  49           immediately raise the timer interrupt */
  50        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
  51        return;
  52    }
  53
  54    /* otherwise, set up the future timer interrupt */
  55    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
  56    diff = cpu->env.timecmp - rtc_r;
  57    /* back to ns (note args switched in muldiv64) */
  58    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
  59        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
  60    timer_mod(cpu->env.timer, next);
  61}
  62
  63/*
  64 * Callback used when the timer set using timer_mod expires.
  65 * Should raise the timer interrupt line
  66 */
  67static void sifive_clint_timer_cb(void *opaque)
  68{
  69    RISCVCPU *cpu = opaque;
  70    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
  71}
  72
  73/* CPU wants to read rtc or timecmp register */
  74static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
  75{
  76    SiFiveCLINTState *clint = opaque;
  77    if (addr >= clint->sip_base &&
  78        addr < clint->sip_base + (clint->num_harts << 2)) {
  79        size_t hartid = (addr - clint->sip_base) >> 2;
  80        CPUState *cpu = qemu_get_cpu(hartid);
  81        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
  82        if (!env) {
  83            error_report("clint: invalid timecmp hartid: %zu", hartid);
  84        } else if ((addr & 0x3) == 0) {
  85            return (env->mip & MIP_MSIP) > 0;
  86        } else {
  87            error_report("clint: invalid read: %08x", (uint32_t)addr);
  88            return 0;
  89        }
  90    } else if (addr >= clint->timecmp_base &&
  91        addr < clint->timecmp_base + (clint->num_harts << 3)) {
  92        size_t hartid = (addr - clint->timecmp_base) >> 3;
  93        CPUState *cpu = qemu_get_cpu(hartid);
  94        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
  95        if (!env) {
  96            error_report("clint: invalid timecmp hartid: %zu", hartid);
  97        } else if ((addr & 0x7) == 0) {
  98            /* timecmp_lo */
  99            uint64_t timecmp = env->timecmp;
 100            return timecmp & 0xFFFFFFFF;
 101        } else if ((addr & 0x7) == 4) {
 102            /* timecmp_hi */
 103            uint64_t timecmp = env->timecmp;
 104            return (timecmp >> 32) & 0xFFFFFFFF;
 105        } else {
 106            error_report("clint: invalid read: %08x", (uint32_t)addr);
 107            return 0;
 108        }
 109    } else if (addr == clint->time_base) {
 110        /* time_lo */
 111        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
 112    } else if (addr == clint->time_base + 4) {
 113        /* time_hi */
 114        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
 115    }
 116
 117    error_report("clint: invalid read: %08x", (uint32_t)addr);
 118    return 0;
 119}
 120
 121/* CPU wrote to rtc or timecmp register */
 122static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
 123        unsigned size)
 124{
 125    SiFiveCLINTState *clint = opaque;
 126
 127    if (addr >= clint->sip_base &&
 128        addr < clint->sip_base + (clint->num_harts << 2)) {
 129        size_t hartid = (addr - clint->sip_base) >> 2;
 130        CPUState *cpu = qemu_get_cpu(hartid);
 131        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 132        if (!env) {
 133            error_report("clint: invalid timecmp hartid: %zu", hartid);
 134        } else if ((addr & 0x3) == 0) {
 135            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
 136        } else {
 137            error_report("clint: invalid sip write: %08x", (uint32_t)addr);
 138        }
 139        return;
 140    } else if (addr >= clint->timecmp_base &&
 141        addr < clint->timecmp_base + (clint->num_harts << 3)) {
 142        size_t hartid = (addr - clint->timecmp_base) >> 3;
 143        CPUState *cpu = qemu_get_cpu(hartid);
 144        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 145        if (!env) {
 146            error_report("clint: invalid timecmp hartid: %zu", hartid);
 147        } else if ((addr & 0x7) == 0) {
 148            /* timecmp_lo */
 149            uint64_t timecmp = env->timecmp;
 150            sifive_clint_write_timecmp(RISCV_CPU(cpu),
 151                timecmp << 32 | (value & 0xFFFFFFFF));
 152            return;
 153        } else if ((addr & 0x7) == 4) {
 154            /* timecmp_hi */
 155            uint64_t timecmp = env->timecmp;
 156            sifive_clint_write_timecmp(RISCV_CPU(cpu),
 157                value << 32 | (timecmp & 0xFFFFFFFF));
 158        } else {
 159            error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
 160        }
 161        return;
 162    } else if (addr == clint->time_base) {
 163        /* time_lo */
 164        error_report("clint: time_lo write not implemented");
 165        return;
 166    } else if (addr == clint->time_base + 4) {
 167        /* time_hi */
 168        error_report("clint: time_hi write not implemented");
 169        return;
 170    }
 171
 172    error_report("clint: invalid write: %08x", (uint32_t)addr);
 173}
 174
 175static const MemoryRegionOps sifive_clint_ops = {
 176    .read = sifive_clint_read,
 177    .write = sifive_clint_write,
 178    .endianness = DEVICE_LITTLE_ENDIAN,
 179    .valid = {
 180        .min_access_size = 4,
 181        .max_access_size = 4
 182    }
 183};
 184
 185static Property sifive_clint_properties[] = {
 186    DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
 187    DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
 188    DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
 189    DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
 190    DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
 191    DEFINE_PROP_END_OF_LIST(),
 192};
 193
 194static void sifive_clint_realize(DeviceState *dev, Error **errp)
 195{
 196    SiFiveCLINTState *s = SIFIVE_CLINT(dev);
 197    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
 198                          TYPE_SIFIVE_CLINT, s->aperture_size);
 199    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 200}
 201
 202static void sifive_clint_class_init(ObjectClass *klass, void *data)
 203{
 204    DeviceClass *dc = DEVICE_CLASS(klass);
 205    dc->realize = sifive_clint_realize;
 206    dc->props = sifive_clint_properties;
 207}
 208
 209static const TypeInfo sifive_clint_info = {
 210    .name          = TYPE_SIFIVE_CLINT,
 211    .parent        = TYPE_SYS_BUS_DEVICE,
 212    .instance_size = sizeof(SiFiveCLINTState),
 213    .class_init    = sifive_clint_class_init,
 214};
 215
 216static void sifive_clint_register_types(void)
 217{
 218    type_register_static(&sifive_clint_info);
 219}
 220
 221type_init(sifive_clint_register_types)
 222
 223
 224/*
 225 * Create CLINT device.
 226 */
 227DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
 228    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base)
 229{
 230    int i;
 231    for (i = 0; i < num_harts; i++) {
 232        CPUState *cpu = qemu_get_cpu(i);
 233        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 234        if (!env) {
 235            continue;
 236        }
 237        env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 238                                  &sifive_clint_timer_cb, cpu);
 239        env->timecmp = 0;
 240    }
 241
 242    DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT);
 243    qdev_prop_set_uint32(dev, "num-harts", num_harts);
 244    qdev_prop_set_uint32(dev, "sip-base", sip_base);
 245    qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
 246    qdev_prop_set_uint32(dev, "time-base", time_base);
 247    qdev_prop_set_uint32(dev, "aperture-size", size);
 248    qdev_init_nofail(dev);
 249    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 250    return dev;
 251}
 252