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31#include "qemu/osdep.h"
32#include "qemu/log.h"
33#include "qemu/error-report.h"
34#include "qapi/error.h"
35#include "hw/hw.h"
36#include "hw/boards.h"
37#include "hw/loader.h"
38#include "hw/sysbus.h"
39#include "hw/char/serial.h"
40#include "target/riscv/cpu.h"
41#include "hw/riscv/riscv_hart.h"
42#include "hw/riscv/sifive_plic.h"
43#include "hw/riscv/sifive_clint.h"
44#include "hw/riscv/sifive_prci.h"
45#include "hw/riscv/sifive_uart.h"
46#include "hw/riscv/sifive_e.h"
47#include "chardev/char.h"
48#include "sysemu/arch_init.h"
49#include "exec/address-spaces.h"
50#include "elf.h"
51
52static const struct MemmapEntry {
53 hwaddr base;
54 hwaddr size;
55} sifive_e_memmap[] = {
56 [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
57 [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
58 [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
59 [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
60 [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
61 [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
62 [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
63 [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
64 [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
65 [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
66 [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
67 [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
68 [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
69 [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
70 [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
71 [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
72 [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
73 [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
74 [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
75};
76
77static uint64_t load_kernel(const char *kernel_filename)
78{
79 uint64_t kernel_entry, kernel_high;
80
81 if (load_elf(kernel_filename, NULL, NULL,
82 &kernel_entry, NULL, &kernel_high,
83 0, EM_RISCV, 1, 0) < 0) {
84 error_report("could not load kernel '%s'", kernel_filename);
85 exit(1);
86 }
87 return kernel_entry;
88}
89
90static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
91 uintptr_t offset, uintptr_t length)
92{
93 MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
94 memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
95 memory_region_add_subregion(parent, offset, mock_mmio);
96}
97
98static void riscv_sifive_e_init(MachineState *machine)
99{
100 const struct MemmapEntry *memmap = sifive_e_memmap;
101
102 SiFiveEState *s = g_new0(SiFiveEState, 1);
103 MemoryRegion *sys_mem = get_system_memory();
104 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
105 int i;
106
107
108 object_initialize_child(OBJECT(machine), "soc", &s->soc,
109 sizeof(s->soc), TYPE_RISCV_E_SOC,
110 &error_abort, NULL);
111 object_property_set_bool(OBJECT(&s->soc), true, "realized",
112 &error_abort);
113
114
115 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
116 memmap[SIFIVE_E_DTIM].size, &error_fatal);
117 memory_region_add_subregion(sys_mem,
118 memmap[SIFIVE_E_DTIM].base, main_mem);
119
120
121 uint32_t reset_vec[2] = {
122 0x204002b7,
123 0x00028067,
124 };
125
126
127 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
128 reset_vec[i] = cpu_to_le32(reset_vec[i]);
129 }
130 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
131 memmap[SIFIVE_E_MROM].base, &address_space_memory);
132
133 if (machine->kernel_filename) {
134 load_kernel(machine->kernel_filename);
135 }
136}
137
138static void riscv_sifive_e_soc_init(Object *obj)
139{
140 SiFiveESoCState *s = RISCV_E_SOC(obj);
141
142 object_initialize_child(obj, "cpus", &s->cpus,
143 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
144 &error_abort, NULL);
145 object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
146 &error_abort);
147 object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
148 &error_abort);
149}
150
151static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
152{
153 const struct MemmapEntry *memmap = sifive_e_memmap;
154
155 SiFiveESoCState *s = RISCV_E_SOC(dev);
156 MemoryRegion *sys_mem = get_system_memory();
157 MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
158 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
159
160 object_property_set_bool(OBJECT(&s->cpus), true, "realized",
161 &error_abort);
162
163
164 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
165 memmap[SIFIVE_E_MROM].size, &error_fatal);
166 memory_region_add_subregion(sys_mem,
167 memmap[SIFIVE_E_MROM].base, mask_rom);
168
169
170 s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
171 (char *)SIFIVE_E_PLIC_HART_CONFIG,
172 SIFIVE_E_PLIC_NUM_SOURCES,
173 SIFIVE_E_PLIC_NUM_PRIORITIES,
174 SIFIVE_E_PLIC_PRIORITY_BASE,
175 SIFIVE_E_PLIC_PENDING_BASE,
176 SIFIVE_E_PLIC_ENABLE_BASE,
177 SIFIVE_E_PLIC_ENABLE_STRIDE,
178 SIFIVE_E_PLIC_CONTEXT_BASE,
179 SIFIVE_E_PLIC_CONTEXT_STRIDE,
180 memmap[SIFIVE_E_PLIC].size);
181 sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
182 memmap[SIFIVE_E_CLINT].size, smp_cpus,
183 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
184 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
185 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
186 sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
187 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
188 memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
189 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
190 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
191 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
192 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
193 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
194 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
195
196
197
198 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
199 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
200 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
201 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
202 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
203 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
204 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
205 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
206
207
208 memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip",
209 memmap[SIFIVE_E_XIP].size, &error_fatal);
210 memory_region_set_readonly(xip_mem, true);
211 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem);
212}
213
214static void riscv_sifive_e_machine_init(MachineClass *mc)
215{
216 mc->desc = "RISC-V Board compatible with SiFive E SDK";
217 mc->init = riscv_sifive_e_init;
218 mc->max_cpus = 1;
219}
220
221DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
222
223static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
224{
225 DeviceClass *dc = DEVICE_CLASS(oc);
226
227 dc->realize = riscv_sifive_e_soc_realize;
228
229 dc->user_creatable = false;
230}
231
232static const TypeInfo riscv_sifive_e_soc_type_info = {
233 .name = TYPE_RISCV_E_SOC,
234 .parent = TYPE_DEVICE,
235 .instance_size = sizeof(SiFiveESoCState),
236 .instance_init = riscv_sifive_e_soc_init,
237 .class_init = riscv_sifive_e_soc_class_init,
238};
239
240static void riscv_sifive_e_soc_register_types(void)
241{
242 type_register_static(&riscv_sifive_e_soc_type_info);
243}
244
245type_init(riscv_sifive_e_soc_register_types)
246
