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21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "target/riscv/cpu.h"
24#include "hw/riscv/sifive_test.h"
25
26static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
27{
28 return 0;
29}
30
31static void sifive_test_write(void *opaque, hwaddr addr,
32 uint64_t val64, unsigned int size)
33{
34 if (addr == 0) {
35 int status = val64 & 0xffff;
36 int code = (val64 >> 16) & 0xffff;
37 switch (status) {
38 case FINISHER_FAIL:
39 exit(code);
40 case FINISHER_PASS:
41 exit(0);
42 default:
43 break;
44 }
45 }
46 hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
47 __func__, (int)addr, val64);
48}
49
50static const MemoryRegionOps sifive_test_ops = {
51 .read = sifive_test_read,
52 .write = sifive_test_write,
53 .endianness = DEVICE_NATIVE_ENDIAN,
54 .valid = {
55 .min_access_size = 4,
56 .max_access_size = 4
57 }
58};
59
60static void sifive_test_init(Object *obj)
61{
62 SiFiveTestState *s = SIFIVE_TEST(obj);
63
64 memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
65 TYPE_SIFIVE_TEST, 0x1000);
66 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
67}
68
69static const TypeInfo sifive_test_info = {
70 .name = TYPE_SIFIVE_TEST,
71 .parent = TYPE_SYS_BUS_DEVICE,
72 .instance_size = sizeof(SiFiveTestState),
73 .instance_init = sifive_test_init,
74};
75
76static void sifive_test_register_types(void)
77{
78 type_register_static(&sifive_test_info);
79}
80
81type_init(sifive_test_register_types)
82
83
84
85
86
87DeviceState *sifive_test_create(hwaddr addr)
88{
89 DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST);
90 qdev_init_nofail(dev);
91 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
92 return dev;
93}
94