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26#include "qemu/osdep.h"
27#include "hw/sysbus.h"
28#include "hw/scsi/esp.h"
29#include "trace.h"
30#include "qemu/log.h"
31
32
33
34
35
36
37
38
39
40static void esp_raise_irq(ESPState *s)
41{
42 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
43 s->rregs[ESP_RSTAT] |= STAT_INT;
44 qemu_irq_raise(s->irq);
45 trace_esp_raise_irq();
46 }
47}
48
49static void esp_lower_irq(ESPState *s)
50{
51 if (s->rregs[ESP_RSTAT] & STAT_INT) {
52 s->rregs[ESP_RSTAT] &= ~STAT_INT;
53 qemu_irq_lower(s->irq);
54 trace_esp_lower_irq();
55 }
56}
57
58void esp_dma_enable(ESPState *s, int irq, int level)
59{
60 if (level) {
61 s->dma_enabled = 1;
62 trace_esp_dma_enable();
63 if (s->dma_cb) {
64 s->dma_cb(s);
65 s->dma_cb = NULL;
66 }
67 } else {
68 trace_esp_dma_disable();
69 s->dma_enabled = 0;
70 }
71}
72
73void esp_request_cancelled(SCSIRequest *req)
74{
75 ESPState *s = req->hba_private;
76
77 if (req == s->current_req) {
78 scsi_req_unref(s->current_req);
79 s->current_req = NULL;
80 s->current_dev = NULL;
81 }
82}
83
84static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
85{
86 uint32_t dmalen;
87 int target;
88
89 target = s->wregs[ESP_WBUSID] & BUSID_DID;
90 if (s->dma) {
91 dmalen = s->rregs[ESP_TCLO];
92 dmalen |= s->rregs[ESP_TCMID] << 8;
93 dmalen |= s->rregs[ESP_TCHI] << 16;
94 if (dmalen > buflen) {
95 return 0;
96 }
97 s->dma_memory_read(s->dma_opaque, buf, dmalen);
98 } else {
99 dmalen = s->ti_size;
100 if (dmalen > TI_BUFSZ) {
101 return 0;
102 }
103 memcpy(buf, s->ti_buf, dmalen);
104 buf[0] = buf[2] >> 5;
105 }
106 trace_esp_get_cmd(dmalen, target);
107
108 s->ti_size = 0;
109 s->ti_rptr = 0;
110 s->ti_wptr = 0;
111
112 if (s->current_req) {
113
114 scsi_req_cancel(s->current_req);
115 s->async_len = 0;
116 }
117
118 s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
119 if (!s->current_dev) {
120
121 s->rregs[ESP_RSTAT] = 0;
122 s->rregs[ESP_RINTR] = INTR_DC;
123 s->rregs[ESP_RSEQ] = SEQ_0;
124 esp_raise_irq(s);
125 return 0;
126 }
127 return dmalen;
128}
129
130static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
131{
132 int32_t datalen;
133 int lun;
134 SCSIDevice *current_lun;
135
136 trace_esp_do_busid_cmd(busid);
137 lun = busid & 7;
138 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
139 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
140 datalen = scsi_req_enqueue(s->current_req);
141 s->ti_size = datalen;
142 if (datalen != 0) {
143 s->rregs[ESP_RSTAT] = STAT_TC;
144 s->dma_left = 0;
145 s->dma_counter = 0;
146 if (datalen > 0) {
147 s->rregs[ESP_RSTAT] |= STAT_DI;
148 } else {
149 s->rregs[ESP_RSTAT] |= STAT_DO;
150 }
151 scsi_req_continue(s->current_req);
152 }
153 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
154 s->rregs[ESP_RSEQ] = SEQ_CD;
155 esp_raise_irq(s);
156}
157
158static void do_cmd(ESPState *s, uint8_t *buf)
159{
160 uint8_t busid = buf[0];
161
162 do_busid_cmd(s, &buf[1], busid);
163}
164
165static void handle_satn(ESPState *s)
166{
167 uint8_t buf[32];
168 int len;
169
170 if (s->dma && !s->dma_enabled) {
171 s->dma_cb = handle_satn;
172 return;
173 }
174 len = get_cmd(s, buf, sizeof(buf));
175 if (len)
176 do_cmd(s, buf);
177}
178
179static void handle_s_without_atn(ESPState *s)
180{
181 uint8_t buf[32];
182 int len;
183
184 if (s->dma && !s->dma_enabled) {
185 s->dma_cb = handle_s_without_atn;
186 return;
187 }
188 len = get_cmd(s, buf, sizeof(buf));
189 if (len) {
190 do_busid_cmd(s, buf, 0);
191 }
192}
193
194static void handle_satn_stop(ESPState *s)
195{
196 if (s->dma && !s->dma_enabled) {
197 s->dma_cb = handle_satn_stop;
198 return;
199 }
200 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
201 if (s->cmdlen) {
202 trace_esp_handle_satn_stop(s->cmdlen);
203 s->do_cmd = 1;
204 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
205 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
206 s->rregs[ESP_RSEQ] = SEQ_CD;
207 esp_raise_irq(s);
208 }
209}
210
211static void write_response(ESPState *s)
212{
213 trace_esp_write_response(s->status);
214 s->ti_buf[0] = s->status;
215 s->ti_buf[1] = 0;
216 if (s->dma) {
217 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
218 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
219 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
220 s->rregs[ESP_RSEQ] = SEQ_CD;
221 } else {
222 s->ti_size = 2;
223 s->ti_rptr = 0;
224 s->ti_wptr = 2;
225 s->rregs[ESP_RFLAGS] = 2;
226 }
227 esp_raise_irq(s);
228}
229
230static void esp_dma_done(ESPState *s)
231{
232 s->rregs[ESP_RSTAT] |= STAT_TC;
233 s->rregs[ESP_RINTR] = INTR_BS;
234 s->rregs[ESP_RSEQ] = 0;
235 s->rregs[ESP_RFLAGS] = 0;
236 s->rregs[ESP_TCLO] = 0;
237 s->rregs[ESP_TCMID] = 0;
238 s->rregs[ESP_TCHI] = 0;
239 esp_raise_irq(s);
240}
241
242static void esp_do_dma(ESPState *s)
243{
244 uint32_t len;
245 int to_device;
246
247 len = s->dma_left;
248 if (s->do_cmd) {
249 trace_esp_do_dma(s->cmdlen, len);
250 assert (s->cmdlen <= sizeof(s->cmdbuf) &&
251 len <= sizeof(s->cmdbuf) - s->cmdlen);
252 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
253 return;
254 }
255 if (s->async_len == 0) {
256
257 return;
258 }
259 if (len > s->async_len) {
260 len = s->async_len;
261 }
262 to_device = (s->ti_size < 0);
263 if (to_device) {
264 s->dma_memory_read(s->dma_opaque, s->async_buf, len);
265 } else {
266 s->dma_memory_write(s->dma_opaque, s->async_buf, len);
267 }
268 s->dma_left -= len;
269 s->async_buf += len;
270 s->async_len -= len;
271 if (to_device)
272 s->ti_size += len;
273 else
274 s->ti_size -= len;
275 if (s->async_len == 0) {
276 scsi_req_continue(s->current_req);
277
278
279
280 if (to_device || s->dma_left != 0 || s->ti_size == 0) {
281 return;
282 }
283 }
284
285
286 esp_dma_done(s);
287}
288
289void esp_command_complete(SCSIRequest *req, uint32_t status,
290 size_t resid)
291{
292 ESPState *s = req->hba_private;
293
294 trace_esp_command_complete();
295 if (s->ti_size != 0) {
296 trace_esp_command_complete_unexpected();
297 }
298 s->ti_size = 0;
299 s->dma_left = 0;
300 s->async_len = 0;
301 if (status) {
302 trace_esp_command_complete_fail();
303 }
304 s->status = status;
305 s->rregs[ESP_RSTAT] = STAT_ST;
306 esp_dma_done(s);
307 if (s->current_req) {
308 scsi_req_unref(s->current_req);
309 s->current_req = NULL;
310 s->current_dev = NULL;
311 }
312}
313
314void esp_transfer_data(SCSIRequest *req, uint32_t len)
315{
316 ESPState *s = req->hba_private;
317
318 assert(!s->do_cmd);
319 trace_esp_transfer_data(s->dma_left, s->ti_size);
320 s->async_len = len;
321 s->async_buf = scsi_req_get_buf(req);
322 if (s->dma_left) {
323 esp_do_dma(s);
324 } else if (s->dma_counter != 0 && s->ti_size <= 0) {
325
326
327 esp_dma_done(s);
328 }
329}
330
331static void handle_ti(ESPState *s)
332{
333 uint32_t dmalen, minlen;
334
335 if (s->dma && !s->dma_enabled) {
336 s->dma_cb = handle_ti;
337 return;
338 }
339
340 dmalen = s->rregs[ESP_TCLO];
341 dmalen |= s->rregs[ESP_TCMID] << 8;
342 dmalen |= s->rregs[ESP_TCHI] << 16;
343 if (dmalen==0) {
344 dmalen=0x10000;
345 }
346 s->dma_counter = dmalen;
347
348 if (s->do_cmd)
349 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
350 else if (s->ti_size < 0)
351 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
352 else
353 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
354 trace_esp_handle_ti(minlen);
355 if (s->dma) {
356 s->dma_left = minlen;
357 s->rregs[ESP_RSTAT] &= ~STAT_TC;
358 esp_do_dma(s);
359 }
360 if (s->do_cmd) {
361 trace_esp_handle_ti_cmd(s->cmdlen);
362 s->ti_size = 0;
363 s->cmdlen = 0;
364 s->do_cmd = 0;
365 do_cmd(s, s->cmdbuf);
366 }
367}
368
369void esp_hard_reset(ESPState *s)
370{
371 memset(s->rregs, 0, ESP_REGS);
372 memset(s->wregs, 0, ESP_REGS);
373 s->tchi_written = 0;
374 s->ti_size = 0;
375 s->ti_rptr = 0;
376 s->ti_wptr = 0;
377 s->dma = 0;
378 s->do_cmd = 0;
379 s->dma_cb = NULL;
380
381 s->rregs[ESP_CFG1] = 7;
382}
383
384static void esp_soft_reset(ESPState *s)
385{
386 qemu_irq_lower(s->irq);
387 esp_hard_reset(s);
388}
389
390static void parent_esp_reset(ESPState *s, int irq, int level)
391{
392 if (level) {
393 esp_soft_reset(s);
394 }
395}
396
397uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
398{
399 uint32_t old_val;
400
401 trace_esp_mem_readb(saddr, s->rregs[saddr]);
402 switch (saddr) {
403 case ESP_FIFO:
404 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
405
406 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
407 s->rregs[ESP_FIFO] = 0;
408 } else if (s->ti_rptr < s->ti_wptr) {
409 s->ti_size--;
410 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
411 }
412 if (s->ti_rptr == s->ti_wptr) {
413 s->ti_rptr = 0;
414 s->ti_wptr = 0;
415 }
416 break;
417 case ESP_RINTR:
418
419
420 old_val = s->rregs[ESP_RINTR];
421 s->rregs[ESP_RINTR] = 0;
422 s->rregs[ESP_RSTAT] &= ~STAT_TC;
423 s->rregs[ESP_RSEQ] = SEQ_CD;
424 esp_lower_irq(s);
425
426 return old_val;
427 case ESP_TCHI:
428
429 if (!s->tchi_written) {
430 return s->chip_id;
431 }
432 default:
433 break;
434 }
435 return s->rregs[saddr];
436}
437
438void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
439{
440 trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
441 switch (saddr) {
442 case ESP_TCHI:
443 s->tchi_written = true;
444
445 case ESP_TCLO:
446 case ESP_TCMID:
447 s->rregs[ESP_RSTAT] &= ~STAT_TC;
448 break;
449 case ESP_FIFO:
450 if (s->do_cmd) {
451 if (s->cmdlen < ESP_CMDBUF_SZ) {
452 s->cmdbuf[s->cmdlen++] = val & 0xff;
453 } else {
454 trace_esp_error_fifo_overrun();
455 }
456 } else if (s->ti_wptr == TI_BUFSZ - 1) {
457 trace_esp_error_fifo_overrun();
458 } else {
459 s->ti_size++;
460 s->ti_buf[s->ti_wptr++] = val & 0xff;
461 }
462 break;
463 case ESP_CMD:
464 s->rregs[saddr] = val;
465 if (val & CMD_DMA) {
466 s->dma = 1;
467
468 s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
469 s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
470 s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
471 } else {
472 s->dma = 0;
473 }
474 switch(val & CMD_CMD) {
475 case CMD_NOP:
476 trace_esp_mem_writeb_cmd_nop(val);
477 break;
478 case CMD_FLUSH:
479 trace_esp_mem_writeb_cmd_flush(val);
480
481 s->rregs[ESP_RINTR] = INTR_FC;
482 s->rregs[ESP_RSEQ] = 0;
483 s->rregs[ESP_RFLAGS] = 0;
484 break;
485 case CMD_RESET:
486 trace_esp_mem_writeb_cmd_reset(val);
487 esp_soft_reset(s);
488 break;
489 case CMD_BUSRESET:
490 trace_esp_mem_writeb_cmd_bus_reset(val);
491 s->rregs[ESP_RINTR] = INTR_RST;
492 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
493 esp_raise_irq(s);
494 }
495 break;
496 case CMD_TI:
497 handle_ti(s);
498 break;
499 case CMD_ICCS:
500 trace_esp_mem_writeb_cmd_iccs(val);
501 write_response(s);
502 s->rregs[ESP_RINTR] = INTR_FC;
503 s->rregs[ESP_RSTAT] |= STAT_MI;
504 break;
505 case CMD_MSGACC:
506 trace_esp_mem_writeb_cmd_msgacc(val);
507 s->rregs[ESP_RINTR] = INTR_DC;
508 s->rregs[ESP_RSEQ] = 0;
509 s->rregs[ESP_RFLAGS] = 0;
510 esp_raise_irq(s);
511 break;
512 case CMD_PAD:
513 trace_esp_mem_writeb_cmd_pad(val);
514 s->rregs[ESP_RSTAT] = STAT_TC;
515 s->rregs[ESP_RINTR] = INTR_FC;
516 s->rregs[ESP_RSEQ] = 0;
517 break;
518 case CMD_SATN:
519 trace_esp_mem_writeb_cmd_satn(val);
520 break;
521 case CMD_RSTATN:
522 trace_esp_mem_writeb_cmd_rstatn(val);
523 break;
524 case CMD_SEL:
525 trace_esp_mem_writeb_cmd_sel(val);
526 handle_s_without_atn(s);
527 break;
528 case CMD_SELATN:
529 trace_esp_mem_writeb_cmd_selatn(val);
530 handle_satn(s);
531 break;
532 case CMD_SELATNS:
533 trace_esp_mem_writeb_cmd_selatns(val);
534 handle_satn_stop(s);
535 break;
536 case CMD_ENSEL:
537 trace_esp_mem_writeb_cmd_ensel(val);
538 s->rregs[ESP_RINTR] = 0;
539 break;
540 case CMD_DISSEL:
541 trace_esp_mem_writeb_cmd_dissel(val);
542 s->rregs[ESP_RINTR] = 0;
543 esp_raise_irq(s);
544 break;
545 default:
546 trace_esp_error_unhandled_command(val);
547 break;
548 }
549 break;
550 case ESP_WBUSID ... ESP_WSYNO:
551 break;
552 case ESP_CFG1:
553 case ESP_CFG2: case ESP_CFG3:
554 case ESP_RES3: case ESP_RES4:
555 s->rregs[saddr] = val;
556 break;
557 case ESP_WCCF ... ESP_WTEST:
558 break;
559 default:
560 trace_esp_error_invalid_write(val, saddr);
561 return;
562 }
563 s->wregs[saddr] = val;
564}
565
566static bool esp_mem_accepts(void *opaque, hwaddr addr,
567 unsigned size, bool is_write,
568 MemTxAttrs attrs)
569{
570 return (size == 1) || (is_write && size == 4);
571}
572
573const VMStateDescription vmstate_esp = {
574 .name ="esp",
575 .version_id = 4,
576 .minimum_version_id = 3,
577 .fields = (VMStateField[]) {
578 VMSTATE_BUFFER(rregs, ESPState),
579 VMSTATE_BUFFER(wregs, ESPState),
580 VMSTATE_INT32(ti_size, ESPState),
581 VMSTATE_UINT32(ti_rptr, ESPState),
582 VMSTATE_UINT32(ti_wptr, ESPState),
583 VMSTATE_BUFFER(ti_buf, ESPState),
584 VMSTATE_UINT32(status, ESPState),
585 VMSTATE_UINT32(dma, ESPState),
586 VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
587 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
588 VMSTATE_UINT32(cmdlen, ESPState),
589 VMSTATE_UINT32(do_cmd, ESPState),
590 VMSTATE_UINT32(dma_left, ESPState),
591 VMSTATE_END_OF_LIST()
592 }
593};
594
595static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
596 uint64_t val, unsigned int size)
597{
598 SysBusESPState *sysbus = opaque;
599 uint32_t saddr;
600
601 saddr = addr >> sysbus->it_shift;
602 esp_reg_write(&sysbus->esp, saddr, val);
603}
604
605static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
606 unsigned int size)
607{
608 SysBusESPState *sysbus = opaque;
609 uint32_t saddr;
610
611 saddr = addr >> sysbus->it_shift;
612 return esp_reg_read(&sysbus->esp, saddr);
613}
614
615static const MemoryRegionOps sysbus_esp_mem_ops = {
616 .read = sysbus_esp_mem_read,
617 .write = sysbus_esp_mem_write,
618 .endianness = DEVICE_NATIVE_ENDIAN,
619 .valid.accepts = esp_mem_accepts,
620};
621
622static const struct SCSIBusInfo esp_scsi_info = {
623 .tcq = false,
624 .max_target = ESP_MAX_DEVS,
625 .max_lun = 7,
626
627 .transfer_data = esp_transfer_data,
628 .complete = esp_command_complete,
629 .cancel = esp_request_cancelled
630};
631
632static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
633{
634 SysBusESPState *sysbus = ESP_STATE(opaque);
635 ESPState *s = &sysbus->esp;
636
637 switch (irq) {
638 case 0:
639 parent_esp_reset(s, irq, level);
640 break;
641 case 1:
642 esp_dma_enable(opaque, irq, level);
643 break;
644 }
645}
646
647static void sysbus_esp_realize(DeviceState *dev, Error **errp)
648{
649 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
650 SysBusESPState *sysbus = ESP_STATE(dev);
651 ESPState *s = &sysbus->esp;
652
653 sysbus_init_irq(sbd, &s->irq);
654 assert(sysbus->it_shift != -1);
655
656 s->chip_id = TCHI_FAS100A;
657 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
658 sysbus, "esp", ESP_REGS << sysbus->it_shift);
659 sysbus_init_mmio(sbd, &sysbus->iomem);
660
661 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
662
663 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
664}
665
666static void sysbus_esp_hard_reset(DeviceState *dev)
667{
668 SysBusESPState *sysbus = ESP_STATE(dev);
669 esp_hard_reset(&sysbus->esp);
670}
671
672static const VMStateDescription vmstate_sysbus_esp_scsi = {
673 .name = "sysbusespscsi",
674 .version_id = 0,
675 .minimum_version_id = 0,
676 .fields = (VMStateField[]) {
677 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
678 VMSTATE_END_OF_LIST()
679 }
680};
681
682static void sysbus_esp_class_init(ObjectClass *klass, void *data)
683{
684 DeviceClass *dc = DEVICE_CLASS(klass);
685
686 dc->realize = sysbus_esp_realize;
687 dc->reset = sysbus_esp_hard_reset;
688 dc->vmsd = &vmstate_sysbus_esp_scsi;
689 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
690}
691
692static const TypeInfo sysbus_esp_info = {
693 .name = TYPE_ESP,
694 .parent = TYPE_SYS_BUS_DEVICE,
695 .instance_size = sizeof(SysBusESPState),
696 .class_init = sysbus_esp_class_init,
697};
698
699static void esp_register_types(void)
700{
701 type_register_static(&sysbus_esp_info);
702}
703
704type_init(esp_register_types)
705
