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24#include "qemu/osdep.h"
25#include "qemu/units.h"
26#include "qemu/error-report.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "cpu.h"
30#include "hw/hw.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/pci_bridge.h"
33#include "hw/pci/pci_bus.h"
34#include "hw/pci/pci_host.h"
35#include "hw/pci-host/sabre.h"
36#include "hw/i386/pc.h"
37#include "hw/char/serial.h"
38#include "hw/char/parallel.h"
39#include "hw/timer/m48t59.h"
40#include "hw/input/i8042.h"
41#include "hw/block/fdc.h"
42#include "net/net.h"
43#include "qemu/timer.h"
44#include "sysemu/sysemu.h"
45#include "hw/boards.h"
46#include "hw/nvram/sun_nvram.h"
47#include "hw/nvram/chrp_nvram.h"
48#include "hw/sparc/sparc64.h"
49#include "hw/nvram/fw_cfg.h"
50#include "hw/sysbus.h"
51#include "hw/ide.h"
52#include "hw/ide/pci.h"
53#include "hw/loader.h"
54#include "hw/fw-path-provider.h"
55#include "elf.h"
56#include "trace.h"
57
58#define KERNEL_LOAD_ADDR 0x00404000
59#define CMDLINE_ADDR 0x003ff000
60#define PROM_SIZE_MAX (4 * MiB)
61#define PROM_VADDR 0x000ffd00000ULL
62#define PBM_SPECIAL_BASE 0x1fe00000000ULL
63#define PBM_MEM_BASE 0x1ff00000000ULL
64#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
65#define PROM_FILENAME "openbios-sparc64"
66#define NVRAM_SIZE 0x2000
67#define MAX_IDE_BUS 2
68#define BIOS_CFG_IOPORT 0x510
69#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
70#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
71#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
72
73#define IVEC_MAX 0x40
74
75struct hwdef {
76 uint16_t machine_id;
77 uint64_t prom_addr;
78 uint64_t console_serial_base;
79};
80
81typedef struct EbusState {
82
83 PCIDevice parent_obj;
84
85 ISABus *isa_bus;
86 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
87 uint64_t console_serial_base;
88 MemoryRegion bar0;
89 MemoryRegion bar1;
90} EbusState;
91
92#define TYPE_EBUS "ebus"
93#define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
94
95static void fw_cfg_boot_set(void *opaque, const char *boot_device,
96 Error **errp)
97{
98 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
99}
100
101static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
102 const char *arch, ram_addr_t RAM_size,
103 const char *boot_devices,
104 uint32_t kernel_image, uint32_t kernel_size,
105 const char *cmdline,
106 uint32_t initrd_image, uint32_t initrd_size,
107 uint32_t NVRAM_image,
108 int width, int height, int depth,
109 const uint8_t *macaddr)
110{
111 unsigned int i;
112 int sysp_end;
113 uint8_t image[0x1ff0];
114 NvramClass *k = NVRAM_GET_CLASS(nvram);
115
116 memset(image, '\0', sizeof(image));
117
118
119 sysp_end = chrp_nvram_create_system_partition(image, 0);
120
121
122 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
123
124 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
125
126 for (i = 0; i < sizeof(image); i++) {
127 (k->write)(nvram, i, image[i]);
128 }
129
130 return 0;
131}
132
133static uint64_t sun4u_load_kernel(const char *kernel_filename,
134 const char *initrd_filename,
135 ram_addr_t RAM_size, uint64_t *initrd_size,
136 uint64_t *initrd_addr, uint64_t *kernel_addr,
137 uint64_t *kernel_entry)
138{
139 int linux_boot;
140 unsigned int i;
141 long kernel_size;
142 uint8_t *ptr;
143 uint64_t kernel_top = 0;
144
145 linux_boot = (kernel_filename != NULL);
146
147 kernel_size = 0;
148 if (linux_boot) {
149 int bswap_needed;
150
151#ifdef BSWAP_NEEDED
152 bswap_needed = 1;
153#else
154 bswap_needed = 0;
155#endif
156 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
157 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
158 if (kernel_size < 0) {
159 *kernel_addr = KERNEL_LOAD_ADDR;
160 *kernel_entry = KERNEL_LOAD_ADDR;
161 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
162 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
163 TARGET_PAGE_SIZE);
164 }
165 if (kernel_size < 0) {
166 kernel_size = load_image_targphys(kernel_filename,
167 KERNEL_LOAD_ADDR,
168 RAM_size - KERNEL_LOAD_ADDR);
169 }
170 if (kernel_size < 0) {
171 error_report("could not load kernel '%s'", kernel_filename);
172 exit(1);
173 }
174
175 *initrd_size = 0;
176 if (initrd_filename && kernel_top) {
177 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
178
179 *initrd_size = load_image_targphys(initrd_filename,
180 *initrd_addr,
181 RAM_size - *initrd_addr);
182 if ((int)*initrd_size < 0) {
183 error_report("could not load initial ram disk '%s'",
184 initrd_filename);
185 exit(1);
186 }
187 }
188 if (*initrd_size > 0) {
189 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
190 ptr = rom_ptr(*kernel_addr + i, 32);
191 if (ptr && ldl_p(ptr + 8) == 0x48647253) {
192 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
193 stl_p(ptr + 28, *initrd_size);
194 break;
195 }
196 }
197 }
198 }
199 return kernel_size;
200}
201
202typedef struct ResetData {
203 SPARCCPU *cpu;
204 uint64_t prom_addr;
205} ResetData;
206
207#define TYPE_SUN4U_POWER "power"
208#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
209
210typedef struct PowerDevice {
211 SysBusDevice parent_obj;
212
213 MemoryRegion power_mmio;
214} PowerDevice;
215
216
217static void power_mem_write(void *opaque, hwaddr addr,
218 uint64_t val, unsigned size)
219{
220
221 if (val & 0x1000000) {
222 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
223 }
224}
225
226static const MemoryRegionOps power_mem_ops = {
227 .write = power_mem_write,
228 .endianness = DEVICE_NATIVE_ENDIAN,
229 .valid = {
230 .min_access_size = 4,
231 .max_access_size = 4,
232 },
233};
234
235static void power_realize(DeviceState *dev, Error **errp)
236{
237 PowerDevice *d = SUN4U_POWER(dev);
238 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
239
240 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
241 "power", sizeof(uint32_t));
242
243 sysbus_init_mmio(sbd, &d->power_mmio);
244}
245
246static void power_class_init(ObjectClass *klass, void *data)
247{
248 DeviceClass *dc = DEVICE_CLASS(klass);
249
250 dc->realize = power_realize;
251}
252
253static const TypeInfo power_info = {
254 .name = TYPE_SUN4U_POWER,
255 .parent = TYPE_SYS_BUS_DEVICE,
256 .instance_size = sizeof(PowerDevice),
257 .class_init = power_class_init,
258};
259
260static void ebus_isa_irq_handler(void *opaque, int n, int level)
261{
262 EbusState *s = EBUS(opaque);
263 qemu_irq irq = s->isa_bus_irqs[n];
264
265
266 trace_ebus_isa_irq_handler(n, level);
267 if (irq) {
268 qemu_set_irq(irq, level);
269 }
270}
271
272
273static void ebus_realize(PCIDevice *pci_dev, Error **errp)
274{
275 EbusState *s = EBUS(pci_dev);
276 SysBusDevice *sbd;
277 DeviceState *dev;
278 qemu_irq *isa_irq;
279 DriveInfo *fd[MAX_FD];
280 int i;
281
282 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
283 pci_address_space_io(pci_dev), errp);
284 if (!s->isa_bus) {
285 error_setg(errp, "unable to instantiate EBUS ISA bus");
286 return;
287 }
288
289
290 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
291 isa_bus_irqs(s->isa_bus, isa_irq);
292 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
293 ISA_NUM_IRQS);
294
295
296 i = 0;
297 if (s->console_serial_base) {
298 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
299 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
300 i++;
301 }
302 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
303
304
305 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
306
307
308 isa_create_simple(s->isa_bus, "i8042");
309
310
311 for (i = 0; i < MAX_FD; i++) {
312 fd[i] = drive_get(IF_FLOPPY, 0, i);
313 }
314 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
315 if (fd[0]) {
316 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
317 &error_abort);
318 }
319 if (fd[1]) {
320 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
321 &error_abort);
322 }
323 qdev_prop_set_uint32(dev, "dma", -1);
324 qdev_init_nofail(dev);
325
326
327 dev = qdev_create(NULL, TYPE_SUN4U_POWER);
328 qdev_init_nofail(dev);
329 sbd = SYS_BUS_DEVICE(dev);
330 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
331 sysbus_mmio_get_region(sbd, 0));
332
333
334 pci_dev->config[0x04] = 0x06;
335 pci_dev->config[0x05] = 0x00;
336 pci_dev->config[0x06] = 0xa0;
337 pci_dev->config[0x07] = 0x03;
338 pci_dev->config[0x09] = 0x00;
339 pci_dev->config[0x0D] = 0x0a;
340
341 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
342 0, 0x1000000);
343 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
344 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
345 0, 0x8000);
346 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
347}
348
349static Property ebus_properties[] = {
350 DEFINE_PROP_UINT64("console-serial-base", EbusState,
351 console_serial_base, 0),
352 DEFINE_PROP_END_OF_LIST(),
353};
354
355static void ebus_class_init(ObjectClass *klass, void *data)
356{
357 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
358 DeviceClass *dc = DEVICE_CLASS(klass);
359
360 k->realize = ebus_realize;
361 k->vendor_id = PCI_VENDOR_ID_SUN;
362 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
363 k->revision = 0x01;
364 k->class_id = PCI_CLASS_BRIDGE_OTHER;
365 dc->props = ebus_properties;
366}
367
368static const TypeInfo ebus_info = {
369 .name = TYPE_EBUS,
370 .parent = TYPE_PCI_DEVICE,
371 .class_init = ebus_class_init,
372 .instance_size = sizeof(EbusState),
373 .interfaces = (InterfaceInfo[]) {
374 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
375 { },
376 },
377};
378
379#define TYPE_OPENPROM "openprom"
380#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
381
382typedef struct PROMState {
383 SysBusDevice parent_obj;
384
385 MemoryRegion prom;
386} PROMState;
387
388static uint64_t translate_prom_address(void *opaque, uint64_t addr)
389{
390 hwaddr *base_addr = (hwaddr *)opaque;
391 return addr + *base_addr - PROM_VADDR;
392}
393
394
395static void prom_init(hwaddr addr, const char *bios_name)
396{
397 DeviceState *dev;
398 SysBusDevice *s;
399 char *filename;
400 int ret;
401
402 dev = qdev_create(NULL, TYPE_OPENPROM);
403 qdev_init_nofail(dev);
404 s = SYS_BUS_DEVICE(dev);
405
406 sysbus_mmio_map(s, 0, addr);
407
408
409 if (bios_name == NULL) {
410 bios_name = PROM_FILENAME;
411 }
412 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
413 if (filename) {
414 ret = load_elf(filename, translate_prom_address, &addr,
415 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
416 if (ret < 0 || ret > PROM_SIZE_MAX) {
417 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
418 }
419 g_free(filename);
420 } else {
421 ret = -1;
422 }
423 if (ret < 0 || ret > PROM_SIZE_MAX) {
424 error_report("could not load prom '%s'", bios_name);
425 exit(1);
426 }
427}
428
429static void prom_realize(DeviceState *ds, Error **errp)
430{
431 PROMState *s = OPENPROM(ds);
432 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
433 Error *local_err = NULL;
434
435 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
436 PROM_SIZE_MAX, &local_err);
437 if (local_err) {
438 error_propagate(errp, local_err);
439 return;
440 }
441
442 vmstate_register_ram_global(&s->prom);
443 memory_region_set_readonly(&s->prom, true);
444 sysbus_init_mmio(dev, &s->prom);
445}
446
447static Property prom_properties[] = {
448 {},
449};
450
451static void prom_class_init(ObjectClass *klass, void *data)
452{
453 DeviceClass *dc = DEVICE_CLASS(klass);
454
455 dc->props = prom_properties;
456 dc->realize = prom_realize;
457}
458
459static const TypeInfo prom_info = {
460 .name = TYPE_OPENPROM,
461 .parent = TYPE_SYS_BUS_DEVICE,
462 .instance_size = sizeof(PROMState),
463 .class_init = prom_class_init,
464};
465
466
467#define TYPE_SUN4U_MEMORY "memory"
468#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
469
470typedef struct RamDevice {
471 SysBusDevice parent_obj;
472
473 MemoryRegion ram;
474 uint64_t size;
475} RamDevice;
476
477
478static void ram_realize(DeviceState *dev, Error **errp)
479{
480 RamDevice *d = SUN4U_RAM(dev);
481 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
482
483 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
484 &error_fatal);
485 vmstate_register_ram_global(&d->ram);
486 sysbus_init_mmio(sbd, &d->ram);
487}
488
489static void ram_init(hwaddr addr, ram_addr_t RAM_size)
490{
491 DeviceState *dev;
492 SysBusDevice *s;
493 RamDevice *d;
494
495
496 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
497 s = SYS_BUS_DEVICE(dev);
498
499 d = SUN4U_RAM(dev);
500 d->size = RAM_size;
501 qdev_init_nofail(dev);
502
503 sysbus_mmio_map(s, 0, addr);
504}
505
506static Property ram_properties[] = {
507 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
508 DEFINE_PROP_END_OF_LIST(),
509};
510
511static void ram_class_init(ObjectClass *klass, void *data)
512{
513 DeviceClass *dc = DEVICE_CLASS(klass);
514
515 dc->realize = ram_realize;
516 dc->props = ram_properties;
517}
518
519static const TypeInfo ram_info = {
520 .name = TYPE_SUN4U_MEMORY,
521 .parent = TYPE_SYS_BUS_DEVICE,
522 .instance_size = sizeof(RamDevice),
523 .class_init = ram_class_init,
524};
525
526static void sun4uv_init(MemoryRegion *address_space_mem,
527 MachineState *machine,
528 const struct hwdef *hwdef)
529{
530 SPARCCPU *cpu;
531 Nvram *nvram;
532 unsigned int i;
533 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
534 SabreState *sabre;
535 PCIBus *pci_bus, *pci_busA, *pci_busB;
536 PCIDevice *ebus, *pci_dev;
537 SysBusDevice *s;
538 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
539 DeviceState *iommu, *dev;
540 FWCfgState *fw_cfg;
541 NICInfo *nd;
542 MACAddr macaddr;
543 bool onboard_nic;
544
545
546 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
547
548
549 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
550 qdev_init_nofail(iommu);
551
552
553 ram_init(0, machine->ram_size);
554
555 prom_init(hwdef->prom_addr, bios_name);
556
557
558 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
559 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
560 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
561 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
562 &error_abort);
563 qdev_init_nofail(DEVICE(sabre));
564
565
566 for (i = 0; i < IVEC_MAX; i++) {
567 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
568 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
569 }
570
571 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
572 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
573 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
574
575
576
577
578 pci_bus->slot_reserved_mask = 0xfffffffc;
579 pci_busA->slot_reserved_mask = 0xfffffff1;
580 pci_busB->slot_reserved_mask = 0xfffffff0;
581
582 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
583 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
584 hwdef->console_serial_base);
585 qdev_init_nofail(DEVICE(ebus));
586
587
588 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
589 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
590 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
591 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
592 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
593 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
594 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
595 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
596 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
597 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
598
599 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
600
601 memset(&macaddr, 0, sizeof(MACAddr));
602 onboard_nic = false;
603 for (i = 0; i < nb_nics; i++) {
604 nd = &nd_table[i];
605
606 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
607 if (!onboard_nic) {
608 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
609 true, "sunhme");
610 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
611 onboard_nic = true;
612 } else {
613 pci_dev = pci_create(pci_busB, -1, "sunhme");
614 }
615 } else {
616 pci_dev = pci_create(pci_busB, -1, nd->model);
617 }
618
619 dev = &pci_dev->qdev;
620 qdev_set_nic_properties(dev, nd);
621 qdev_init_nofail(dev);
622 }
623
624
625
626 if (!onboard_nic) {
627 qemu_macaddr_default_if_unset(&macaddr);
628 }
629
630 ide_drive_get(hd, ARRAY_SIZE(hd));
631
632 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
633 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
634 qdev_init_nofail(&pci_dev->qdev);
635 pci_ide_create_devs(pci_dev, hd);
636
637
638 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
639 s = SYS_BUS_DEVICE(nvram);
640 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
641 sysbus_mmio_get_region(s, 0));
642
643 initrd_size = 0;
644 initrd_addr = 0;
645 kernel_size = sun4u_load_kernel(machine->kernel_filename,
646 machine->initrd_filename,
647 ram_size, &initrd_size, &initrd_addr,
648 &kernel_addr, &kernel_entry);
649
650 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
651 machine->boot_order,
652 kernel_addr, kernel_size,
653 machine->kernel_cmdline,
654 initrd_addr, initrd_size,
655
656 0,
657 graphic_width, graphic_height, graphic_depth,
658 (uint8_t *)&macaddr);
659
660 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
661 qdev_prop_set_bit(dev, "dma_enabled", false);
662 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
663 qdev_init_nofail(dev);
664 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
665 &FW_CFG_IO(dev)->comb_iomem);
666
667 fw_cfg = FW_CFG(dev);
668 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
669 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
670 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
671 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
672 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
673 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
674 if (machine->kernel_cmdline) {
675 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
676 strlen(machine->kernel_cmdline) + 1);
677 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
678 } else {
679 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
680 }
681 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
682 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
683 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
684
685 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
686 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
687 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
688
689 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
690}
691
692enum {
693 sun4u_id = 0,
694 sun4v_id = 64,
695};
696
697
698
699
700
701static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
702 DeviceState *dev)
703{
704 PCIDevice *pci;
705 IDEBus *ide_bus;
706 IDEState *ide_s;
707 int bus_id;
708
709 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
710 pci = PCI_DEVICE(dev);
711
712 if (PCI_FUNC(pci->devfn)) {
713 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
714 PCI_FUNC(pci->devfn));
715 } else {
716 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
717 }
718 }
719
720 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
721 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
722 ide_s = idebus_active_if(ide_bus);
723 bus_id = ide_bus->bus_id;
724
725 if (ide_s->drive_kind == IDE_CD) {
726 return g_strdup_printf("ide@%x/cdrom", bus_id);
727 }
728
729 return g_strdup_printf("ide@%x/disk", bus_id);
730 }
731
732 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
733 return g_strdup("disk");
734 }
735
736 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
737 return g_strdup("cdrom");
738 }
739
740 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
741 return g_strdup("disk");
742 }
743
744 return NULL;
745}
746
747static const struct hwdef hwdefs[] = {
748
749 {
750 .machine_id = sun4u_id,
751 .prom_addr = 0x1fff0000000ULL,
752 .console_serial_base = 0,
753 },
754
755 {
756 .machine_id = sun4v_id,
757 .prom_addr = 0x1fff0000000ULL,
758 .console_serial_base = 0,
759 },
760};
761
762
763static void sun4u_init(MachineState *machine)
764{
765 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
766}
767
768
769static void sun4v_init(MachineState *machine)
770{
771 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
772}
773
774static void sun4u_class_init(ObjectClass *oc, void *data)
775{
776 MachineClass *mc = MACHINE_CLASS(oc);
777 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
778
779 mc->desc = "Sun4u platform";
780 mc->init = sun4u_init;
781 mc->block_default_type = IF_IDE;
782 mc->max_cpus = 1;
783 mc->is_default = 1;
784 mc->default_boot_order = "c";
785 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
786 mc->ignore_boot_device_suffixes = true;
787 fwc->get_dev_path = sun4u_fw_dev_path;
788}
789
790static const TypeInfo sun4u_type = {
791 .name = MACHINE_TYPE_NAME("sun4u"),
792 .parent = TYPE_MACHINE,
793 .class_init = sun4u_class_init,
794 .interfaces = (InterfaceInfo[]) {
795 { TYPE_FW_PATH_PROVIDER },
796 { }
797 },
798};
799
800static void sun4v_class_init(ObjectClass *oc, void *data)
801{
802 MachineClass *mc = MACHINE_CLASS(oc);
803
804 mc->desc = "Sun4v platform";
805 mc->init = sun4v_init;
806 mc->block_default_type = IF_IDE;
807 mc->max_cpus = 1;
808 mc->default_boot_order = "c";
809 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
810}
811
812static const TypeInfo sun4v_type = {
813 .name = MACHINE_TYPE_NAME("sun4v"),
814 .parent = TYPE_MACHINE,
815 .class_init = sun4v_class_init,
816};
817
818static void sun4u_register_types(void)
819{
820 type_register_static(&power_info);
821 type_register_static(&ebus_info);
822 type_register_static(&prom_info);
823 type_register_static(&ram_info);
824
825 type_register_static(&sun4u_type);
826 type_register_static(&sun4v_type);
827}
828
829type_init(sun4u_register_types)
830
